tqm8560.dts 8.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382
  1. /*
  2. * TQM 8560 Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor Inc.
  5. * Copyright 2008 Wolfgang Grandegger <wg@grandegger.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify it
  8. * under the terms of the GNU General Public License as published by the
  9. * Free Software Foundation; either version 2 of the License, or (at your
  10. * option) any later version.
  11. */
  12. /dts-v1/;
  13. / {
  14. model = "tqc,tqm8560";
  15. compatible = "tqc,tqm8560";
  16. #address-cells = <1>;
  17. #size-cells = <1>;
  18. aliases {
  19. ethernet0 = &enet0;
  20. ethernet1 = &enet1;
  21. ethernet2 = &enet2;
  22. serial0 = &serial0;
  23. serial1 = &serial1;
  24. pci0 = &pci0;
  25. };
  26. cpus {
  27. #address-cells = <1>;
  28. #size-cells = <0>;
  29. PowerPC,8560@0 {
  30. device_type = "cpu";
  31. reg = <0>;
  32. d-cache-line-size = <32>;
  33. i-cache-line-size = <32>;
  34. d-cache-size = <32768>;
  35. i-cache-size = <32768>;
  36. timebase-frequency = <0>;
  37. bus-frequency = <0>;
  38. clock-frequency = <0>;
  39. next-level-cache = <&L2>;
  40. };
  41. };
  42. memory {
  43. device_type = "memory";
  44. reg = <0x00000000 0x10000000>;
  45. };
  46. soc@e0000000 {
  47. #address-cells = <1>;
  48. #size-cells = <1>;
  49. device_type = "soc";
  50. ranges = <0x0 0xe0000000 0x100000>;
  51. reg = <0xe0000000 0x200>;
  52. bus-frequency = <0>;
  53. compatible = "fsl,mpc8560-immr", "simple-bus";
  54. memory-controller@2000 {
  55. compatible = "fsl,mpc8540-memory-controller";
  56. reg = <0x2000 0x1000>;
  57. interrupt-parent = <&mpic>;
  58. interrupts = <18 2>;
  59. };
  60. L2: l2-cache-controller@20000 {
  61. compatible = "fsl,mpc8540-l2-cache-controller";
  62. reg = <0x20000 0x1000>;
  63. cache-line-size = <32>;
  64. cache-size = <0x40000>; // L2, 256K
  65. interrupt-parent = <&mpic>;
  66. interrupts = <16 2>;
  67. };
  68. i2c@3000 {
  69. #address-cells = <1>;
  70. #size-cells = <0>;
  71. cell-index = <0>;
  72. compatible = "fsl-i2c";
  73. reg = <0x3000 0x100>;
  74. interrupts = <43 2>;
  75. interrupt-parent = <&mpic>;
  76. dfsrr;
  77. dtt@50 {
  78. compatible = "national,lm75";
  79. reg = <0x50>;
  80. };
  81. rtc@68 {
  82. compatible = "dallas,ds1337";
  83. reg = <0x68>;
  84. };
  85. };
  86. dma@21300 {
  87. #address-cells = <1>;
  88. #size-cells = <1>;
  89. compatible = "fsl,mpc8560-dma", "fsl,eloplus-dma";
  90. reg = <0x21300 0x4>;
  91. ranges = <0x0 0x21100 0x200>;
  92. cell-index = <0>;
  93. dma-channel@0 {
  94. compatible = "fsl,mpc8560-dma-channel",
  95. "fsl,eloplus-dma-channel";
  96. reg = <0x0 0x80>;
  97. cell-index = <0>;
  98. interrupt-parent = <&mpic>;
  99. interrupts = <20 2>;
  100. };
  101. dma-channel@80 {
  102. compatible = "fsl,mpc8560-dma-channel",
  103. "fsl,eloplus-dma-channel";
  104. reg = <0x80 0x80>;
  105. cell-index = <1>;
  106. interrupt-parent = <&mpic>;
  107. interrupts = <21 2>;
  108. };
  109. dma-channel@100 {
  110. compatible = "fsl,mpc8560-dma-channel",
  111. "fsl,eloplus-dma-channel";
  112. reg = <0x100 0x80>;
  113. cell-index = <2>;
  114. interrupt-parent = <&mpic>;
  115. interrupts = <22 2>;
  116. };
  117. dma-channel@180 {
  118. compatible = "fsl,mpc8560-dma-channel",
  119. "fsl,eloplus-dma-channel";
  120. reg = <0x180 0x80>;
  121. cell-index = <3>;
  122. interrupt-parent = <&mpic>;
  123. interrupts = <23 2>;
  124. };
  125. };
  126. enet0: ethernet@24000 {
  127. #address-cells = <1>;
  128. #size-cells = <1>;
  129. cell-index = <0>;
  130. device_type = "network";
  131. model = "TSEC";
  132. compatible = "gianfar";
  133. reg = <0x24000 0x1000>;
  134. ranges = <0x0 0x24000 0x1000>;
  135. local-mac-address = [ 00 00 00 00 00 00 ];
  136. interrupts = <29 2 30 2 34 2>;
  137. interrupt-parent = <&mpic>;
  138. tbi-handle = <&tbi0>;
  139. phy-handle = <&phy2>;
  140. mdio@520 {
  141. #address-cells = <1>;
  142. #size-cells = <0>;
  143. compatible = "fsl,gianfar-mdio";
  144. reg = <0x520 0x20>;
  145. phy1: ethernet-phy@1 {
  146. interrupt-parent = <&mpic>;
  147. interrupts = <8 1>;
  148. reg = <1>;
  149. device_type = "ethernet-phy";
  150. };
  151. phy2: ethernet-phy@2 {
  152. interrupt-parent = <&mpic>;
  153. interrupts = <8 1>;
  154. reg = <2>;
  155. device_type = "ethernet-phy";
  156. };
  157. phy3: ethernet-phy@3 {
  158. interrupt-parent = <&mpic>;
  159. interrupts = <8 1>;
  160. reg = <3>;
  161. device_type = "ethernet-phy";
  162. };
  163. tbi0: tbi-phy@11 {
  164. reg = <0x11>;
  165. device_type = "tbi-phy";
  166. };
  167. };
  168. };
  169. enet1: ethernet@25000 {
  170. #address-cells = <1>;
  171. #size-cells = <1>;
  172. cell-index = <1>;
  173. device_type = "network";
  174. model = "TSEC";
  175. compatible = "gianfar";
  176. reg = <0x25000 0x1000>;
  177. ranges = <0x0 0x25000 0x1000>;
  178. local-mac-address = [ 00 00 00 00 00 00 ];
  179. interrupts = <35 2 36 2 40 2>;
  180. interrupt-parent = <&mpic>;
  181. tbi-handle = <&tbi1>;
  182. phy-handle = <&phy1>;
  183. mdio@520 {
  184. #address-cells = <1>;
  185. #size-cells = <0>;
  186. compatible = "fsl,gianfar-tbi";
  187. reg = <0x520 0x20>;
  188. tbi1: tbi-phy@11 {
  189. reg = <0x11>;
  190. device_type = "tbi-phy";
  191. };
  192. };
  193. };
  194. mpic: pic@40000 {
  195. interrupt-controller;
  196. #address-cells = <0>;
  197. #interrupt-cells = <2>;
  198. reg = <0x40000 0x40000>;
  199. device_type = "open-pic";
  200. compatible = "chrp,open-pic";
  201. };
  202. cpm@919c0 {
  203. #address-cells = <1>;
  204. #size-cells = <1>;
  205. compatible = "fsl,mpc8560-cpm", "fsl,cpm2", "simple-bus";
  206. reg = <0x919c0 0x30>;
  207. ranges;
  208. muram@80000 {
  209. #address-cells = <1>;
  210. #size-cells = <1>;
  211. ranges = <0 0x80000 0x10000>;
  212. data@0 {
  213. compatible = "fsl,cpm-muram-data";
  214. reg = <0 0x4000 0x9000 0x2000>;
  215. };
  216. };
  217. brg@919f0 {
  218. compatible = "fsl,mpc8560-brg",
  219. "fsl,cpm2-brg",
  220. "fsl,cpm-brg";
  221. reg = <0x919f0 0x10 0x915f0 0x10>;
  222. clock-frequency = <0>;
  223. };
  224. cpmpic: pic@90c00 {
  225. interrupt-controller;
  226. #address-cells = <0>;
  227. #interrupt-cells = <2>;
  228. interrupts = <46 2>;
  229. interrupt-parent = <&mpic>;
  230. reg = <0x90c00 0x80>;
  231. compatible = "fsl,mpc8560-cpm-pic", "fsl,cpm2-pic";
  232. };
  233. serial0: serial@91a00 {
  234. device_type = "serial";
  235. compatible = "fsl,mpc8560-scc-uart",
  236. "fsl,cpm2-scc-uart";
  237. reg = <0x91a00 0x20 0x88000 0x100>;
  238. fsl,cpm-brg = <1>;
  239. fsl,cpm-command = <0x800000>;
  240. current-speed = <115200>;
  241. interrupts = <40 8>;
  242. interrupt-parent = <&cpmpic>;
  243. };
  244. serial1: serial@91a20 {
  245. device_type = "serial";
  246. compatible = "fsl,mpc8560-scc-uart",
  247. "fsl,cpm2-scc-uart";
  248. reg = <0x91a20 0x20 0x88100 0x100>;
  249. fsl,cpm-brg = <2>;
  250. fsl,cpm-command = <0x4a00000>;
  251. current-speed = <115200>;
  252. interrupts = <41 8>;
  253. interrupt-parent = <&cpmpic>;
  254. };
  255. enet2: ethernet@91340 {
  256. device_type = "network";
  257. compatible = "fsl,mpc8560-fcc-enet",
  258. "fsl,cpm2-fcc-enet";
  259. reg = <0x91340 0x20 0x88600 0x100 0x913d0 0x1>;
  260. local-mac-address = [ 00 00 00 00 00 00 ];
  261. fsl,cpm-command = <0x1a400300>;
  262. interrupts = <34 8>;
  263. interrupt-parent = <&cpmpic>;
  264. phy-handle = <&phy3>;
  265. };
  266. };
  267. };
  268. localbus@e0005000 {
  269. compatible = "fsl,mpc8560-localbus", "fsl,pq3-localbus",
  270. "simple-bus";
  271. #address-cells = <2>;
  272. #size-cells = <1>;
  273. reg = <0xe0005000 0x100>; // BRx, ORx, etc.
  274. ranges = <
  275. 0 0x0 0xfc000000 0x04000000 // NOR FLASH bank 1
  276. 1 0x0 0xf8000000 0x08000000 // NOR FLASH bank 0
  277. 2 0x0 0xe3000000 0x00008000 // CAN (2 x i82527)
  278. >;
  279. flash@1,0 {
  280. #address-cells = <1>;
  281. #size-cells = <1>;
  282. compatible = "cfi-flash";
  283. reg = <1 0x0 0x8000000>;
  284. bank-width = <4>;
  285. device-width = <1>;
  286. partition@0 {
  287. label = "kernel";
  288. reg = <0x00000000 0x00200000>;
  289. };
  290. partition@200000 {
  291. label = "root";
  292. reg = <0x00200000 0x00300000>;
  293. };
  294. partition@500000 {
  295. label = "user";
  296. reg = <0x00500000 0x07a00000>;
  297. };
  298. partition@7f00000 {
  299. label = "env1";
  300. reg = <0x07f00000 0x00040000>;
  301. };
  302. partition@7f40000 {
  303. label = "env2";
  304. reg = <0x07f40000 0x00040000>;
  305. };
  306. partition@7f80000 {
  307. label = "u-boot";
  308. reg = <0x07f80000 0x00080000>;
  309. read-only;
  310. };
  311. };
  312. /* Note: CAN support needs be enabled in U-Boot */
  313. can0@2,0 {
  314. compatible = "intel,82527"; // Bosch CC770
  315. reg = <2 0x0 0x100>;
  316. interrupts = <4 1>;
  317. interrupt-parent = <&mpic>;
  318. };
  319. can1@2,100 {
  320. compatible = "intel,82527"; // Bosch CC770
  321. reg = <2 0x100 0x100>;
  322. interrupts = <4 1>;
  323. interrupt-parent = <&mpic>;
  324. };
  325. };
  326. pci0: pci@e0008000 {
  327. cell-index = <0>;
  328. #interrupt-cells = <1>;
  329. #size-cells = <2>;
  330. #address-cells = <3>;
  331. compatible = "fsl,mpc8540-pcix", "fsl,mpc8540-pci";
  332. device_type = "pci";
  333. reg = <0xe0008000 0x1000>;
  334. clock-frequency = <66666666>;
  335. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  336. interrupt-map = <
  337. /* IDSEL 28 */
  338. 0xe000 0 0 1 &mpic 2 1
  339. 0xe000 0 0 2 &mpic 3 1>;
  340. interrupt-parent = <&mpic>;
  341. interrupts = <24 2>;
  342. bus-range = <0 0>;
  343. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x20000000
  344. 0x01000000 0 0x00000000 0xe2000000 0 0x01000000>;
  345. };
  346. };