mpc8536ds.dts 10 KB

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  1. /*
  2. * MPC8536 DS Device Tree Source
  3. *
  4. * Copyright 2008 Freescale Semiconductor, Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License as published by the
  8. * Free Software Foundation; either version 2 of the License, or (at your
  9. * option) any later version.
  10. */
  11. /dts-v1/;
  12. / {
  13. model = "fsl,mpc8536ds";
  14. compatible = "fsl,mpc8536ds";
  15. #address-cells = <1>;
  16. #size-cells = <1>;
  17. aliases {
  18. ethernet0 = &enet0;
  19. ethernet1 = &enet1;
  20. serial0 = &serial0;
  21. serial1 = &serial1;
  22. pci0 = &pci0;
  23. pci1 = &pci1;
  24. pci2 = &pci2;
  25. pci3 = &pci3;
  26. };
  27. cpus {
  28. #cpus = <1>;
  29. #address-cells = <1>;
  30. #size-cells = <0>;
  31. PowerPC,8536@0 {
  32. device_type = "cpu";
  33. reg = <0>;
  34. next-level-cache = <&L2>;
  35. };
  36. };
  37. memory {
  38. device_type = "memory";
  39. reg = <00000000 00000000>; // Filled by U-Boot
  40. };
  41. soc@ffe00000 {
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. device_type = "soc";
  45. compatible = "simple-bus";
  46. ranges = <0x0 0xffe00000 0x100000>;
  47. reg = <0xffe00000 0x1000>;
  48. bus-frequency = <0>; // Filled out by uboot.
  49. memory-controller@2000 {
  50. compatible = "fsl,mpc8536-memory-controller";
  51. reg = <0x2000 0x1000>;
  52. interrupt-parent = <&mpic>;
  53. interrupts = <18 0x2>;
  54. };
  55. L2: l2-cache-controller@20000 {
  56. compatible = "fsl,mpc8536-l2-cache-controller";
  57. reg = <0x20000 0x1000>;
  58. interrupt-parent = <&mpic>;
  59. interrupts = <16 0x2>;
  60. };
  61. i2c@3000 {
  62. #address-cells = <1>;
  63. #size-cells = <0>;
  64. cell-index = <0>;
  65. compatible = "fsl-i2c";
  66. reg = <0x3000 0x100>;
  67. interrupts = <43 0x2>;
  68. interrupt-parent = <&mpic>;
  69. dfsrr;
  70. };
  71. i2c@3100 {
  72. #address-cells = <1>;
  73. #size-cells = <0>;
  74. cell-index = <1>;
  75. compatible = "fsl-i2c";
  76. reg = <0x3100 0x100>;
  77. interrupts = <43 0x2>;
  78. interrupt-parent = <&mpic>;
  79. dfsrr;
  80. rtc@68 {
  81. compatible = "dallas,ds3232";
  82. reg = <0x68>;
  83. interrupts = <0 0x1>;
  84. interrupt-parent = <&mpic>;
  85. };
  86. };
  87. dma@21300 {
  88. #address-cells = <1>;
  89. #size-cells = <1>;
  90. compatible = "fsl,mpc8536-dma", "fsl,eloplus-dma";
  91. reg = <0x21300 4>;
  92. ranges = <0 0x21100 0x200>;
  93. cell-index = <0>;
  94. dma-channel@0 {
  95. compatible = "fsl,mpc8536-dma-channel",
  96. "fsl,eloplus-dma-channel";
  97. reg = <0x0 0x80>;
  98. cell-index = <0>;
  99. interrupt-parent = <&mpic>;
  100. interrupts = <20 2>;
  101. };
  102. dma-channel@80 {
  103. compatible = "fsl,mpc8536-dma-channel",
  104. "fsl,eloplus-dma-channel";
  105. reg = <0x80 0x80>;
  106. cell-index = <1>;
  107. interrupt-parent = <&mpic>;
  108. interrupts = <21 2>;
  109. };
  110. dma-channel@100 {
  111. compatible = "fsl,mpc8536-dma-channel",
  112. "fsl,eloplus-dma-channel";
  113. reg = <0x100 0x80>;
  114. cell-index = <2>;
  115. interrupt-parent = <&mpic>;
  116. interrupts = <22 2>;
  117. };
  118. dma-channel@180 {
  119. compatible = "fsl,mpc8536-dma-channel",
  120. "fsl,eloplus-dma-channel";
  121. reg = <0x180 0x80>;
  122. cell-index = <3>;
  123. interrupt-parent = <&mpic>;
  124. interrupts = <23 2>;
  125. };
  126. };
  127. usb@22000 {
  128. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  129. reg = <0x22000 0x1000>;
  130. #address-cells = <1>;
  131. #size-cells = <0>;
  132. interrupt-parent = <&mpic>;
  133. interrupts = <28 0x2>;
  134. phy_type = "ulpi";
  135. };
  136. usb@23000 {
  137. compatible = "fsl,mpc8536-usb2-mph", "fsl-usb2-mph";
  138. reg = <0x23000 0x1000>;
  139. #address-cells = <1>;
  140. #size-cells = <0>;
  141. interrupt-parent = <&mpic>;
  142. interrupts = <46 0x2>;
  143. phy_type = "ulpi";
  144. };
  145. enet0: ethernet@24000 {
  146. #address-cells = <1>;
  147. #size-cells = <1>;
  148. cell-index = <0>;
  149. device_type = "network";
  150. model = "eTSEC";
  151. compatible = "gianfar";
  152. reg = <0x24000 0x1000>;
  153. ranges = <0x0 0x24000 0x1000>;
  154. local-mac-address = [ 00 00 00 00 00 00 ];
  155. interrupts = <29 2 30 2 34 2>;
  156. interrupt-parent = <&mpic>;
  157. tbi-handle = <&tbi0>;
  158. phy-handle = <&phy1>;
  159. phy-connection-type = "rgmii-id";
  160. mdio@520 {
  161. #address-cells = <1>;
  162. #size-cells = <0>;
  163. compatible = "fsl,gianfar-mdio";
  164. reg = <0x520 0x20>;
  165. phy0: ethernet-phy@0 {
  166. interrupt-parent = <&mpic>;
  167. interrupts = <10 0x1>;
  168. reg = <0>;
  169. device_type = "ethernet-phy";
  170. };
  171. phy1: ethernet-phy@1 {
  172. interrupt-parent = <&mpic>;
  173. interrupts = <10 0x1>;
  174. reg = <1>;
  175. device_type = "ethernet-phy";
  176. };
  177. tbi0: tbi-phy@11 {
  178. reg = <0x11>;
  179. device_type = "tbi-phy";
  180. };
  181. };
  182. };
  183. enet1: ethernet@26000 {
  184. #address-cells = <1>;
  185. #size-cells = <1>;
  186. cell-index = <1>;
  187. device_type = "network";
  188. model = "eTSEC";
  189. compatible = "gianfar";
  190. reg = <0x26000 0x1000>;
  191. ranges = <0x0 0x26000 0x1000>;
  192. local-mac-address = [ 00 00 00 00 00 00 ];
  193. interrupts = <31 2 32 2 33 2>;
  194. interrupt-parent = <&mpic>;
  195. tbi-handle = <&tbi1>;
  196. phy-handle = <&phy0>;
  197. phy-connection-type = "rgmii-id";
  198. mdio@520 {
  199. #address-cells = <1>;
  200. #size-cells = <0>;
  201. compatible = "fsl,gianfar-tbi";
  202. reg = <0x520 0x20>;
  203. tbi1: tbi-phy@11 {
  204. reg = <0x11>;
  205. device_type = "tbi-phy";
  206. };
  207. };
  208. };
  209. usb@2b000 {
  210. compatible = "fsl,mpc8536-usb2-dr", "fsl-usb2-dr";
  211. reg = <0x2b000 0x1000>;
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. interrupt-parent = <&mpic>;
  215. interrupts = <60 0x2>;
  216. dr_mode = "peripheral";
  217. phy_type = "ulpi";
  218. };
  219. serial0: serial@4500 {
  220. cell-index = <0>;
  221. device_type = "serial";
  222. compatible = "ns16550";
  223. reg = <0x4500 0x100>;
  224. clock-frequency = <0>;
  225. interrupts = <42 0x2>;
  226. interrupt-parent = <&mpic>;
  227. };
  228. serial1: serial@4600 {
  229. cell-index = <1>;
  230. device_type = "serial";
  231. compatible = "ns16550";
  232. reg = <0x4600 0x100>;
  233. clock-frequency = <0>;
  234. interrupts = <42 0x2>;
  235. interrupt-parent = <&mpic>;
  236. };
  237. crypto@30000 {
  238. compatible = "fsl,sec3.0", "fsl,sec2.4", "fsl,sec2.2",
  239. "fsl,sec2.1", "fsl,sec2.0";
  240. reg = <0x30000 0x10000>;
  241. interrupts = <45 2 58 2>;
  242. interrupt-parent = <&mpic>;
  243. fsl,num-channels = <4>;
  244. fsl,channel-fifo-len = <24>;
  245. fsl,exec-units-mask = <0x9fe>;
  246. fsl,descriptor-types-mask = <0x3ab0ebf>;
  247. };
  248. sata@18000 {
  249. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  250. reg = <0x18000 0x1000>;
  251. cell-index = <1>;
  252. interrupts = <74 0x2>;
  253. interrupt-parent = <&mpic>;
  254. };
  255. sata@19000 {
  256. compatible = "fsl,mpc8536-sata", "fsl,pq-sata";
  257. reg = <0x19000 0x1000>;
  258. cell-index = <2>;
  259. interrupts = <41 0x2>;
  260. interrupt-parent = <&mpic>;
  261. };
  262. global-utilities@e0000 { //global utilities block
  263. compatible = "fsl,mpc8548-guts";
  264. reg = <0xe0000 0x1000>;
  265. fsl,has-rstcr;
  266. };
  267. mpic: pic@40000 {
  268. clock-frequency = <0>;
  269. interrupt-controller;
  270. #address-cells = <0>;
  271. #interrupt-cells = <2>;
  272. reg = <0x40000 0x40000>;
  273. compatible = "chrp,open-pic";
  274. device_type = "open-pic";
  275. big-endian;
  276. };
  277. msi@41600 {
  278. compatible = "fsl,mpc8536-msi", "fsl,mpic-msi";
  279. reg = <0x41600 0x80>;
  280. msi-available-ranges = <0 0x100>;
  281. interrupts = <
  282. 0xe0 0
  283. 0xe1 0
  284. 0xe2 0
  285. 0xe3 0
  286. 0xe4 0
  287. 0xe5 0
  288. 0xe6 0
  289. 0xe7 0>;
  290. interrupt-parent = <&mpic>;
  291. };
  292. };
  293. pci0: pci@ffe08000 {
  294. cell-index = <0>;
  295. compatible = "fsl,mpc8540-pci";
  296. device_type = "pci";
  297. interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
  298. interrupt-map = <
  299. /* IDSEL 0x11 J17 Slot 1 */
  300. 0x8800 0 0 1 &mpic 1 1
  301. 0x8800 0 0 2 &mpic 2 1
  302. 0x8800 0 0 3 &mpic 3 1
  303. 0x8800 0 0 4 &mpic 4 1>;
  304. interrupt-parent = <&mpic>;
  305. interrupts = <24 0x2>;
  306. bus-range = <0 0xff>;
  307. ranges = <0x02000000 0 0x80000000 0x80000000 0 0x10000000
  308. 0x01000000 0 0x00000000 0xffc00000 0 0x00010000>;
  309. clock-frequency = <66666666>;
  310. #interrupt-cells = <1>;
  311. #size-cells = <2>;
  312. #address-cells = <3>;
  313. reg = <0xffe08000 0x1000>;
  314. };
  315. pci1: pcie@ffe09000 {
  316. cell-index = <1>;
  317. compatible = "fsl,mpc8548-pcie";
  318. device_type = "pci";
  319. #interrupt-cells = <1>;
  320. #size-cells = <2>;
  321. #address-cells = <3>;
  322. reg = <0xffe09000 0x1000>;
  323. bus-range = <0 0xff>;
  324. ranges = <0x02000000 0 0x98000000 0x98000000 0 0x08000000
  325. 0x01000000 0 0x00000000 0xffc20000 0 0x00010000>;
  326. clock-frequency = <33333333>;
  327. interrupt-parent = <&mpic>;
  328. interrupts = <25 0x2>;
  329. interrupt-map-mask = <0xf800 0 0 7>;
  330. interrupt-map = <
  331. /* IDSEL 0x0 */
  332. 0000 0 0 1 &mpic 4 1
  333. 0000 0 0 2 &mpic 5 1
  334. 0000 0 0 3 &mpic 6 1
  335. 0000 0 0 4 &mpic 7 1
  336. >;
  337. pcie@0 {
  338. reg = <0 0 0 0 0>;
  339. #size-cells = <2>;
  340. #address-cells = <3>;
  341. device_type = "pci";
  342. ranges = <0x02000000 0 0x98000000
  343. 0x02000000 0 0x98000000
  344. 0 0x08000000
  345. 0x01000000 0 0x00000000
  346. 0x01000000 0 0x00000000
  347. 0 0x00010000>;
  348. };
  349. };
  350. pci2: pcie@ffe0a000 {
  351. cell-index = <2>;
  352. compatible = "fsl,mpc8548-pcie";
  353. device_type = "pci";
  354. #interrupt-cells = <1>;
  355. #size-cells = <2>;
  356. #address-cells = <3>;
  357. reg = <0xffe0a000 0x1000>;
  358. bus-range = <0 0xff>;
  359. ranges = <0x02000000 0 0x90000000 0x90000000 0 0x08000000
  360. 0x01000000 0 0x00000000 0xffc10000 0 0x00010000>;
  361. clock-frequency = <33333333>;
  362. interrupt-parent = <&mpic>;
  363. interrupts = <26 0x2>;
  364. interrupt-map-mask = <0xf800 0 0 7>;
  365. interrupt-map = <
  366. /* IDSEL 0x0 */
  367. 0000 0 0 1 &mpic 0 1
  368. 0000 0 0 2 &mpic 1 1
  369. 0000 0 0 3 &mpic 2 1
  370. 0000 0 0 4 &mpic 3 1
  371. >;
  372. pcie@0 {
  373. reg = <0 0 0 0 0>;
  374. #size-cells = <2>;
  375. #address-cells = <3>;
  376. device_type = "pci";
  377. ranges = <0x02000000 0 0x90000000
  378. 0x02000000 0 0x90000000
  379. 0 0x08000000
  380. 0x01000000 0 0x00000000
  381. 0x01000000 0 0x00000000
  382. 0 0x00010000>;
  383. };
  384. };
  385. pci3: pcie@ffe0b000 {
  386. cell-index = <3>;
  387. compatible = "fsl,mpc8548-pcie";
  388. device_type = "pci";
  389. #interrupt-cells = <1>;
  390. #size-cells = <2>;
  391. #address-cells = <3>;
  392. reg = <0xffe0b000 0x1000>;
  393. bus-range = <0 0xff>;
  394. ranges = <0x02000000 0 0xa0000000 0xa0000000 0 0x20000000
  395. 0x01000000 0 0x00000000 0xffc30000 0 0x00010000>;
  396. clock-frequency = <33333333>;
  397. interrupt-parent = <&mpic>;
  398. interrupts = <27 0x2>;
  399. interrupt-map-mask = <0xf800 0 0 7>;
  400. interrupt-map = <
  401. /* IDSEL 0x0 */
  402. 0000 0 0 1 &mpic 8 1
  403. 0000 0 0 2 &mpic 9 1
  404. 0000 0 0 3 &mpic 10 1
  405. 0000 0 0 4 &mpic 11 1
  406. >;
  407. pcie@0 {
  408. reg = <0 0 0 0 0>;
  409. #size-cells = <2>;
  410. #address-cells = <3>;
  411. device_type = "pci";
  412. ranges = <0x02000000 0 0xa0000000
  413. 0x02000000 0 0xa0000000
  414. 0 0x20000000
  415. 0x01000000 0 0x00000000
  416. 0x01000000 0 0x00000000
  417. 0 0x00100000>;
  418. };
  419. };
  420. };