cevt-ds1287.c 2.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129
  1. /*
  2. * DS1287 clockevent driver
  3. *
  4. * Copyright (C) 2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; either version 2 of the License, or
  9. * (at your option) any later version.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
  19. */
  20. #include <linux/clockchips.h>
  21. #include <linux/init.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/mc146818rtc.h>
  24. #include <asm/time.h>
  25. int ds1287_timer_state(void)
  26. {
  27. return (CMOS_READ(RTC_REG_C) & RTC_PF) != 0;
  28. }
  29. int ds1287_set_base_clock(unsigned int hz)
  30. {
  31. u8 rate;
  32. switch (hz) {
  33. case 128:
  34. rate = 0x9;
  35. break;
  36. case 256:
  37. rate = 0x8;
  38. break;
  39. case 1024:
  40. rate = 0x6;
  41. break;
  42. default:
  43. return -EINVAL;
  44. }
  45. CMOS_WRITE(RTC_REF_CLCK_32KHZ | rate, RTC_REG_A);
  46. return 0;
  47. }
  48. static int ds1287_set_next_event(unsigned long delta,
  49. struct clock_event_device *evt)
  50. {
  51. return -EINVAL;
  52. }
  53. static void ds1287_set_mode(enum clock_event_mode mode,
  54. struct clock_event_device *evt)
  55. {
  56. u8 val;
  57. spin_lock(&rtc_lock);
  58. val = CMOS_READ(RTC_REG_B);
  59. switch (mode) {
  60. case CLOCK_EVT_MODE_PERIODIC:
  61. val |= RTC_PIE;
  62. break;
  63. default:
  64. val &= ~RTC_PIE;
  65. break;
  66. }
  67. CMOS_WRITE(val, RTC_REG_B);
  68. spin_unlock(&rtc_lock);
  69. }
  70. static void ds1287_event_handler(struct clock_event_device *dev)
  71. {
  72. }
  73. static struct clock_event_device ds1287_clockevent = {
  74. .name = "ds1287",
  75. .features = CLOCK_EVT_FEAT_PERIODIC,
  76. .set_next_event = ds1287_set_next_event,
  77. .set_mode = ds1287_set_mode,
  78. .event_handler = ds1287_event_handler,
  79. };
  80. static irqreturn_t ds1287_interrupt(int irq, void *dev_id)
  81. {
  82. struct clock_event_device *cd = &ds1287_clockevent;
  83. /* Ack the RTC interrupt. */
  84. CMOS_READ(RTC_REG_C);
  85. cd->event_handler(cd);
  86. return IRQ_HANDLED;
  87. }
  88. static struct irqaction ds1287_irqaction = {
  89. .handler = ds1287_interrupt,
  90. .flags = IRQF_DISABLED | IRQF_PERCPU,
  91. .name = "ds1287",
  92. };
  93. int __init ds1287_clockevent_init(int irq)
  94. {
  95. struct clock_event_device *cd;
  96. cd = &ds1287_clockevent;
  97. cd->rating = 100;
  98. cd->irq = irq;
  99. clockevent_set_clock(cd, 32768);
  100. cd->max_delta_ns = clockevent_delta2ns(0x7fffffff, cd);
  101. cd->min_delta_ns = clockevent_delta2ns(0x300, cd);
  102. cd->cpumask = cpumask_of(0);
  103. clockevents_register_device(&ds1287_clockevent);
  104. return setup_irq(irq, &ds1287_irqaction);
  105. }