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arch
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mips
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include
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asm
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emma
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markeins.h

markeins.h 3.3 KB
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  1. /*
    2. 

  2.  *  include/asm-mips/emma2rh/markeins.h
    3. 

  3.  *      This file is EMMA2RH board depended header.
    4. 

  4.  *
    5. 

  5.  *  Copyright (C) NEC Electronics Corporation 2005-2006
    6. 

  6.  *
    7. 

  7.  *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
    8. 

  8.  *          Copyright 2001 MontaVista Software Inc.
    9. 

  9.  *
    10. 

  10.  *  This program is free software; you can redistribute it and/or modify
    11. 

  11.  *  it under the terms of the GNU General Public License as published by
    12. 

  12.  *  the Free Software Foundation; either version 2 of the License, or
    13. 

  13.  *  (at your option) any later version.
    14. 

  14.  *
    15. 

  15.  *  This program is distributed in the hope that it will be useful,
    16. 

  16.  *  but WITHOUT ANY WARRANTY; without even the implied warranty of
    17. 

  17.  *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    18. 

  18.  *  GNU General Public License for more details.
    19. 

  19.  *
    20. 

  20.  *  You should have received a copy of the GNU General Public License
    21. 

  21.  *  along with this program; if not, write to the Free Software
    22. 

  22.  *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
    23. 

  23.  */
    24. 

  24. 

  25. #ifndef MARKEINS_H
    26. 

  26. #define MARKEINS_H
    27. 

  27. 

  28. #define NUM_EMMA2RH_IRQ_SW	32
    29. 

  29. #define NUM_EMMA2RH_IRQ_GPIO	32
    30. 

  30. 

  31. #define EMMA2RH_SW_CASCADE	(EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
    32. 

  32. #define EMMA2RH_GPIO_CASCADE	(EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
    33. 

  33. 

  34. #define EMMA2RH_SW_IRQ_BASE	(EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
    35. 

  35. #define EMMA2RH_GPIO_IRQ_BASE	(EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
    36. 

  36. 

  37. #define EMMA2RH_SW_IRQ_INT0	(0+EMMA2RH_SW_IRQ_BASE)
    38. 

  38. #define EMMA2RH_SW_IRQ_INT1	(1+EMMA2RH_SW_IRQ_BASE)
    39. 

  39. #define EMMA2RH_SW_IRQ_INT2	(2+EMMA2RH_SW_IRQ_BASE)
    40. 

  40. #define EMMA2RH_SW_IRQ_INT3	(3+EMMA2RH_SW_IRQ_BASE)
    41. 

  41. #define EMMA2RH_SW_IRQ_INT4	(4+EMMA2RH_SW_IRQ_BASE)
    42. 

  42. #define EMMA2RH_SW_IRQ_INT5	(5+EMMA2RH_SW_IRQ_BASE)
    43. 

  43. #define EMMA2RH_SW_IRQ_INT6	(6+EMMA2RH_SW_IRQ_BASE)
    44. 

  44. #define EMMA2RH_SW_IRQ_INT7	(7+EMMA2RH_SW_IRQ_BASE)
    45. 

  45. #define EMMA2RH_SW_IRQ_INT8	(8+EMMA2RH_SW_IRQ_BASE)
    46. 

  46. #define EMMA2RH_SW_IRQ_INT9	(9+EMMA2RH_SW_IRQ_BASE)
    47. 

  47. #define EMMA2RH_SW_IRQ_INT10	(10+EMMA2RH_SW_IRQ_BASE)
    48. 

  48. #define EMMA2RH_SW_IRQ_INT11	(11+EMMA2RH_SW_IRQ_BASE)
    49. 

  49. #define EMMA2RH_SW_IRQ_INT12	(12+EMMA2RH_SW_IRQ_BASE)
    50. 

  50. #define EMMA2RH_SW_IRQ_INT13	(13+EMMA2RH_SW_IRQ_BASE)
    51. 

  51. #define EMMA2RH_SW_IRQ_INT14	(14+EMMA2RH_SW_IRQ_BASE)
    52. 

  52. #define EMMA2RH_SW_IRQ_INT15	(15+EMMA2RH_SW_IRQ_BASE)
    53. 

  53. #define EMMA2RH_SW_IRQ_INT16	(16+EMMA2RH_SW_IRQ_BASE)
    54. 

  54. #define EMMA2RH_SW_IRQ_INT17	(17+EMMA2RH_SW_IRQ_BASE)
    55. 

  55. #define EMMA2RH_SW_IRQ_INT18	(18+EMMA2RH_SW_IRQ_BASE)
    56. 

  56. #define EMMA2RH_SW_IRQ_INT19	(19+EMMA2RH_SW_IRQ_BASE)
    57. 

  57. #define EMMA2RH_SW_IRQ_INT20	(20+EMMA2RH_SW_IRQ_BASE)
    58. 

  58. #define EMMA2RH_SW_IRQ_INT21	(21+EMMA2RH_SW_IRQ_BASE)
    59. 

  59. #define EMMA2RH_SW_IRQ_INT22	(22+EMMA2RH_SW_IRQ_BASE)
    60. 

  60. #define EMMA2RH_SW_IRQ_INT23	(23+EMMA2RH_SW_IRQ_BASE)
    61. 

  61. #define EMMA2RH_SW_IRQ_INT24	(24+EMMA2RH_SW_IRQ_BASE)
    62. 

  62. #define EMMA2RH_SW_IRQ_INT25	(25+EMMA2RH_SW_IRQ_BASE)
    63. 

  63. #define EMMA2RH_SW_IRQ_INT26	(26+EMMA2RH_SW_IRQ_BASE)
    64. 

  64. #define EMMA2RH_SW_IRQ_INT27	(27+EMMA2RH_SW_IRQ_BASE)
    65. 

  65. #define EMMA2RH_SW_IRQ_INT28	(28+EMMA2RH_SW_IRQ_BASE)
    66. 

  66. #define EMMA2RH_SW_IRQ_INT29	(29+EMMA2RH_SW_IRQ_BASE)
    67. 

  67. #define EMMA2RH_SW_IRQ_INT30	(30+EMMA2RH_SW_IRQ_BASE)
    68. 

  68. #define EMMA2RH_SW_IRQ_INT31	(31+EMMA2RH_SW_IRQ_BASE)
    69. 

  69. 

  70. #define MARKEINS_PCI_IRQ_INTA	EMMA2RH_GPIO_IRQ_BASE+15
    71. 

  71. #define MARKEINS_PCI_IRQ_INTB	EMMA2RH_GPIO_IRQ_BASE+16
    72. 

  72. #define MARKEINS_PCI_IRQ_INTC	EMMA2RH_GPIO_IRQ_BASE+17
    73. 

  73. #define MARKEINS_PCI_IRQ_INTD	EMMA2RH_GPIO_IRQ_BASE+18
    74. 

  74. 

  75. #endif /* CONFIG_MARKEINS */
    76.