irq.c 13 KB

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  1. /*
  2. * Platform dependent support for SGI SN
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (c) 2000-2008 Silicon Graphics, Inc. All Rights Reserved.
  9. */
  10. #include <linux/irq.h>
  11. #include <linux/spinlock.h>
  12. #include <linux/init.h>
  13. #include <linux/rculist.h>
  14. #include <asm/sn/addrs.h>
  15. #include <asm/sn/arch.h>
  16. #include <asm/sn/intr.h>
  17. #include <asm/sn/pcibr_provider.h>
  18. #include <asm/sn/pcibus_provider_defs.h>
  19. #include <asm/sn/pcidev.h>
  20. #include <asm/sn/shub_mmr.h>
  21. #include <asm/sn/sn_sal.h>
  22. #include <asm/sn/sn_feature_sets.h>
  23. static void force_interrupt(int irq);
  24. static void register_intr_pda(struct sn_irq_info *sn_irq_info);
  25. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info);
  26. int sn_force_interrupt_flag = 1;
  27. extern int sn_ioif_inited;
  28. struct list_head **sn_irq_lh;
  29. static DEFINE_SPINLOCK(sn_irq_info_lock); /* non-IRQ lock */
  30. u64 sn_intr_alloc(nasid_t local_nasid, int local_widget,
  31. struct sn_irq_info *sn_irq_info,
  32. int req_irq, nasid_t req_nasid,
  33. int req_slice)
  34. {
  35. struct ia64_sal_retval ret_stuff;
  36. ret_stuff.status = 0;
  37. ret_stuff.v0 = 0;
  38. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  39. (u64) SAL_INTR_ALLOC, (u64) local_nasid,
  40. (u64) local_widget, __pa(sn_irq_info), (u64) req_irq,
  41. (u64) req_nasid, (u64) req_slice);
  42. return ret_stuff.status;
  43. }
  44. void sn_intr_free(nasid_t local_nasid, int local_widget,
  45. struct sn_irq_info *sn_irq_info)
  46. {
  47. struct ia64_sal_retval ret_stuff;
  48. ret_stuff.status = 0;
  49. ret_stuff.v0 = 0;
  50. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  51. (u64) SAL_INTR_FREE, (u64) local_nasid,
  52. (u64) local_widget, (u64) sn_irq_info->irq_irq,
  53. (u64) sn_irq_info->irq_cookie, 0, 0);
  54. }
  55. u64 sn_intr_redirect(nasid_t local_nasid, int local_widget,
  56. struct sn_irq_info *sn_irq_info,
  57. nasid_t req_nasid, int req_slice)
  58. {
  59. struct ia64_sal_retval ret_stuff;
  60. ret_stuff.status = 0;
  61. ret_stuff.v0 = 0;
  62. SAL_CALL_NOLOCK(ret_stuff, (u64) SN_SAL_IOIF_INTERRUPT,
  63. (u64) SAL_INTR_REDIRECT, (u64) local_nasid,
  64. (u64) local_widget, __pa(sn_irq_info),
  65. (u64) req_nasid, (u64) req_slice, 0);
  66. return ret_stuff.status;
  67. }
  68. static unsigned int sn_startup_irq(unsigned int irq)
  69. {
  70. return 0;
  71. }
  72. static void sn_shutdown_irq(unsigned int irq)
  73. {
  74. }
  75. extern void ia64_mca_register_cpev(int);
  76. static void sn_disable_irq(unsigned int irq)
  77. {
  78. if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
  79. ia64_mca_register_cpev(0);
  80. }
  81. static void sn_enable_irq(unsigned int irq)
  82. {
  83. if (irq == local_vector_to_irq(IA64_CPE_VECTOR))
  84. ia64_mca_register_cpev(irq);
  85. }
  86. static void sn_ack_irq(unsigned int irq)
  87. {
  88. u64 event_occurred, mask;
  89. irq = irq & 0xff;
  90. event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED));
  91. mask = event_occurred & SH_ALL_INT_MASK;
  92. HUB_S((u64*)LOCAL_MMR_ADDR(SH_EVENT_OCCURRED_ALIAS), mask);
  93. __set_bit(irq, (volatile void *)pda->sn_in_service_ivecs);
  94. move_native_irq(irq);
  95. }
  96. static void sn_end_irq(unsigned int irq)
  97. {
  98. int ivec;
  99. u64 event_occurred;
  100. ivec = irq & 0xff;
  101. if (ivec == SGI_UART_VECTOR) {
  102. event_occurred = HUB_L((u64*)LOCAL_MMR_ADDR (SH_EVENT_OCCURRED));
  103. /* If the UART bit is set here, we may have received an
  104. * interrupt from the UART that the driver missed. To
  105. * make sure, we IPI ourselves to force us to look again.
  106. */
  107. if (event_occurred & SH_EVENT_OCCURRED_UART_INT_MASK) {
  108. platform_send_ipi(smp_processor_id(), SGI_UART_VECTOR,
  109. IA64_IPI_DM_INT, 0);
  110. }
  111. }
  112. __clear_bit(ivec, (volatile void *)pda->sn_in_service_ivecs);
  113. if (sn_force_interrupt_flag)
  114. force_interrupt(irq);
  115. }
  116. static void sn_irq_info_free(struct rcu_head *head);
  117. struct sn_irq_info *sn_retarget_vector(struct sn_irq_info *sn_irq_info,
  118. nasid_t nasid, int slice)
  119. {
  120. int vector;
  121. int cpuid;
  122. #ifdef CONFIG_SMP
  123. int cpuphys;
  124. #endif
  125. int64_t bridge;
  126. int local_widget, status;
  127. nasid_t local_nasid;
  128. struct sn_irq_info *new_irq_info;
  129. struct sn_pcibus_provider *pci_provider;
  130. bridge = (u64) sn_irq_info->irq_bridge;
  131. if (!bridge) {
  132. return NULL; /* irq is not a device interrupt */
  133. }
  134. local_nasid = NASID_GET(bridge);
  135. if (local_nasid & 1)
  136. local_widget = TIO_SWIN_WIDGETNUM(bridge);
  137. else
  138. local_widget = SWIN_WIDGETNUM(bridge);
  139. vector = sn_irq_info->irq_irq;
  140. /* Make use of SAL_INTR_REDIRECT if PROM supports it */
  141. status = sn_intr_redirect(local_nasid, local_widget, sn_irq_info, nasid, slice);
  142. if (!status) {
  143. new_irq_info = sn_irq_info;
  144. goto finish_up;
  145. }
  146. /*
  147. * PROM does not support SAL_INTR_REDIRECT, or it failed.
  148. * Revert to old method.
  149. */
  150. new_irq_info = kmalloc(sizeof(struct sn_irq_info), GFP_ATOMIC);
  151. if (new_irq_info == NULL)
  152. return NULL;
  153. memcpy(new_irq_info, sn_irq_info, sizeof(struct sn_irq_info));
  154. /* Free the old PROM new_irq_info structure */
  155. sn_intr_free(local_nasid, local_widget, new_irq_info);
  156. unregister_intr_pda(new_irq_info);
  157. /* allocate a new PROM new_irq_info struct */
  158. status = sn_intr_alloc(local_nasid, local_widget,
  159. new_irq_info, vector,
  160. nasid, slice);
  161. /* SAL call failed */
  162. if (status) {
  163. kfree(new_irq_info);
  164. return NULL;
  165. }
  166. register_intr_pda(new_irq_info);
  167. spin_lock(&sn_irq_info_lock);
  168. list_replace_rcu(&sn_irq_info->list, &new_irq_info->list);
  169. spin_unlock(&sn_irq_info_lock);
  170. call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
  171. finish_up:
  172. /* Update kernels new_irq_info with new target info */
  173. cpuid = nasid_slice_to_cpuid(new_irq_info->irq_nasid,
  174. new_irq_info->irq_slice);
  175. new_irq_info->irq_cpuid = cpuid;
  176. pci_provider = sn_pci_provider[new_irq_info->irq_bridge_type];
  177. /*
  178. * If this represents a line interrupt, target it. If it's
  179. * an msi (irq_int_bit < 0), it's already targeted.
  180. */
  181. if (new_irq_info->irq_int_bit >= 0 &&
  182. pci_provider && pci_provider->target_interrupt)
  183. (pci_provider->target_interrupt)(new_irq_info);
  184. #ifdef CONFIG_SMP
  185. cpuphys = cpu_physical_id(cpuid);
  186. set_irq_affinity_info((vector & 0xff), cpuphys, 0);
  187. #endif
  188. return new_irq_info;
  189. }
  190. static void sn_set_affinity_irq(unsigned int irq, const struct cpumask *mask)
  191. {
  192. struct sn_irq_info *sn_irq_info, *sn_irq_info_safe;
  193. nasid_t nasid;
  194. int slice;
  195. nasid = cpuid_to_nasid(cpumask_first(mask));
  196. slice = cpuid_to_slice(cpumask_first(mask));
  197. list_for_each_entry_safe(sn_irq_info, sn_irq_info_safe,
  198. sn_irq_lh[irq], list)
  199. (void)sn_retarget_vector(sn_irq_info, nasid, slice);
  200. }
  201. #ifdef CONFIG_SMP
  202. void sn_set_err_irq_affinity(unsigned int irq)
  203. {
  204. /*
  205. * On systems which support CPU disabling (SHub2), all error interrupts
  206. * are targetted at the boot CPU.
  207. */
  208. if (is_shub2() && sn_prom_feature_available(PRF_CPU_DISABLE_SUPPORT))
  209. set_irq_affinity_info(irq, cpu_physical_id(0), 0);
  210. }
  211. #else
  212. void sn_set_err_irq_affinity(unsigned int irq) { }
  213. #endif
  214. static void
  215. sn_mask_irq(unsigned int irq)
  216. {
  217. }
  218. static void
  219. sn_unmask_irq(unsigned int irq)
  220. {
  221. }
  222. struct irq_chip irq_type_sn = {
  223. .name = "SN hub",
  224. .startup = sn_startup_irq,
  225. .shutdown = sn_shutdown_irq,
  226. .enable = sn_enable_irq,
  227. .disable = sn_disable_irq,
  228. .ack = sn_ack_irq,
  229. .end = sn_end_irq,
  230. .mask = sn_mask_irq,
  231. .unmask = sn_unmask_irq,
  232. .set_affinity = sn_set_affinity_irq
  233. };
  234. ia64_vector sn_irq_to_vector(int irq)
  235. {
  236. if (irq >= IA64_NUM_VECTORS)
  237. return 0;
  238. return (ia64_vector)irq;
  239. }
  240. unsigned int sn_local_vector_to_irq(u8 vector)
  241. {
  242. return (CPU_VECTOR_TO_IRQ(smp_processor_id(), vector));
  243. }
  244. void sn_irq_init(void)
  245. {
  246. int i;
  247. irq_desc_t *base_desc = irq_desc;
  248. ia64_first_device_vector = IA64_SN2_FIRST_DEVICE_VECTOR;
  249. ia64_last_device_vector = IA64_SN2_LAST_DEVICE_VECTOR;
  250. for (i = 0; i < NR_IRQS; i++) {
  251. if (base_desc[i].chip == &no_irq_type) {
  252. base_desc[i].chip = &irq_type_sn;
  253. }
  254. }
  255. }
  256. static void register_intr_pda(struct sn_irq_info *sn_irq_info)
  257. {
  258. int irq = sn_irq_info->irq_irq;
  259. int cpu = sn_irq_info->irq_cpuid;
  260. if (pdacpu(cpu)->sn_last_irq < irq) {
  261. pdacpu(cpu)->sn_last_irq = irq;
  262. }
  263. if (pdacpu(cpu)->sn_first_irq == 0 || pdacpu(cpu)->sn_first_irq > irq)
  264. pdacpu(cpu)->sn_first_irq = irq;
  265. }
  266. static void unregister_intr_pda(struct sn_irq_info *sn_irq_info)
  267. {
  268. int irq = sn_irq_info->irq_irq;
  269. int cpu = sn_irq_info->irq_cpuid;
  270. struct sn_irq_info *tmp_irq_info;
  271. int i, foundmatch;
  272. rcu_read_lock();
  273. if (pdacpu(cpu)->sn_last_irq == irq) {
  274. foundmatch = 0;
  275. for (i = pdacpu(cpu)->sn_last_irq - 1;
  276. i && !foundmatch; i--) {
  277. list_for_each_entry_rcu(tmp_irq_info,
  278. sn_irq_lh[i],
  279. list) {
  280. if (tmp_irq_info->irq_cpuid == cpu) {
  281. foundmatch = 1;
  282. break;
  283. }
  284. }
  285. }
  286. pdacpu(cpu)->sn_last_irq = i;
  287. }
  288. if (pdacpu(cpu)->sn_first_irq == irq) {
  289. foundmatch = 0;
  290. for (i = pdacpu(cpu)->sn_first_irq + 1;
  291. i < NR_IRQS && !foundmatch; i++) {
  292. list_for_each_entry_rcu(tmp_irq_info,
  293. sn_irq_lh[i],
  294. list) {
  295. if (tmp_irq_info->irq_cpuid == cpu) {
  296. foundmatch = 1;
  297. break;
  298. }
  299. }
  300. }
  301. pdacpu(cpu)->sn_first_irq = ((i == NR_IRQS) ? 0 : i);
  302. }
  303. rcu_read_unlock();
  304. }
  305. static void sn_irq_info_free(struct rcu_head *head)
  306. {
  307. struct sn_irq_info *sn_irq_info;
  308. sn_irq_info = container_of(head, struct sn_irq_info, rcu);
  309. kfree(sn_irq_info);
  310. }
  311. void sn_irq_fixup(struct pci_dev *pci_dev, struct sn_irq_info *sn_irq_info)
  312. {
  313. nasid_t nasid = sn_irq_info->irq_nasid;
  314. int slice = sn_irq_info->irq_slice;
  315. int cpu = nasid_slice_to_cpuid(nasid, slice);
  316. #ifdef CONFIG_SMP
  317. int cpuphys;
  318. irq_desc_t *desc;
  319. #endif
  320. pci_dev_get(pci_dev);
  321. sn_irq_info->irq_cpuid = cpu;
  322. sn_irq_info->irq_pciioinfo = SN_PCIDEV_INFO(pci_dev);
  323. /* link it into the sn_irq[irq] list */
  324. spin_lock(&sn_irq_info_lock);
  325. list_add_rcu(&sn_irq_info->list, sn_irq_lh[sn_irq_info->irq_irq]);
  326. reserve_irq_vector(sn_irq_info->irq_irq);
  327. spin_unlock(&sn_irq_info_lock);
  328. register_intr_pda(sn_irq_info);
  329. #ifdef CONFIG_SMP
  330. cpuphys = cpu_physical_id(cpu);
  331. set_irq_affinity_info(sn_irq_info->irq_irq, cpuphys, 0);
  332. desc = irq_to_desc(sn_irq_info->irq_irq);
  333. /*
  334. * Affinity was set by the PROM, prevent it from
  335. * being reset by the request_irq() path.
  336. */
  337. desc->status |= IRQ_AFFINITY_SET;
  338. #endif
  339. }
  340. void sn_irq_unfixup(struct pci_dev *pci_dev)
  341. {
  342. struct sn_irq_info *sn_irq_info;
  343. /* Only cleanup IRQ stuff if this device has a host bus context */
  344. if (!SN_PCIDEV_BUSSOFT(pci_dev))
  345. return;
  346. sn_irq_info = SN_PCIDEV_INFO(pci_dev)->pdi_sn_irq_info;
  347. if (!sn_irq_info)
  348. return;
  349. if (!sn_irq_info->irq_irq) {
  350. kfree(sn_irq_info);
  351. return;
  352. }
  353. unregister_intr_pda(sn_irq_info);
  354. spin_lock(&sn_irq_info_lock);
  355. list_del_rcu(&sn_irq_info->list);
  356. spin_unlock(&sn_irq_info_lock);
  357. if (list_empty(sn_irq_lh[sn_irq_info->irq_irq]))
  358. free_irq_vector(sn_irq_info->irq_irq);
  359. call_rcu(&sn_irq_info->rcu, sn_irq_info_free);
  360. pci_dev_put(pci_dev);
  361. }
  362. static inline void
  363. sn_call_force_intr_provider(struct sn_irq_info *sn_irq_info)
  364. {
  365. struct sn_pcibus_provider *pci_provider;
  366. pci_provider = sn_pci_provider[sn_irq_info->irq_bridge_type];
  367. /* Don't force an interrupt if the irq has been disabled */
  368. if (!(irq_desc[sn_irq_info->irq_irq].status & IRQ_DISABLED) &&
  369. pci_provider && pci_provider->force_interrupt)
  370. (*pci_provider->force_interrupt)(sn_irq_info);
  371. }
  372. static void force_interrupt(int irq)
  373. {
  374. struct sn_irq_info *sn_irq_info;
  375. if (!sn_ioif_inited)
  376. return;
  377. rcu_read_lock();
  378. list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[irq], list)
  379. sn_call_force_intr_provider(sn_irq_info);
  380. rcu_read_unlock();
  381. }
  382. /*
  383. * Check for lost interrupts. If the PIC int_status reg. says that
  384. * an interrupt has been sent, but not handled, and the interrupt
  385. * is not pending in either the cpu irr regs or in the soft irr regs,
  386. * and the interrupt is not in service, then the interrupt may have
  387. * been lost. Force an interrupt on that pin. It is possible that
  388. * the interrupt is in flight, so we may generate a spurious interrupt,
  389. * but we should never miss a real lost interrupt.
  390. */
  391. static void sn_check_intr(int irq, struct sn_irq_info *sn_irq_info)
  392. {
  393. u64 regval;
  394. struct pcidev_info *pcidev_info;
  395. struct pcibus_info *pcibus_info;
  396. /*
  397. * Bridge types attached to TIO (anything but PIC) do not need this WAR
  398. * since they do not target Shub II interrupt registers. If that
  399. * ever changes, this check needs to accomodate.
  400. */
  401. if (sn_irq_info->irq_bridge_type != PCIIO_ASIC_TYPE_PIC)
  402. return;
  403. pcidev_info = (struct pcidev_info *)sn_irq_info->irq_pciioinfo;
  404. if (!pcidev_info)
  405. return;
  406. pcibus_info =
  407. (struct pcibus_info *)pcidev_info->pdi_host_pcidev_info->
  408. pdi_pcibus_info;
  409. regval = pcireg_intr_status_get(pcibus_info);
  410. if (!ia64_get_irr(irq_to_vector(irq))) {
  411. if (!test_bit(irq, pda->sn_in_service_ivecs)) {
  412. regval &= 0xff;
  413. if (sn_irq_info->irq_int_bit & regval &
  414. sn_irq_info->irq_last_intr) {
  415. regval &= ~(sn_irq_info->irq_int_bit & regval);
  416. sn_call_force_intr_provider(sn_irq_info);
  417. }
  418. }
  419. }
  420. sn_irq_info->irq_last_intr = regval;
  421. }
  422. void sn_lb_int_war_check(void)
  423. {
  424. struct sn_irq_info *sn_irq_info;
  425. int i;
  426. if (!sn_ioif_inited || pda->sn_first_irq == 0)
  427. return;
  428. rcu_read_lock();
  429. for (i = pda->sn_first_irq; i <= pda->sn_last_irq; i++) {
  430. list_for_each_entry_rcu(sn_irq_info, sn_irq_lh[i], list) {
  431. sn_check_intr(i, sn_irq_info);
  432. }
  433. }
  434. rcu_read_unlock();
  435. }
  436. void __init sn_irq_lh_init(void)
  437. {
  438. int i;
  439. sn_irq_lh = kmalloc(sizeof(struct list_head *) * NR_IRQS, GFP_KERNEL);
  440. if (!sn_irq_lh)
  441. panic("SN PCI INIT: Failed to allocate memory for PCI init\n");
  442. for (i = 0; i < NR_IRQS; i++) {
  443. sn_irq_lh[i] = kmalloc(sizeof(struct list_head), GFP_KERNEL);
  444. if (!sn_irq_lh[i])
  445. panic("SN PCI INIT: Failed IRQ memory allocation\n");
  446. INIT_LIST_HEAD(sn_irq_lh[i]);
  447. }
  448. }