irqpanic.c 4.0 KB

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  1. /*
  2. * File: arch/blackfin/mach-common/irqpanic.c
  3. * Based on:
  4. * Author:
  5. *
  6. * Created: ?
  7. * Description: panic kernel with dump information
  8. *
  9. * Modified: rgetz - added cache checking code 14Feb06
  10. * Copyright 2004-2006 Analog Devices Inc.
  11. *
  12. * Bugs: Enter bugs at http://blackfin.uclinux.org/
  13. *
  14. * This program is free software; you can redistribute it and/or modify
  15. * it under the terms of the GNU General Public License as published by
  16. * the Free Software Foundation; either version 2 of the License, or
  17. * (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  22. * GNU General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU General Public License
  25. * along with this program; if not, see the file COPYING, or write
  26. * to the Free Software Foundation, Inc.,
  27. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  28. */
  29. #include <linux/module.h>
  30. #include <linux/kernel_stat.h>
  31. #include <linux/sched.h>
  32. #include <asm/traps.h>
  33. #include <asm/blackfin.h>
  34. #ifdef CONFIG_DEBUG_ICACHE_CHECK
  35. #define L1_ICACHE_START 0xffa10000
  36. #define L1_ICACHE_END 0xffa13fff
  37. void irq_panic(int reason, struct pt_regs *regs) __attribute__ ((l1_text));
  38. #endif
  39. /*
  40. * irq_panic - calls panic with string setup
  41. */
  42. asmlinkage void irq_panic(int reason, struct pt_regs *regs)
  43. {
  44. #ifdef CONFIG_DEBUG_ICACHE_CHECK
  45. unsigned int cmd, tag, ca, cache_hi, cache_lo, *pa;
  46. unsigned short i, j, die;
  47. unsigned int bad[10][6];
  48. /* check entire cache for coherency
  49. * Since printk is in cacheable memory,
  50. * don't call it until you have checked everything
  51. */
  52. die = 0;
  53. i = 0;
  54. /* check icache */
  55. for (ca = L1_ICACHE_START; ca <= L1_ICACHE_END && i < 10; ca += 32) {
  56. /* Grab various address bits for the itest_cmd fields */
  57. cmd = (((ca & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
  58. ((ca & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
  59. ((ca & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
  60. 0); /* Access Tag, Read access */
  61. SSYNC();
  62. bfin_write_ITEST_COMMAND(cmd);
  63. SSYNC();
  64. tag = bfin_read_ITEST_DATA0();
  65. SSYNC();
  66. /* if tag is marked as valid, check it */
  67. if (tag & 1) {
  68. /* The icache is arranged in 4 groups of 64-bits */
  69. for (j = 0; j < 32; j += 8) {
  70. cmd = ((((ca + j) & 0x3000) << 4) | /* ca[13:12] for SBNK[1:0] */
  71. (((ca + j) & 0x0c00) << 16) | /* ca[11:10] for WAYSEL[1:0] */
  72. (((ca + j) & 0x3f8)) | /* ca[09:03] for SET[4:0] and DW[1:0] */
  73. 4); /* Access Data, Read access */
  74. SSYNC();
  75. bfin_write_ITEST_COMMAND(cmd);
  76. SSYNC();
  77. cache_hi = bfin_read_ITEST_DATA1();
  78. cache_lo = bfin_read_ITEST_DATA0();
  79. pa = ((unsigned int *)((tag & 0xffffcc00) |
  80. ((ca + j) & ~(0xffffcc00))));
  81. /*
  82. * Debugging this, enable
  83. *
  84. * printk("addr: %08x %08x%08x | %08x%08x\n",
  85. * ((unsigned int *)((tag & 0xffffcc00) | ((ca+j) & ~(0xffffcc00)))),
  86. * cache_hi, cache_lo, *(pa+1), *pa);
  87. */
  88. if (cache_hi != *(pa + 1) || cache_lo != *pa) {
  89. /* Since icache is not working, stay out of it, by not printing */
  90. die = 1;
  91. bad[i][0] = (ca + j);
  92. bad[i][1] = cache_hi;
  93. bad[i][2] = cache_lo;
  94. bad[i][3] = ((tag & 0xffffcc00) |
  95. ((ca + j) & ~(0xffffcc00)));
  96. bad[i][4] = *(pa + 1);
  97. bad[i][5] = *(pa);
  98. i++;
  99. }
  100. }
  101. }
  102. }
  103. if (die) {
  104. printk(KERN_EMERG "icache coherency error\n");
  105. for (j = 0; j <= i; j++) {
  106. printk(KERN_EMERG
  107. "cache address : %08x cache value : %08x%08x\n",
  108. bad[j][0], bad[j][1], bad[j][2]);
  109. printk(KERN_EMERG
  110. "physical address: %08x SDRAM value : %08x%08x\n",
  111. bad[j][3], bad[j][4], bad[j][5]);
  112. }
  113. panic("icache coherency error");
  114. } else {
  115. printk(KERN_EMERG "icache checked, and OK\n");
  116. }
  117. #endif
  118. }