ip0x.c 8.0 KB

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  1. /*
  2. * File: arch/blackfin/mach-bf533/ip0x.c
  3. * Based on: arch/blackfin/mach-bf533/bf1.c
  4. * Based on: arch/blackfin/mach-bf533/stamp.c
  5. * Author: Ivan Danov <idanov@gmail.com>
  6. * Modified for IP0X David Rowe
  7. *
  8. * Created: 2007
  9. * Description: Board info file for the IP04/IP08 boards, which
  10. * are derived from the BlackfinOne V2.0 boards.
  11. *
  12. * Modified:
  13. * COpyright 2007 David Rowe
  14. * Copyright 2006 Intratrade Ltd.
  15. * Copyright 2005 National ICT Australia (NICTA)
  16. * Copyright 2004-2006 Analog Devices Inc.
  17. *
  18. * This program is free software; you can redistribute it and/or modify
  19. * it under the terms of the GNU General Public License as published by
  20. * the Free Software Foundation; either version 2 of the License, or
  21. * (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, see the file COPYING, or write
  30. * to the Free Software Foundation, Inc.,
  31. * 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  32. */
  33. #include <linux/device.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/mtd/mtd.h>
  36. #include <linux/mtd/partitions.h>
  37. #include <linux/spi/spi.h>
  38. #include <linux/spi/flash.h>
  39. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  40. #include <linux/usb/isp1362.h>
  41. #endif
  42. #include <asm/irq.h>
  43. #include <asm/bfin5xx_spi.h>
  44. /*
  45. * Name the Board for the /proc/cpuinfo
  46. */
  47. const char bfin_board_name[] = "IP04/IP08";
  48. /*
  49. * Driver needs to know address, irq and flag pin.
  50. */
  51. #if defined(CONFIG_BFIN532_IP0X)
  52. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  53. #include <linux/dm9000.h>
  54. static struct resource dm9000_resource1[] = {
  55. {
  56. .start = 0x20100000,
  57. .end = 0x20100000 + 1,
  58. .flags = IORESOURCE_MEM
  59. },{
  60. .start = 0x20100000 + 2,
  61. .end = 0x20100000 + 3,
  62. .flags = IORESOURCE_MEM
  63. },{
  64. .start = IRQ_PF15,
  65. .end = IRQ_PF15,
  66. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  67. }
  68. };
  69. static struct resource dm9000_resource2[] = {
  70. {
  71. .start = 0x20200000,
  72. .end = 0x20200000 + 1,
  73. .flags = IORESOURCE_MEM
  74. },{
  75. .start = 0x20200000 + 2,
  76. .end = 0x20200000 + 3,
  77. .flags = IORESOURCE_MEM
  78. },{
  79. .start = IRQ_PF14,
  80. .end = IRQ_PF14,
  81. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHEDGE
  82. }
  83. };
  84. /*
  85. * for the moment we limit ourselves to 16bit IO until some
  86. * better IO routines can be written and tested
  87. */
  88. static struct dm9000_plat_data dm9000_platdata1 = {
  89. .flags = DM9000_PLATF_16BITONLY,
  90. };
  91. static struct platform_device dm9000_device1 = {
  92. .name = "dm9000",
  93. .id = 0,
  94. .num_resources = ARRAY_SIZE(dm9000_resource1),
  95. .resource = dm9000_resource1,
  96. .dev = {
  97. .platform_data = &dm9000_platdata1,
  98. }
  99. };
  100. static struct dm9000_plat_data dm9000_platdata2 = {
  101. .flags = DM9000_PLATF_16BITONLY,
  102. };
  103. static struct platform_device dm9000_device2 = {
  104. .name = "dm9000",
  105. .id = 1,
  106. .num_resources = ARRAY_SIZE(dm9000_resource2),
  107. .resource = dm9000_resource2,
  108. .dev = {
  109. .platform_data = &dm9000_platdata2,
  110. }
  111. };
  112. #endif
  113. #endif
  114. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  115. /* all SPI peripherals info goes here */
  116. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  117. static struct bfin5xx_spi_chip mmc_spi_chip_info = {
  118. /*
  119. * CPOL (Clock Polarity)
  120. * 0 - Active high SCK
  121. * 1 - Active low SCK
  122. * CPHA (Clock Phase) Selects transfer format and operation mode
  123. * 0 - SCLK toggles from middle of the first data bit, slave select
  124. * pins controlled by hardware.
  125. * 1 - SCLK toggles from beginning of first data bit, slave select
  126. * pins controller by user software.
  127. * .ctl_reg = 0x1c00, * CPOL=1,CPHA=1,Sandisk 1G work
  128. * NO NO .ctl_reg = 0x1800, * CPOL=1,CPHA=0
  129. * NO NO .ctl_reg = 0x1400, * CPOL=0,CPHA=1
  130. */
  131. .ctl_reg = 0x1000, /* CPOL=0,CPHA=0,Sandisk 1G work */
  132. .enable_dma = 0, /* if 1 - block!!! */
  133. .bits_per_word = 8,
  134. .cs_change_per_word = 0,
  135. };
  136. #endif
  137. /* Notice: for blackfin, the speed_hz is the value of register
  138. * SPI_BAUD, not the real baudrate */
  139. static struct spi_board_info bfin_spi_board_info[] __initdata = {
  140. #if defined(CONFIG_MMC_SPI) || defined(CONFIG_MMC_SPI_MODULE)
  141. {
  142. .modalias = "mmc_spi",
  143. .max_speed_hz = 2,
  144. .bus_num = 1,
  145. .chip_select = 5,
  146. .controller_data = &mmc_spi_chip_info,
  147. },
  148. #endif
  149. };
  150. /* SPI controller data */
  151. static struct bfin5xx_spi_master spi_bfin_master_info = {
  152. .num_chipselect = 8,
  153. .enable_dma = 1, /* master has the ability to do dma transfer */
  154. };
  155. static struct platform_device spi_bfin_master_device = {
  156. .name = "bfin-spi-master",
  157. .id = 1, /* Bus number */
  158. .dev = {
  159. .platform_data = &spi_bfin_master_info, /* Passed to driver */
  160. },
  161. };
  162. #endif /* spi master and devices */
  163. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  164. static struct resource bfin_uart_resources[] = {
  165. {
  166. .start = 0xFFC00400,
  167. .end = 0xFFC004FF,
  168. .flags = IORESOURCE_MEM,
  169. },
  170. };
  171. static struct platform_device bfin_uart_device = {
  172. .name = "bfin-uart",
  173. .id = 1,
  174. .num_resources = ARRAY_SIZE(bfin_uart_resources),
  175. .resource = bfin_uart_resources,
  176. };
  177. #endif
  178. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  179. #ifdef CONFIG_BFIN_SIR0
  180. static struct resource bfin_sir0_resources[] = {
  181. {
  182. .start = 0xFFC00400,
  183. .end = 0xFFC004FF,
  184. .flags = IORESOURCE_MEM,
  185. },
  186. {
  187. .start = IRQ_UART0_RX,
  188. .end = IRQ_UART0_RX+1,
  189. .flags = IORESOURCE_IRQ,
  190. },
  191. {
  192. .start = CH_UART0_RX,
  193. .end = CH_UART0_RX+1,
  194. .flags = IORESOURCE_DMA,
  195. },
  196. };
  197. static struct platform_device bfin_sir0_device = {
  198. .name = "bfin_sir",
  199. .id = 0,
  200. .num_resources = ARRAY_SIZE(bfin_sir0_resources),
  201. .resource = bfin_sir0_resources,
  202. };
  203. #endif
  204. #endif
  205. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  206. static struct resource isp1362_hcd_resources[] = {
  207. {
  208. .start = 0x20300000,
  209. .end = 0x20300000 + 1,
  210. .flags = IORESOURCE_MEM,
  211. },{
  212. .start = 0x20300000 + 2,
  213. .end = 0x20300000 + 3,
  214. .flags = IORESOURCE_MEM,
  215. },{
  216. .start = IRQ_PF11,
  217. .end = IRQ_PF11,
  218. .flags = IORESOURCE_IRQ | IORESOURCE_IRQ_HIGHLEVEL,
  219. },
  220. };
  221. static struct isp1362_platform_data isp1362_priv = {
  222. .sel15Kres = 1,
  223. .clknotstop = 0,
  224. .oc_enable = 0, /* external OC */
  225. .int_act_high = 0,
  226. .int_edge_triggered = 0,
  227. .remote_wakeup_connected = 0,
  228. .no_power_switching = 1,
  229. .power_switching_mode = 0,
  230. };
  231. static struct platform_device isp1362_hcd_device = {
  232. .name = "isp1362-hcd",
  233. .id = 0,
  234. .dev = {
  235. .platform_data = &isp1362_priv,
  236. },
  237. .num_resources = ARRAY_SIZE(isp1362_hcd_resources),
  238. .resource = isp1362_hcd_resources,
  239. };
  240. #endif
  241. static struct platform_device *ip0x_devices[] __initdata = {
  242. #if defined(CONFIG_BFIN532_IP0X)
  243. #if defined(CONFIG_DM9000) || defined(CONFIG_DM9000_MODULE)
  244. &dm9000_device1,
  245. &dm9000_device2,
  246. #endif
  247. #endif
  248. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  249. &spi_bfin_master_device,
  250. #endif
  251. #if defined(CONFIG_SERIAL_BFIN) || defined(CONFIG_SERIAL_BFIN_MODULE)
  252. &bfin_uart_device,
  253. #endif
  254. #if defined(CONFIG_BFIN_SIR) || defined(CONFIG_BFIN_SIR_MODULE)
  255. #ifdef CONFIG_BFIN_SIR0
  256. &bfin_sir0_device,
  257. #endif
  258. #endif
  259. #if defined(CONFIG_USB_ISP1362_HCD) || defined(CONFIG_USB_ISP1362_HCD_MODULE)
  260. &isp1362_hcd_device,
  261. #endif
  262. };
  263. static int __init ip0x_init(void)
  264. {
  265. int i;
  266. printk(KERN_INFO "%s(): registering device resources\n", __func__);
  267. platform_add_devices(ip0x_devices, ARRAY_SIZE(ip0x_devices));
  268. #if defined(CONFIG_SPI_BFIN) || defined(CONFIG_SPI_BFIN_MODULE)
  269. for (i = 0; i < ARRAY_SIZE(bfin_spi_board_info); ++i) {
  270. int j = 1 << bfin_spi_board_info[i].chip_select;
  271. /* set spi cs to 1 */
  272. bfin_write_FIO_DIR(bfin_read_FIO_DIR() | j);
  273. bfin_write_FIO_FLAG_S(j);
  274. }
  275. spi_register_board_info(bfin_spi_board_info, ARRAY_SIZE(bfin_spi_board_info));
  276. #endif
  277. return 0;
  278. }
  279. arch_initcall(ip0x_init);