dma.c 4.8 KB

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  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/sysdev.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-ac97.h>
  25. #include <mach/regs-mem.h>
  26. #include <mach/regs-lcd.h>
  27. #include <mach/regs-sdi.h>
  28. #include <plat/regs-iis.h>
  29. #include <plat/regs-spi.h>
  30. #define MAP(x) { \
  31. [0] = (x) | DMA_CH_VALID, \
  32. [1] = (x) | DMA_CH_VALID, \
  33. [2] = (x) | DMA_CH_VALID, \
  34. [3] = (x) | DMA_CH_VALID, \
  35. [4] = (x) | DMA_CH_VALID, \
  36. [5] = (x) | DMA_CH_VALID, \
  37. }
  38. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  39. [DMACH_XD0] = {
  40. .name = "xdreq0",
  41. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  42. },
  43. [DMACH_XD1] = {
  44. .name = "xdreq1",
  45. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  46. },
  47. [DMACH_SDI] = {
  48. .name = "sdi",
  49. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  50. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  51. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  52. },
  53. [DMACH_SPI0] = {
  54. .name = "spi0",
  55. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  56. .hw_addr.to = S3C2410_PA_SPI + S3C2410_SPTDAT,
  57. .hw_addr.from = S3C2410_PA_SPI + S3C2410_SPRDAT,
  58. },
  59. [DMACH_SPI1] = {
  60. .name = "spi1",
  61. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  62. .hw_addr.to = S3C2410_PA_SPI + 0x20 + S3C2410_SPTDAT,
  63. .hw_addr.from = S3C2410_PA_SPI + 0x20 + S3C2410_SPRDAT,
  64. },
  65. [DMACH_UART0] = {
  66. .name = "uart0",
  67. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  68. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  69. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  70. },
  71. [DMACH_UART1] = {
  72. .name = "uart1",
  73. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  74. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  75. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  76. },
  77. [DMACH_UART2] = {
  78. .name = "uart2",
  79. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  80. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  81. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  82. },
  83. [DMACH_UART3] = {
  84. .name = "uart3",
  85. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  86. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  87. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  88. },
  89. [DMACH_UART0_SRC2] = {
  90. .name = "uart0",
  91. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  92. .hw_addr.to = S3C2410_PA_UART0 + S3C2410_UTXH,
  93. .hw_addr.from = S3C2410_PA_UART0 + S3C2410_URXH,
  94. },
  95. [DMACH_UART1_SRC2] = {
  96. .name = "uart1",
  97. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  98. .hw_addr.to = S3C2410_PA_UART1 + S3C2410_UTXH,
  99. .hw_addr.from = S3C2410_PA_UART1 + S3C2410_URXH,
  100. },
  101. [DMACH_UART2_SRC2] = {
  102. .name = "uart2",
  103. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  104. .hw_addr.to = S3C2410_PA_UART2 + S3C2410_UTXH,
  105. .hw_addr.from = S3C2410_PA_UART2 + S3C2410_URXH,
  106. },
  107. [DMACH_UART3_SRC2] = {
  108. .name = "uart3",
  109. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  110. .hw_addr.to = S3C2443_PA_UART3 + S3C2410_UTXH,
  111. .hw_addr.from = S3C2443_PA_UART3 + S3C2410_URXH,
  112. },
  113. [DMACH_TIMER] = {
  114. .name = "timer",
  115. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  116. },
  117. [DMACH_I2S_IN] = {
  118. .name = "i2s-sdi",
  119. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  120. .hw_addr.from = S3C2410_PA_IIS + S3C2410_IISFIFO,
  121. },
  122. [DMACH_I2S_OUT] = {
  123. .name = "i2s-sdo",
  124. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  125. .hw_addr.to = S3C2410_PA_IIS + S3C2410_IISFIFO,
  126. },
  127. [DMACH_PCM_IN] = {
  128. .name = "pcm-in",
  129. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  130. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  131. },
  132. [DMACH_PCM_OUT] = {
  133. .name = "pcm-out",
  134. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  135. .hw_addr.to = S3C2440_PA_AC97 + S3C_AC97_PCM_DATA,
  136. },
  137. [DMACH_MIC_IN] = {
  138. .name = "mic-in",
  139. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  140. .hw_addr.from = S3C2440_PA_AC97 + S3C_AC97_MIC_DATA,
  141. },
  142. };
  143. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  144. struct s3c24xx_dma_map *map)
  145. {
  146. writel(map->channels[0] | S3C2443_DMAREQSEL_HW,
  147. chan->regs + S3C2443_DMA_DMAREQSEL);
  148. }
  149. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  150. .select = s3c2443_dma_select,
  151. .dcon_mask = 0,
  152. .map = s3c2443_dma_mappings,
  153. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  154. };
  155. static int __init s3c2443_dma_add(struct sys_device *sysdev)
  156. {
  157. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  158. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  159. }
  160. static struct sysdev_driver s3c2443_dma_driver = {
  161. .add = s3c2443_dma_add,
  162. };
  163. static int __init s3c2443_dma_init(void)
  164. {
  165. return sysdev_driver_register(&s3c2443_sysclass, &s3c2443_dma_driver);
  166. }
  167. arch_initcall(s3c2443_dma_init);