sys_mikasa.c 6.2 KB

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  1. /*
  2. * linux/arch/alpha/kernel/sys_mikasa.c
  3. *
  4. * Copyright (C) 1995 David A Rusling
  5. * Copyright (C) 1996 Jay A Estabrook
  6. * Copyright (C) 1998, 1999 Richard Henderson
  7. *
  8. * Code supporting the MIKASA (AlphaServer 1000).
  9. */
  10. #include <linux/kernel.h>
  11. #include <linux/types.h>
  12. #include <linux/mm.h>
  13. #include <linux/sched.h>
  14. #include <linux/pci.h>
  15. #include <linux/init.h>
  16. #include <linux/bitops.h>
  17. #include <asm/ptrace.h>
  18. #include <asm/system.h>
  19. #include <asm/dma.h>
  20. #include <asm/irq.h>
  21. #include <asm/mmu_context.h>
  22. #include <asm/io.h>
  23. #include <asm/pgtable.h>
  24. #include <asm/core_apecs.h>
  25. #include <asm/core_cia.h>
  26. #include <asm/tlbflush.h>
  27. #include "proto.h"
  28. #include "irq_impl.h"
  29. #include "pci_impl.h"
  30. #include "machvec_impl.h"
  31. /* Note mask bit is true for ENABLED irqs. */
  32. static int cached_irq_mask;
  33. static inline void
  34. mikasa_update_irq_hw(int mask)
  35. {
  36. outw(mask, 0x536);
  37. }
  38. static inline void
  39. mikasa_enable_irq(unsigned int irq)
  40. {
  41. mikasa_update_irq_hw(cached_irq_mask |= 1 << (irq - 16));
  42. }
  43. static void
  44. mikasa_disable_irq(unsigned int irq)
  45. {
  46. mikasa_update_irq_hw(cached_irq_mask &= ~(1 << (irq - 16)));
  47. }
  48. static unsigned int
  49. mikasa_startup_irq(unsigned int irq)
  50. {
  51. mikasa_enable_irq(irq);
  52. return 0;
  53. }
  54. static void
  55. mikasa_end_irq(unsigned int irq)
  56. {
  57. if (!(irq_desc[irq].status & (IRQ_DISABLED|IRQ_INPROGRESS)))
  58. mikasa_enable_irq(irq);
  59. }
  60. static struct hw_interrupt_type mikasa_irq_type = {
  61. .typename = "MIKASA",
  62. .startup = mikasa_startup_irq,
  63. .shutdown = mikasa_disable_irq,
  64. .enable = mikasa_enable_irq,
  65. .disable = mikasa_disable_irq,
  66. .ack = mikasa_disable_irq,
  67. .end = mikasa_end_irq,
  68. };
  69. static void
  70. mikasa_device_interrupt(unsigned long vector)
  71. {
  72. unsigned long pld;
  73. unsigned int i;
  74. /* Read the interrupt summary registers */
  75. pld = (((~inw(0x534) & 0x0000ffffUL) << 16)
  76. | (((unsigned long) inb(0xa0)) << 8)
  77. | inb(0x20));
  78. /*
  79. * Now for every possible bit set, work through them and call
  80. * the appropriate interrupt handler.
  81. */
  82. while (pld) {
  83. i = ffz(~pld);
  84. pld &= pld - 1; /* clear least bit set */
  85. if (i < 16) {
  86. isa_device_interrupt(vector);
  87. } else {
  88. handle_irq(i);
  89. }
  90. }
  91. }
  92. static void __init
  93. mikasa_init_irq(void)
  94. {
  95. long i;
  96. if (alpha_using_srm)
  97. alpha_mv.device_interrupt = srm_device_interrupt;
  98. mikasa_update_irq_hw(0);
  99. for (i = 16; i < 32; ++i) {
  100. irq_desc[i].status = IRQ_DISABLED | IRQ_LEVEL;
  101. irq_desc[i].chip = &mikasa_irq_type;
  102. }
  103. init_i8259a_irqs();
  104. common_init_isa_dma();
  105. }
  106. /*
  107. * PCI Fixup configuration.
  108. *
  109. * Summary @ 0x536:
  110. * Bit Meaning
  111. * 0 Interrupt Line A from slot 0
  112. * 1 Interrupt Line B from slot 0
  113. * 2 Interrupt Line C from slot 0
  114. * 3 Interrupt Line D from slot 0
  115. * 4 Interrupt Line A from slot 1
  116. * 5 Interrupt line B from slot 1
  117. * 6 Interrupt Line C from slot 1
  118. * 7 Interrupt Line D from slot 1
  119. * 8 Interrupt Line A from slot 2
  120. * 9 Interrupt Line B from slot 2
  121. *10 Interrupt Line C from slot 2
  122. *11 Interrupt Line D from slot 2
  123. *12 NCR 810 SCSI
  124. *13 Power Supply Fail
  125. *14 Temperature Warn
  126. *15 Reserved
  127. *
  128. * The device to slot mapping looks like:
  129. *
  130. * Slot Device
  131. * 6 NCR SCSI controller
  132. * 7 Intel PCI-EISA bridge chip
  133. * 11 PCI on board slot 0
  134. * 12 PCI on board slot 1
  135. * 13 PCI on board slot 2
  136. *
  137. *
  138. * This two layered interrupt approach means that we allocate IRQ 16 and
  139. * above for PCI interrupts. The IRQ relates to which bit the interrupt
  140. * comes in on. This makes interrupt processing much easier.
  141. */
  142. static int __init
  143. mikasa_map_irq(struct pci_dev *dev, u8 slot, u8 pin)
  144. {
  145. static char irq_tab[8][5] __initdata = {
  146. /*INT INTA INTB INTC INTD */
  147. {16+12, 16+12, 16+12, 16+12, 16+12}, /* IdSel 17, SCSI */
  148. { -1, -1, -1, -1, -1}, /* IdSel 18, PCEB */
  149. { -1, -1, -1, -1, -1}, /* IdSel 19, ???? */
  150. { -1, -1, -1, -1, -1}, /* IdSel 20, ???? */
  151. { -1, -1, -1, -1, -1}, /* IdSel 21, ???? */
  152. { 16+0, 16+0, 16+1, 16+2, 16+3}, /* IdSel 22, slot 0 */
  153. { 16+4, 16+4, 16+5, 16+6, 16+7}, /* IdSel 23, slot 1 */
  154. { 16+8, 16+8, 16+9, 16+10, 16+11}, /* IdSel 24, slot 2 */
  155. };
  156. const long min_idsel = 6, max_idsel = 13, irqs_per_slot = 5;
  157. return COMMON_TABLE_LOOKUP;
  158. }
  159. #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
  160. static void
  161. mikasa_apecs_machine_check(unsigned long vector, unsigned long la_ptr)
  162. {
  163. #define MCHK_NO_DEVSEL 0x205U
  164. #define MCHK_NO_TABT 0x204U
  165. struct el_common *mchk_header;
  166. unsigned int code;
  167. mchk_header = (struct el_common *)la_ptr;
  168. /* Clear the error before any reporting. */
  169. mb();
  170. mb(); /* magic */
  171. draina();
  172. apecs_pci_clr_err();
  173. wrmces(0x7);
  174. mb();
  175. code = mchk_header->code;
  176. process_mcheck_info(vector, la_ptr, "MIKASA APECS",
  177. (mcheck_expected(0)
  178. && (code == MCHK_NO_DEVSEL
  179. || code == MCHK_NO_TABT)));
  180. }
  181. #endif
  182. /*
  183. * The System Vector
  184. */
  185. #if defined(CONFIG_ALPHA_GENERIC) || !defined(CONFIG_ALPHA_PRIMO)
  186. struct alpha_machine_vector mikasa_mv __initmv = {
  187. .vector_name = "Mikasa",
  188. DO_EV4_MMU,
  189. DO_DEFAULT_RTC,
  190. DO_APECS_IO,
  191. .machine_check = mikasa_apecs_machine_check,
  192. .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
  193. .min_io_address = DEFAULT_IO_BASE,
  194. .min_mem_address = APECS_AND_LCA_DEFAULT_MEM_BASE,
  195. .nr_irqs = 32,
  196. .device_interrupt = mikasa_device_interrupt,
  197. .init_arch = apecs_init_arch,
  198. .init_irq = mikasa_init_irq,
  199. .init_rtc = common_init_rtc,
  200. .init_pci = common_init_pci,
  201. .pci_map_irq = mikasa_map_irq,
  202. .pci_swizzle = common_swizzle,
  203. };
  204. ALIAS_MV(mikasa)
  205. #endif
  206. #if defined(CONFIG_ALPHA_GENERIC) || defined(CONFIG_ALPHA_PRIMO)
  207. struct alpha_machine_vector mikasa_primo_mv __initmv = {
  208. .vector_name = "Mikasa-Primo",
  209. DO_EV5_MMU,
  210. DO_DEFAULT_RTC,
  211. DO_CIA_IO,
  212. .machine_check = cia_machine_check,
  213. .max_isa_dma_address = ALPHA_MAX_ISA_DMA_ADDRESS,
  214. .min_io_address = DEFAULT_IO_BASE,
  215. .min_mem_address = CIA_DEFAULT_MEM_BASE,
  216. .nr_irqs = 32,
  217. .device_interrupt = mikasa_device_interrupt,
  218. .init_arch = cia_init_arch,
  219. .init_irq = mikasa_init_irq,
  220. .init_rtc = common_init_rtc,
  221. .init_pci = cia_init_pci,
  222. .kill_arch = cia_kill_arch,
  223. .pci_map_irq = mikasa_map_irq,
  224. .pci_swizzle = common_swizzle,
  225. };
  226. ALIAS_MV(mikasa_primo)
  227. #endif