core_t2.c 16 KB

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  1. /*
  2. * linux/arch/alpha/kernel/core_t2.c
  3. *
  4. * Written by Jay A Estabrook (jestabro@amt.tay1.dec.com).
  5. * December 1996.
  6. *
  7. * based on CIA code by David A Rusling (david.rusling@reo.mts.dec.com)
  8. *
  9. * Code common to all T2 core logic chips.
  10. */
  11. #define __EXTERN_INLINE
  12. #include <asm/io.h>
  13. #include <asm/core_t2.h>
  14. #undef __EXTERN_INLINE
  15. #include <linux/types.h>
  16. #include <linux/pci.h>
  17. #include <linux/sched.h>
  18. #include <linux/init.h>
  19. #include <asm/ptrace.h>
  20. #include <asm/delay.h>
  21. #include "proto.h"
  22. #include "pci_impl.h"
  23. /* For dumping initial DMA window settings. */
  24. #define DEBUG_PRINT_INITIAL_SETTINGS 0
  25. /* For dumping final DMA window settings. */
  26. #define DEBUG_PRINT_FINAL_SETTINGS 0
  27. /*
  28. * By default, we direct-map starting at 2GB, in order to allow the
  29. * maximum size direct-map window (2GB) to match the maximum amount of
  30. * memory (2GB) that can be present on SABLEs. But that limits the
  31. * floppy to DMA only via the scatter/gather window set up for 8MB
  32. * ISA DMA, since the maximum ISA DMA address is 2GB-1.
  33. *
  34. * For now, this seems a reasonable trade-off: even though most SABLEs
  35. * have less than 1GB of memory, floppy usage/performance will not
  36. * really be affected by forcing it to go via scatter/gather...
  37. */
  38. #define T2_DIRECTMAP_2G 1
  39. #if T2_DIRECTMAP_2G
  40. # define T2_DIRECTMAP_START 0x80000000UL
  41. # define T2_DIRECTMAP_LENGTH 0x80000000UL
  42. #else
  43. # define T2_DIRECTMAP_START 0x40000000UL
  44. # define T2_DIRECTMAP_LENGTH 0x40000000UL
  45. #endif
  46. /* The ISA scatter/gather window settings. */
  47. #define T2_ISA_SG_START 0x00800000UL
  48. #define T2_ISA_SG_LENGTH 0x00800000UL
  49. /*
  50. * NOTE: Herein lie back-to-back mb instructions. They are magic.
  51. * One plausible explanation is that the i/o controller does not properly
  52. * handle the system transaction. Another involves timing. Ho hum.
  53. */
  54. /*
  55. * BIOS32-style PCI interface:
  56. */
  57. #define DEBUG_CONFIG 0
  58. #if DEBUG_CONFIG
  59. # define DBG(args) printk args
  60. #else
  61. # define DBG(args)
  62. #endif
  63. DEFINE_SPINLOCK(t2_hae_lock);
  64. static volatile unsigned int t2_mcheck_any_expected;
  65. static volatile unsigned int t2_mcheck_last_taken;
  66. /* Place to save the DMA Window registers as set up by SRM
  67. for restoration during shutdown. */
  68. static struct
  69. {
  70. struct {
  71. unsigned long wbase;
  72. unsigned long wmask;
  73. unsigned long tbase;
  74. } window[2];
  75. unsigned long hae_1;
  76. unsigned long hae_2;
  77. unsigned long hae_3;
  78. unsigned long hae_4;
  79. unsigned long hbase;
  80. } t2_saved_config __attribute((common));
  81. /*
  82. * Given a bus, device, and function number, compute resulting
  83. * configuration space address and setup the T2_HAXR2 register
  84. * accordingly. It is therefore not safe to have concurrent
  85. * invocations to configuration space access routines, but there
  86. * really shouldn't be any need for this.
  87. *
  88. * Type 0:
  89. *
  90. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  91. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  92. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  93. * | | |D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|0|
  94. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  95. *
  96. * 31:11 Device select bit.
  97. * 10:8 Function number
  98. * 7:2 Register number
  99. *
  100. * Type 1:
  101. *
  102. * 3 3|3 3 2 2|2 2 2 2|2 2 2 2|1 1 1 1|1 1 1 1|1 1
  103. * 3 2|1 0 9 8|7 6 5 4|3 2 1 0|9 8 7 6|5 4 3 2|1 0 9 8|7 6 5 4|3 2 1 0
  104. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  105. * | | | | | | | | | | |B|B|B|B|B|B|B|B|D|D|D|D|D|F|F|F|R|R|R|R|R|R|0|1|
  106. * +-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
  107. *
  108. * 31:24 reserved
  109. * 23:16 bus number (8 bits = 128 possible buses)
  110. * 15:11 Device number (5 bits)
  111. * 10:8 function number
  112. * 7:2 register number
  113. *
  114. * Notes:
  115. * The function number selects which function of a multi-function device
  116. * (e.g., SCSI and Ethernet).
  117. *
  118. * The register selects a DWORD (32 bit) register offset. Hence it
  119. * doesn't get shifted by 2 bits as we want to "drop" the bottom two
  120. * bits.
  121. */
  122. static int
  123. mk_conf_addr(struct pci_bus *pbus, unsigned int device_fn, int where,
  124. unsigned long *pci_addr, unsigned char *type1)
  125. {
  126. unsigned long addr;
  127. u8 bus = pbus->number;
  128. DBG(("mk_conf_addr(bus=%d, dfn=0x%x, where=0x%x,"
  129. " addr=0x%lx, type1=0x%x)\n",
  130. bus, device_fn, where, pci_addr, type1));
  131. if (bus == 0) {
  132. int device = device_fn >> 3;
  133. /* Type 0 configuration cycle. */
  134. if (device > 8) {
  135. DBG(("mk_conf_addr: device (%d)>20, returning -1\n",
  136. device));
  137. return -1;
  138. }
  139. *type1 = 0;
  140. addr = (0x0800L << device) | ((device_fn & 7) << 8) | (where);
  141. } else {
  142. /* Type 1 configuration cycle. */
  143. *type1 = 1;
  144. addr = (bus << 16) | (device_fn << 8) | (where);
  145. }
  146. *pci_addr = addr;
  147. DBG(("mk_conf_addr: returning pci_addr 0x%lx\n", addr));
  148. return 0;
  149. }
  150. /*
  151. * NOTE: both conf_read() and conf_write() may set HAE_3 when needing
  152. * to do type1 access. This is protected by the use of spinlock IRQ
  153. * primitives in the wrapper functions pci_{read,write}_config_*()
  154. * defined in drivers/pci/pci.c.
  155. */
  156. static unsigned int
  157. conf_read(unsigned long addr, unsigned char type1)
  158. {
  159. unsigned int value, cpu, taken;
  160. unsigned long t2_cfg = 0;
  161. cpu = smp_processor_id();
  162. DBG(("conf_read(addr=0x%lx, type1=%d)\n", addr, type1));
  163. /* If Type1 access, must set T2 CFG. */
  164. if (type1) {
  165. t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
  166. *(vulp)T2_HAE_3 = 0x40000000UL | t2_cfg;
  167. mb();
  168. }
  169. mb();
  170. draina();
  171. mcheck_expected(cpu) = 1;
  172. mcheck_taken(cpu) = 0;
  173. t2_mcheck_any_expected |= (1 << cpu);
  174. mb();
  175. /* Access configuration space. */
  176. value = *(vuip)addr;
  177. mb();
  178. mb(); /* magic */
  179. /* Wait for possible mcheck. Also, this lets other CPUs clear
  180. their mchecks as well, as they can reliably tell when
  181. another CPU is in the midst of handling a real mcheck via
  182. the "taken" function. */
  183. udelay(100);
  184. if ((taken = mcheck_taken(cpu))) {
  185. mcheck_taken(cpu) = 0;
  186. t2_mcheck_last_taken |= (1 << cpu);
  187. value = 0xffffffffU;
  188. mb();
  189. }
  190. mcheck_expected(cpu) = 0;
  191. t2_mcheck_any_expected = 0;
  192. mb();
  193. /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
  194. if (type1) {
  195. *(vulp)T2_HAE_3 = t2_cfg;
  196. mb();
  197. }
  198. return value;
  199. }
  200. static void
  201. conf_write(unsigned long addr, unsigned int value, unsigned char type1)
  202. {
  203. unsigned int cpu, taken;
  204. unsigned long t2_cfg = 0;
  205. cpu = smp_processor_id();
  206. /* If Type1 access, must set T2 CFG. */
  207. if (type1) {
  208. t2_cfg = *(vulp)T2_HAE_3 & ~0xc0000000UL;
  209. *(vulp)T2_HAE_3 = t2_cfg | 0x40000000UL;
  210. mb();
  211. }
  212. mb();
  213. draina();
  214. mcheck_expected(cpu) = 1;
  215. mcheck_taken(cpu) = 0;
  216. t2_mcheck_any_expected |= (1 << cpu);
  217. mb();
  218. /* Access configuration space. */
  219. *(vuip)addr = value;
  220. mb();
  221. mb(); /* magic */
  222. /* Wait for possible mcheck. Also, this lets other CPUs clear
  223. their mchecks as well, as they can reliably tell when
  224. this CPU is in the midst of handling a real mcheck via
  225. the "taken" function. */
  226. udelay(100);
  227. if ((taken = mcheck_taken(cpu))) {
  228. mcheck_taken(cpu) = 0;
  229. t2_mcheck_last_taken |= (1 << cpu);
  230. mb();
  231. }
  232. mcheck_expected(cpu) = 0;
  233. t2_mcheck_any_expected = 0;
  234. mb();
  235. /* If Type1 access, must reset T2 CFG so normal IO space ops work. */
  236. if (type1) {
  237. *(vulp)T2_HAE_3 = t2_cfg;
  238. mb();
  239. }
  240. }
  241. static int
  242. t2_read_config(struct pci_bus *bus, unsigned int devfn, int where,
  243. int size, u32 *value)
  244. {
  245. unsigned long addr, pci_addr;
  246. unsigned char type1;
  247. int shift;
  248. long mask;
  249. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  250. return PCIBIOS_DEVICE_NOT_FOUND;
  251. mask = (size - 1) * 8;
  252. shift = (where & 3) * 8;
  253. addr = (pci_addr << 5) + mask + T2_CONF;
  254. *value = conf_read(addr, type1) >> (shift);
  255. return PCIBIOS_SUCCESSFUL;
  256. }
  257. static int
  258. t2_write_config(struct pci_bus *bus, unsigned int devfn, int where, int size,
  259. u32 value)
  260. {
  261. unsigned long addr, pci_addr;
  262. unsigned char type1;
  263. long mask;
  264. if (mk_conf_addr(bus, devfn, where, &pci_addr, &type1))
  265. return PCIBIOS_DEVICE_NOT_FOUND;
  266. mask = (size - 1) * 8;
  267. addr = (pci_addr << 5) + mask + T2_CONF;
  268. conf_write(addr, value << ((where & 3) * 8), type1);
  269. return PCIBIOS_SUCCESSFUL;
  270. }
  271. struct pci_ops t2_pci_ops =
  272. {
  273. .read = t2_read_config,
  274. .write = t2_write_config,
  275. };
  276. static void __init
  277. t2_direct_map_window1(unsigned long base, unsigned long length)
  278. {
  279. unsigned long temp;
  280. __direct_map_base = base;
  281. __direct_map_size = length;
  282. temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
  283. *(vulp)T2_WBASE1 = temp | 0x80000UL; /* OR in ENABLE bit */
  284. temp = (length - 1) & 0xfff00000UL;
  285. *(vulp)T2_WMASK1 = temp;
  286. *(vulp)T2_TBASE1 = 0;
  287. #if DEBUG_PRINT_FINAL_SETTINGS
  288. printk("%s: setting WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n",
  289. __func__, *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
  290. #endif
  291. }
  292. static void __init
  293. t2_sg_map_window2(struct pci_controller *hose,
  294. unsigned long base,
  295. unsigned long length)
  296. {
  297. unsigned long temp;
  298. /* Note we can only do 1 SG window, as the other is for direct, so
  299. do an ISA SG area, especially for the floppy. */
  300. hose->sg_isa = iommu_arena_new(hose, base, length, 0);
  301. hose->sg_pci = NULL;
  302. temp = (base & 0xfff00000UL) | ((base + length - 1) >> 20);
  303. *(vulp)T2_WBASE2 = temp | 0xc0000UL; /* OR in ENABLE/SG bits */
  304. temp = (length - 1) & 0xfff00000UL;
  305. *(vulp)T2_WMASK2 = temp;
  306. *(vulp)T2_TBASE2 = virt_to_phys(hose->sg_isa->ptes) >> 1;
  307. mb();
  308. t2_pci_tbi(hose, 0, -1); /* flush TLB all */
  309. #if DEBUG_PRINT_FINAL_SETTINGS
  310. printk("%s: setting WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n",
  311. __func__, *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
  312. #endif
  313. }
  314. static void __init
  315. t2_save_configuration(void)
  316. {
  317. #if DEBUG_PRINT_INITIAL_SETTINGS
  318. printk("%s: HAE_1 was 0x%lx\n", __func__, srm_hae); /* HW is 0 */
  319. printk("%s: HAE_2 was 0x%lx\n", __func__, *(vulp)T2_HAE_2);
  320. printk("%s: HAE_3 was 0x%lx\n", __func__, *(vulp)T2_HAE_3);
  321. printk("%s: HAE_4 was 0x%lx\n", __func__, *(vulp)T2_HAE_4);
  322. printk("%s: HBASE was 0x%lx\n", __func__, *(vulp)T2_HBASE);
  323. printk("%s: WBASE1=0x%lx WMASK1=0x%lx TBASE1=0x%lx\n", __func__,
  324. *(vulp)T2_WBASE1, *(vulp)T2_WMASK1, *(vulp)T2_TBASE1);
  325. printk("%s: WBASE2=0x%lx WMASK2=0x%lx TBASE2=0x%lx\n", __func__,
  326. *(vulp)T2_WBASE2, *(vulp)T2_WMASK2, *(vulp)T2_TBASE2);
  327. #endif
  328. /*
  329. * Save the DMA Window registers.
  330. */
  331. t2_saved_config.window[0].wbase = *(vulp)T2_WBASE1;
  332. t2_saved_config.window[0].wmask = *(vulp)T2_WMASK1;
  333. t2_saved_config.window[0].tbase = *(vulp)T2_TBASE1;
  334. t2_saved_config.window[1].wbase = *(vulp)T2_WBASE2;
  335. t2_saved_config.window[1].wmask = *(vulp)T2_WMASK2;
  336. t2_saved_config.window[1].tbase = *(vulp)T2_TBASE2;
  337. t2_saved_config.hae_1 = srm_hae; /* HW is already set to 0 */
  338. t2_saved_config.hae_2 = *(vulp)T2_HAE_2;
  339. t2_saved_config.hae_3 = *(vulp)T2_HAE_3;
  340. t2_saved_config.hae_4 = *(vulp)T2_HAE_4;
  341. t2_saved_config.hbase = *(vulp)T2_HBASE;
  342. }
  343. void __init
  344. t2_init_arch(void)
  345. {
  346. struct pci_controller *hose;
  347. unsigned long temp;
  348. unsigned int i;
  349. for (i = 0; i < NR_CPUS; i++) {
  350. mcheck_expected(i) = 0;
  351. mcheck_taken(i) = 0;
  352. }
  353. t2_mcheck_any_expected = 0;
  354. t2_mcheck_last_taken = 0;
  355. /* Enable scatter/gather TLB use. */
  356. temp = *(vulp)T2_IOCSR;
  357. if (!(temp & (0x1UL << 26))) {
  358. printk("t2_init_arch: enabling SG TLB, IOCSR was 0x%lx\n",
  359. temp);
  360. *(vulp)T2_IOCSR = temp | (0x1UL << 26);
  361. mb();
  362. *(vulp)T2_IOCSR; /* read it back to make sure */
  363. }
  364. t2_save_configuration();
  365. /*
  366. * Create our single hose.
  367. */
  368. pci_isa_hose = hose = alloc_pci_controller();
  369. hose->io_space = &ioport_resource;
  370. hose->mem_space = &iomem_resource;
  371. hose->index = 0;
  372. hose->sparse_mem_base = T2_SPARSE_MEM - IDENT_ADDR;
  373. hose->dense_mem_base = T2_DENSE_MEM - IDENT_ADDR;
  374. hose->sparse_io_base = T2_IO - IDENT_ADDR;
  375. hose->dense_io_base = 0;
  376. /*
  377. * Set up the PCI->physical memory translation windows.
  378. *
  379. * Window 1 is direct mapped.
  380. * Window 2 is scatter/gather (for ISA).
  381. */
  382. t2_direct_map_window1(T2_DIRECTMAP_START, T2_DIRECTMAP_LENGTH);
  383. /* Always make an ISA DMA window. */
  384. t2_sg_map_window2(hose, T2_ISA_SG_START, T2_ISA_SG_LENGTH);
  385. *(vulp)T2_HBASE = 0x0; /* Disable HOLES. */
  386. /* Zero HAE. */
  387. *(vulp)T2_HAE_1 = 0; mb(); /* Sparse MEM HAE */
  388. *(vulp)T2_HAE_2 = 0; mb(); /* Sparse I/O HAE */
  389. *(vulp)T2_HAE_3 = 0; mb(); /* Config Space HAE */
  390. /*
  391. * We also now zero out HAE_4, the dense memory HAE, so that
  392. * we need not account for its "offset" when accessing dense
  393. * memory resources which we allocated in our normal way. This
  394. * HAE would need to stay untouched were we to keep the SRM
  395. * resource settings.
  396. *
  397. * Thus we can now run standard X servers on SABLE/LYNX. :-)
  398. */
  399. *(vulp)T2_HAE_4 = 0; mb();
  400. }
  401. void
  402. t2_kill_arch(int mode)
  403. {
  404. /*
  405. * Restore the DMA Window registers.
  406. */
  407. *(vulp)T2_WBASE1 = t2_saved_config.window[0].wbase;
  408. *(vulp)T2_WMASK1 = t2_saved_config.window[0].wmask;
  409. *(vulp)T2_TBASE1 = t2_saved_config.window[0].tbase;
  410. *(vulp)T2_WBASE2 = t2_saved_config.window[1].wbase;
  411. *(vulp)T2_WMASK2 = t2_saved_config.window[1].wmask;
  412. *(vulp)T2_TBASE2 = t2_saved_config.window[1].tbase;
  413. mb();
  414. *(vulp)T2_HAE_1 = srm_hae;
  415. *(vulp)T2_HAE_2 = t2_saved_config.hae_2;
  416. *(vulp)T2_HAE_3 = t2_saved_config.hae_3;
  417. *(vulp)T2_HAE_4 = t2_saved_config.hae_4;
  418. *(vulp)T2_HBASE = t2_saved_config.hbase;
  419. mb();
  420. *(vulp)T2_HBASE; /* READ it back to ensure WRITE occurred. */
  421. }
  422. void
  423. t2_pci_tbi(struct pci_controller *hose, dma_addr_t start, dma_addr_t end)
  424. {
  425. unsigned long t2_iocsr;
  426. t2_iocsr = *(vulp)T2_IOCSR;
  427. /* set the TLB Clear bit */
  428. *(vulp)T2_IOCSR = t2_iocsr | (0x1UL << 28);
  429. mb();
  430. *(vulp)T2_IOCSR; /* read it back to make sure */
  431. /* clear the TLB Clear bit */
  432. *(vulp)T2_IOCSR = t2_iocsr & ~(0x1UL << 28);
  433. mb();
  434. *(vulp)T2_IOCSR; /* read it back to make sure */
  435. }
  436. #define SIC_SEIC (1UL << 33) /* System Event Clear */
  437. static void
  438. t2_clear_errors(int cpu)
  439. {
  440. struct sable_cpu_csr *cpu_regs;
  441. cpu_regs = (struct sable_cpu_csr *)T2_CPUn_BASE(cpu);
  442. cpu_regs->sic &= ~SIC_SEIC;
  443. /* Clear CPU errors. */
  444. cpu_regs->bcce |= cpu_regs->bcce;
  445. cpu_regs->cbe |= cpu_regs->cbe;
  446. cpu_regs->bcue |= cpu_regs->bcue;
  447. cpu_regs->dter |= cpu_regs->dter;
  448. *(vulp)T2_CERR1 |= *(vulp)T2_CERR1;
  449. *(vulp)T2_PERR1 |= *(vulp)T2_PERR1;
  450. mb();
  451. mb(); /* magic */
  452. }
  453. /*
  454. * SABLE seems to have a "broadcast" style machine check, in that all
  455. * CPUs receive it. And, the issuing CPU, in the case of PCI Config
  456. * space read/write faults, will also receive a second mcheck, upon
  457. * lowering IPL during completion processing in pci_read_config_byte()
  458. * et al.
  459. *
  460. * Hence all the taken/expected/any_expected/last_taken stuff...
  461. */
  462. void
  463. t2_machine_check(unsigned long vector, unsigned long la_ptr)
  464. {
  465. int cpu = smp_processor_id();
  466. #ifdef CONFIG_VERBOSE_MCHECK
  467. struct el_common *mchk_header = (struct el_common *)la_ptr;
  468. #endif
  469. /* Clear the error before any reporting. */
  470. mb();
  471. mb(); /* magic */
  472. draina();
  473. t2_clear_errors(cpu);
  474. /* This should not actually be done until the logout frame is
  475. examined, but, since we don't do that, go on and do this... */
  476. wrmces(0x7);
  477. mb();
  478. /* Now, do testing for the anomalous conditions. */
  479. if (!mcheck_expected(cpu) && t2_mcheck_any_expected) {
  480. /*
  481. * FUNKY: Received mcheck on a CPU and not
  482. * expecting it, but another CPU is expecting one.
  483. *
  484. * Just dismiss it for now on this CPU...
  485. */
  486. #ifdef CONFIG_VERBOSE_MCHECK
  487. if (alpha_verbose_mcheck > 1) {
  488. printk("t2_machine_check(cpu%d): any_expected 0x%x -"
  489. " (assumed) spurious -"
  490. " code 0x%x\n", cpu, t2_mcheck_any_expected,
  491. (unsigned int)mchk_header->code);
  492. }
  493. #endif
  494. return;
  495. }
  496. if (!mcheck_expected(cpu) && !t2_mcheck_any_expected) {
  497. if (t2_mcheck_last_taken & (1 << cpu)) {
  498. #ifdef CONFIG_VERBOSE_MCHECK
  499. if (alpha_verbose_mcheck > 1) {
  500. printk("t2_machine_check(cpu%d): last_taken 0x%x - "
  501. "unexpected mcheck - code 0x%x\n",
  502. cpu, t2_mcheck_last_taken,
  503. (unsigned int)mchk_header->code);
  504. }
  505. #endif
  506. t2_mcheck_last_taken = 0;
  507. mb();
  508. return;
  509. } else {
  510. t2_mcheck_last_taken = 0;
  511. mb();
  512. }
  513. }
  514. #ifdef CONFIG_VERBOSE_MCHECK
  515. if (alpha_verbose_mcheck > 1) {
  516. printk("%s t2_mcheck(cpu%d): last_taken 0x%x - "
  517. "any_expected 0x%x - code 0x%x\n",
  518. (mcheck_expected(cpu) ? "EX" : "UN"), cpu,
  519. t2_mcheck_last_taken, t2_mcheck_any_expected,
  520. (unsigned int)mchk_header->code);
  521. }
  522. #endif
  523. process_mcheck_info(vector, la_ptr, "T2", mcheck_expected(cpu));
  524. }