dhd_sdio.c 110 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/kernel.h>
  18. #include <linux/kthread.h>
  19. #include <linux/printk.h>
  20. #include <linux/pci_ids.h>
  21. #include <linux/netdevice.h>
  22. #include <linux/interrupt.h>
  23. #include <linux/sched.h>
  24. #include <linux/mmc/sdio.h>
  25. #include <linux/mmc/sdio_func.h>
  26. #include <linux/mmc/card.h>
  27. #include <linux/semaphore.h>
  28. #include <linux/firmware.h>
  29. #include <linux/module.h>
  30. #include <asm/unaligned.h>
  31. #include <defs.h>
  32. #include <brcmu_wifi.h>
  33. #include <brcmu_utils.h>
  34. #include <brcm_hw_ids.h>
  35. #include <soc.h>
  36. #include "sdio_host.h"
  37. #include "sdio_chip.h"
  38. #define DCMD_RESP_TIMEOUT 2000 /* In milli second */
  39. #ifdef BCMDBG
  40. #define BRCMF_TRAP_INFO_SIZE 80
  41. #define CBUF_LEN (128)
  42. struct rte_log_le {
  43. __le32 buf; /* Can't be pointer on (64-bit) hosts */
  44. __le32 buf_size;
  45. __le32 idx;
  46. char *_buf_compat; /* Redundant pointer for backward compat. */
  47. };
  48. struct rte_console {
  49. /* Virtual UART
  50. * When there is no UART (e.g. Quickturn),
  51. * the host should write a complete
  52. * input line directly into cbuf and then write
  53. * the length into vcons_in.
  54. * This may also be used when there is a real UART
  55. * (at risk of conflicting with
  56. * the real UART). vcons_out is currently unused.
  57. */
  58. uint vcons_in;
  59. uint vcons_out;
  60. /* Output (logging) buffer
  61. * Console output is written to a ring buffer log_buf at index log_idx.
  62. * The host may read the output when it sees log_idx advance.
  63. * Output will be lost if the output wraps around faster than the host
  64. * polls.
  65. */
  66. struct rte_log_le log_le;
  67. /* Console input line buffer
  68. * Characters are read one at a time into cbuf
  69. * until <CR> is received, then
  70. * the buffer is processed as a command line.
  71. * Also used for virtual UART.
  72. */
  73. uint cbuf_idx;
  74. char cbuf[CBUF_LEN];
  75. };
  76. #endif /* BCMDBG */
  77. #include <chipcommon.h>
  78. #include "dhd.h"
  79. #include "dhd_bus.h"
  80. #include "dhd_proto.h"
  81. #include "dhd_dbg.h"
  82. #include <bcmchip.h>
  83. #define TXQLEN 2048 /* bulk tx queue length */
  84. #define TXHI (TXQLEN - 256) /* turn on flow control above TXHI */
  85. #define TXLOW (TXHI - 256) /* turn off flow control below TXLOW */
  86. #define PRIOMASK 7
  87. #define TXRETRIES 2 /* # of retries for tx frames */
  88. #define BRCMF_RXBOUND 50 /* Default for max rx frames in
  89. one scheduling */
  90. #define BRCMF_TXBOUND 20 /* Default for max tx frames in
  91. one scheduling */
  92. #define BRCMF_TXMINMAX 1 /* Max tx frames if rx still pending */
  93. #define MEMBLOCK 2048 /* Block size used for downloading
  94. of dongle image */
  95. #define MAX_DATA_BUF (32 * 1024) /* Must be large enough to hold
  96. biggest possible glom */
  97. #define BRCMF_FIRSTREAD (1 << 6)
  98. /* SBSDIO_DEVICE_CTL */
  99. /* 1: device will assert busy signal when receiving CMD53 */
  100. #define SBSDIO_DEVCTL_SETBUSY 0x01
  101. /* 1: assertion of sdio interrupt is synchronous to the sdio clock */
  102. #define SBSDIO_DEVCTL_SPI_INTR_SYNC 0x02
  103. /* 1: mask all interrupts to host except the chipActive (rev 8) */
  104. #define SBSDIO_DEVCTL_CA_INT_ONLY 0x04
  105. /* 1: isolate internal sdio signals, put external pads in tri-state; requires
  106. * sdio bus power cycle to clear (rev 9) */
  107. #define SBSDIO_DEVCTL_PADS_ISO 0x08
  108. /* Force SD->SB reset mapping (rev 11) */
  109. #define SBSDIO_DEVCTL_SB_RST_CTL 0x30
  110. /* Determined by CoreControl bit */
  111. #define SBSDIO_DEVCTL_RST_CORECTL 0x00
  112. /* Force backplane reset */
  113. #define SBSDIO_DEVCTL_RST_BPRESET 0x10
  114. /* Force no backplane reset */
  115. #define SBSDIO_DEVCTL_RST_NOBPRESET 0x20
  116. /* direct(mapped) cis space */
  117. /* MAPPED common CIS address */
  118. #define SBSDIO_CIS_BASE_COMMON 0x1000
  119. /* maximum bytes in one CIS */
  120. #define SBSDIO_CIS_SIZE_LIMIT 0x200
  121. /* cis offset addr is < 17 bits */
  122. #define SBSDIO_CIS_OFT_ADDR_MASK 0x1FFFF
  123. /* manfid tuple length, include tuple, link bytes */
  124. #define SBSDIO_CIS_MANFID_TUPLE_LEN 6
  125. /* intstatus */
  126. #define I_SMB_SW0 (1 << 0) /* To SB Mail S/W interrupt 0 */
  127. #define I_SMB_SW1 (1 << 1) /* To SB Mail S/W interrupt 1 */
  128. #define I_SMB_SW2 (1 << 2) /* To SB Mail S/W interrupt 2 */
  129. #define I_SMB_SW3 (1 << 3) /* To SB Mail S/W interrupt 3 */
  130. #define I_SMB_SW_MASK 0x0000000f /* To SB Mail S/W interrupts mask */
  131. #define I_SMB_SW_SHIFT 0 /* To SB Mail S/W interrupts shift */
  132. #define I_HMB_SW0 (1 << 4) /* To Host Mail S/W interrupt 0 */
  133. #define I_HMB_SW1 (1 << 5) /* To Host Mail S/W interrupt 1 */
  134. #define I_HMB_SW2 (1 << 6) /* To Host Mail S/W interrupt 2 */
  135. #define I_HMB_SW3 (1 << 7) /* To Host Mail S/W interrupt 3 */
  136. #define I_HMB_SW_MASK 0x000000f0 /* To Host Mail S/W interrupts mask */
  137. #define I_HMB_SW_SHIFT 4 /* To Host Mail S/W interrupts shift */
  138. #define I_WR_OOSYNC (1 << 8) /* Write Frame Out Of Sync */
  139. #define I_RD_OOSYNC (1 << 9) /* Read Frame Out Of Sync */
  140. #define I_PC (1 << 10) /* descriptor error */
  141. #define I_PD (1 << 11) /* data error */
  142. #define I_DE (1 << 12) /* Descriptor protocol Error */
  143. #define I_RU (1 << 13) /* Receive descriptor Underflow */
  144. #define I_RO (1 << 14) /* Receive fifo Overflow */
  145. #define I_XU (1 << 15) /* Transmit fifo Underflow */
  146. #define I_RI (1 << 16) /* Receive Interrupt */
  147. #define I_BUSPWR (1 << 17) /* SDIO Bus Power Change (rev 9) */
  148. #define I_XMTDATA_AVAIL (1 << 23) /* bits in fifo */
  149. #define I_XI (1 << 24) /* Transmit Interrupt */
  150. #define I_RF_TERM (1 << 25) /* Read Frame Terminate */
  151. #define I_WF_TERM (1 << 26) /* Write Frame Terminate */
  152. #define I_PCMCIA_XU (1 << 27) /* PCMCIA Transmit FIFO Underflow */
  153. #define I_SBINT (1 << 28) /* sbintstatus Interrupt */
  154. #define I_CHIPACTIVE (1 << 29) /* chip from doze to active state */
  155. #define I_SRESET (1 << 30) /* CCCR RES interrupt */
  156. #define I_IOE2 (1U << 31) /* CCCR IOE2 Bit Changed */
  157. #define I_ERRORS (I_PC | I_PD | I_DE | I_RU | I_RO | I_XU)
  158. #define I_DMA (I_RI | I_XI | I_ERRORS)
  159. /* corecontrol */
  160. #define CC_CISRDY (1 << 0) /* CIS Ready */
  161. #define CC_BPRESEN (1 << 1) /* CCCR RES signal */
  162. #define CC_F2RDY (1 << 2) /* set CCCR IOR2 bit */
  163. #define CC_CLRPADSISO (1 << 3) /* clear SDIO pads isolation */
  164. #define CC_XMTDATAAVAIL_MODE (1 << 4)
  165. #define CC_XMTDATAAVAIL_CTRL (1 << 5)
  166. /* SDA_FRAMECTRL */
  167. #define SFC_RF_TERM (1 << 0) /* Read Frame Terminate */
  168. #define SFC_WF_TERM (1 << 1) /* Write Frame Terminate */
  169. #define SFC_CRC4WOOS (1 << 2) /* CRC error for write out of sync */
  170. #define SFC_ABORTALL (1 << 3) /* Abort all in-progress frames */
  171. /* HW frame tag */
  172. #define SDPCM_FRAMETAG_LEN 4 /* 2 bytes len, 2 bytes check val */
  173. /* Total length of frame header for dongle protocol */
  174. #define SDPCM_HDRLEN (SDPCM_FRAMETAG_LEN + SDPCM_SWHEADER_LEN)
  175. #define SDPCM_RESERVE (SDPCM_HDRLEN + BRCMF_SDALIGN)
  176. /*
  177. * Software allocation of To SB Mailbox resources
  178. */
  179. /* tosbmailbox bits corresponding to intstatus bits */
  180. #define SMB_NAK (1 << 0) /* Frame NAK */
  181. #define SMB_INT_ACK (1 << 1) /* Host Interrupt ACK */
  182. #define SMB_USE_OOB (1 << 2) /* Use OOB Wakeup */
  183. #define SMB_DEV_INT (1 << 3) /* Miscellaneous Interrupt */
  184. /* tosbmailboxdata */
  185. #define SMB_DATA_VERSION_SHIFT 16 /* host protocol version */
  186. /*
  187. * Software allocation of To Host Mailbox resources
  188. */
  189. /* intstatus bits */
  190. #define I_HMB_FC_STATE I_HMB_SW0 /* Flow Control State */
  191. #define I_HMB_FC_CHANGE I_HMB_SW1 /* Flow Control State Changed */
  192. #define I_HMB_FRAME_IND I_HMB_SW2 /* Frame Indication */
  193. #define I_HMB_HOST_INT I_HMB_SW3 /* Miscellaneous Interrupt */
  194. /* tohostmailboxdata */
  195. #define HMB_DATA_NAKHANDLED 1 /* retransmit NAK'd frame */
  196. #define HMB_DATA_DEVREADY 2 /* talk to host after enable */
  197. #define HMB_DATA_FC 4 /* per prio flowcontrol update flag */
  198. #define HMB_DATA_FWREADY 8 /* fw ready for protocol activity */
  199. #define HMB_DATA_FCDATA_MASK 0xff000000
  200. #define HMB_DATA_FCDATA_SHIFT 24
  201. #define HMB_DATA_VERSION_MASK 0x00ff0000
  202. #define HMB_DATA_VERSION_SHIFT 16
  203. /*
  204. * Software-defined protocol header
  205. */
  206. /* Current protocol version */
  207. #define SDPCM_PROT_VERSION 4
  208. /* SW frame header */
  209. #define SDPCM_PACKET_SEQUENCE(p) (((u8 *)p)[0] & 0xff)
  210. #define SDPCM_CHANNEL_MASK 0x00000f00
  211. #define SDPCM_CHANNEL_SHIFT 8
  212. #define SDPCM_PACKET_CHANNEL(p) (((u8 *)p)[1] & 0x0f)
  213. #define SDPCM_NEXTLEN_OFFSET 2
  214. /* Data Offset from SOF (HW Tag, SW Tag, Pad) */
  215. #define SDPCM_DOFFSET_OFFSET 3 /* Data Offset */
  216. #define SDPCM_DOFFSET_VALUE(p) (((u8 *)p)[SDPCM_DOFFSET_OFFSET] & 0xff)
  217. #define SDPCM_DOFFSET_MASK 0xff000000
  218. #define SDPCM_DOFFSET_SHIFT 24
  219. #define SDPCM_FCMASK_OFFSET 4 /* Flow control */
  220. #define SDPCM_FCMASK_VALUE(p) (((u8 *)p)[SDPCM_FCMASK_OFFSET] & 0xff)
  221. #define SDPCM_WINDOW_OFFSET 5 /* Credit based fc */
  222. #define SDPCM_WINDOW_VALUE(p) (((u8 *)p)[SDPCM_WINDOW_OFFSET] & 0xff)
  223. #define SDPCM_SWHEADER_LEN 8 /* SW header is 64 bits */
  224. /* logical channel numbers */
  225. #define SDPCM_CONTROL_CHANNEL 0 /* Control channel Id */
  226. #define SDPCM_EVENT_CHANNEL 1 /* Asyc Event Indication Channel Id */
  227. #define SDPCM_DATA_CHANNEL 2 /* Data Xmit/Recv Channel Id */
  228. #define SDPCM_GLOM_CHANNEL 3 /* For coalesced packets */
  229. #define SDPCM_TEST_CHANNEL 15 /* Reserved for test/debug packets */
  230. #define SDPCM_SEQUENCE_WRAP 256 /* wrap-around val for 8bit frame seq */
  231. #define SDPCM_GLOMDESC(p) (((u8 *)p)[1] & 0x80)
  232. /*
  233. * Shared structure between dongle and the host.
  234. * The structure contains pointers to trap or assert information.
  235. */
  236. #define SDPCM_SHARED_VERSION 0x0002
  237. #define SDPCM_SHARED_VERSION_MASK 0x00FF
  238. #define SDPCM_SHARED_ASSERT_BUILT 0x0100
  239. #define SDPCM_SHARED_ASSERT 0x0200
  240. #define SDPCM_SHARED_TRAP 0x0400
  241. /* Space for header read, limit for data packets */
  242. #define MAX_HDR_READ (1 << 6)
  243. #define MAX_RX_DATASZ 2048
  244. /* Maximum milliseconds to wait for F2 to come up */
  245. #define BRCMF_WAIT_F2RDY 3000
  246. /* Bump up limit on waiting for HT to account for first startup;
  247. * if the image is doing a CRC calculation before programming the PMU
  248. * for HT availability, it could take a couple hundred ms more, so
  249. * max out at a 1 second (1000000us).
  250. */
  251. #undef PMU_MAX_TRANSITION_DLY
  252. #define PMU_MAX_TRANSITION_DLY 1000000
  253. /* Value for ChipClockCSR during initial setup */
  254. #define BRCMF_INIT_CLKCTL1 (SBSDIO_FORCE_HW_CLKREQ_OFF | \
  255. SBSDIO_ALP_AVAIL_REQ)
  256. /* Flags for SDH calls */
  257. #define F2SYNC (SDIO_REQ_4BYTE | SDIO_REQ_FIXED)
  258. /*
  259. * Conversion of 802.1D priority to precedence level
  260. */
  261. static uint prio2prec(u32 prio)
  262. {
  263. return (prio == PRIO_8021D_NONE || prio == PRIO_8021D_BE) ?
  264. (prio^2) : prio;
  265. }
  266. /* core registers */
  267. struct sdpcmd_regs {
  268. u32 corecontrol; /* 0x00, rev8 */
  269. u32 corestatus; /* rev8 */
  270. u32 PAD[1];
  271. u32 biststatus; /* rev8 */
  272. /* PCMCIA access */
  273. u16 pcmciamesportaladdr; /* 0x010, rev8 */
  274. u16 PAD[1];
  275. u16 pcmciamesportalmask; /* rev8 */
  276. u16 PAD[1];
  277. u16 pcmciawrframebc; /* rev8 */
  278. u16 PAD[1];
  279. u16 pcmciaunderflowtimer; /* rev8 */
  280. u16 PAD[1];
  281. /* interrupt */
  282. u32 intstatus; /* 0x020, rev8 */
  283. u32 hostintmask; /* rev8 */
  284. u32 intmask; /* rev8 */
  285. u32 sbintstatus; /* rev8 */
  286. u32 sbintmask; /* rev8 */
  287. u32 funcintmask; /* rev4 */
  288. u32 PAD[2];
  289. u32 tosbmailbox; /* 0x040, rev8 */
  290. u32 tohostmailbox; /* rev8 */
  291. u32 tosbmailboxdata; /* rev8 */
  292. u32 tohostmailboxdata; /* rev8 */
  293. /* synchronized access to registers in SDIO clock domain */
  294. u32 sdioaccess; /* 0x050, rev8 */
  295. u32 PAD[3];
  296. /* PCMCIA frame control */
  297. u8 pcmciaframectrl; /* 0x060, rev8 */
  298. u8 PAD[3];
  299. u8 pcmciawatermark; /* rev8 */
  300. u8 PAD[155];
  301. /* interrupt batching control */
  302. u32 intrcvlazy; /* 0x100, rev8 */
  303. u32 PAD[3];
  304. /* counters */
  305. u32 cmd52rd; /* 0x110, rev8 */
  306. u32 cmd52wr; /* rev8 */
  307. u32 cmd53rd; /* rev8 */
  308. u32 cmd53wr; /* rev8 */
  309. u32 abort; /* rev8 */
  310. u32 datacrcerror; /* rev8 */
  311. u32 rdoutofsync; /* rev8 */
  312. u32 wroutofsync; /* rev8 */
  313. u32 writebusy; /* rev8 */
  314. u32 readwait; /* rev8 */
  315. u32 readterm; /* rev8 */
  316. u32 writeterm; /* rev8 */
  317. u32 PAD[40];
  318. u32 clockctlstatus; /* rev8 */
  319. u32 PAD[7];
  320. u32 PAD[128]; /* DMA engines */
  321. /* SDIO/PCMCIA CIS region */
  322. char cis[512]; /* 0x400-0x5ff, rev6 */
  323. /* PCMCIA function control registers */
  324. char pcmciafcr[256]; /* 0x600-6ff, rev6 */
  325. u16 PAD[55];
  326. /* PCMCIA backplane access */
  327. u16 backplanecsr; /* 0x76E, rev6 */
  328. u16 backplaneaddr0; /* rev6 */
  329. u16 backplaneaddr1; /* rev6 */
  330. u16 backplaneaddr2; /* rev6 */
  331. u16 backplaneaddr3; /* rev6 */
  332. u16 backplanedata0; /* rev6 */
  333. u16 backplanedata1; /* rev6 */
  334. u16 backplanedata2; /* rev6 */
  335. u16 backplanedata3; /* rev6 */
  336. u16 PAD[31];
  337. /* sprom "size" & "blank" info */
  338. u16 spromstatus; /* 0x7BE, rev2 */
  339. u32 PAD[464];
  340. u16 PAD[0x80];
  341. };
  342. #ifdef BCMDBG
  343. /* Device console log buffer state */
  344. struct brcmf_console {
  345. uint count; /* Poll interval msec counter */
  346. uint log_addr; /* Log struct address (fixed) */
  347. struct rte_log_le log_le; /* Log struct (host copy) */
  348. uint bufsize; /* Size of log buffer */
  349. u8 *buf; /* Log buffer (host copy) */
  350. uint last; /* Last buffer read index */
  351. };
  352. #endif /* BCMDBG */
  353. struct sdpcm_shared {
  354. u32 flags;
  355. u32 trap_addr;
  356. u32 assert_exp_addr;
  357. u32 assert_file_addr;
  358. u32 assert_line;
  359. u32 console_addr; /* Address of struct rte_console */
  360. u32 msgtrace_addr;
  361. u8 tag[32];
  362. };
  363. struct sdpcm_shared_le {
  364. __le32 flags;
  365. __le32 trap_addr;
  366. __le32 assert_exp_addr;
  367. __le32 assert_file_addr;
  368. __le32 assert_line;
  369. __le32 console_addr; /* Address of struct rte_console */
  370. __le32 msgtrace_addr;
  371. u8 tag[32];
  372. };
  373. /* misc chip info needed by some of the routines */
  374. /* Private data for SDIO bus interaction */
  375. struct brcmf_bus {
  376. struct brcmf_pub *drvr;
  377. struct brcmf_sdio_dev *sdiodev; /* sdio device handler */
  378. struct chip_info *ci; /* Chip info struct */
  379. char *vars; /* Variables (from CIS and/or other) */
  380. uint varsz; /* Size of variables buffer */
  381. u32 ramsize; /* Size of RAM in SOCRAM (bytes) */
  382. u32 hostintmask; /* Copy of Host Interrupt Mask */
  383. u32 intstatus; /* Intstatus bits (events) pending */
  384. bool dpc_sched; /* Indicates DPC schedule (intrpt rcvd) */
  385. bool fcstate; /* State of dongle flow-control */
  386. uint blocksize; /* Block size of SDIO transfers */
  387. uint roundup; /* Max roundup limit */
  388. struct pktq txq; /* Queue length used for flow-control */
  389. u8 flowcontrol; /* per prio flow control bitmask */
  390. u8 tx_seq; /* Transmit sequence number (next) */
  391. u8 tx_max; /* Maximum transmit sequence allowed */
  392. u8 hdrbuf[MAX_HDR_READ + BRCMF_SDALIGN];
  393. u8 *rxhdr; /* Header of current rx frame (in hdrbuf) */
  394. u16 nextlen; /* Next Read Len from last header */
  395. u8 rx_seq; /* Receive sequence number (expected) */
  396. bool rxskip; /* Skip receive (awaiting NAK ACK) */
  397. uint rxbound; /* Rx frames to read before resched */
  398. uint txbound; /* Tx frames to send before resched */
  399. uint txminmax;
  400. struct sk_buff *glomd; /* Packet containing glomming descriptor */
  401. struct sk_buff_head glom; /* Packet list for glommed superframe */
  402. uint glomerr; /* Glom packet read errors */
  403. u8 *rxbuf; /* Buffer for receiving control packets */
  404. uint rxblen; /* Allocated length of rxbuf */
  405. u8 *rxctl; /* Aligned pointer into rxbuf */
  406. u8 *databuf; /* Buffer for receiving big glom packet */
  407. u8 *dataptr; /* Aligned pointer into databuf */
  408. uint rxlen; /* Length of valid data in buffer */
  409. u8 sdpcm_ver; /* Bus protocol reported by dongle */
  410. bool intr; /* Use interrupts */
  411. bool poll; /* Use polling */
  412. bool ipend; /* Device interrupt is pending */
  413. uint intrcount; /* Count of device interrupt callbacks */
  414. uint lastintrs; /* Count as of last watchdog timer */
  415. uint spurious; /* Count of spurious interrupts */
  416. uint pollrate; /* Ticks between device polls */
  417. uint polltick; /* Tick counter */
  418. uint pollcnt; /* Count of active polls */
  419. #ifdef BCMDBG
  420. uint console_interval;
  421. struct brcmf_console console; /* Console output polling support */
  422. uint console_addr; /* Console address from shared struct */
  423. #endif /* BCMDBG */
  424. uint regfails; /* Count of R_REG failures */
  425. uint clkstate; /* State of sd and backplane clock(s) */
  426. bool activity; /* Activity flag for clock down */
  427. s32 idletime; /* Control for activity timeout */
  428. s32 idlecount; /* Activity timeout counter */
  429. s32 idleclock; /* How to set bus driver when idle */
  430. s32 sd_rxchain;
  431. bool use_rxchain; /* If brcmf should use PKT chains */
  432. bool sleeping; /* Is SDIO bus sleeping? */
  433. bool rxflow_mode; /* Rx flow control mode */
  434. bool rxflow; /* Is rx flow control on */
  435. bool alp_only; /* Don't use HT clock (ALP only) */
  436. /* Field to decide if rx of control frames happen in rxbuf or lb-pool */
  437. bool usebufpool;
  438. /* Some additional counters */
  439. uint tx_sderrs; /* Count of tx attempts with sd errors */
  440. uint fcqueued; /* Tx packets that got queued */
  441. uint rxrtx; /* Count of rtx requests (NAK to dongle) */
  442. uint rx_toolong; /* Receive frames too long to receive */
  443. uint rxc_errors; /* SDIO errors when reading control frames */
  444. uint rx_hdrfail; /* SDIO errors on header reads */
  445. uint rx_badhdr; /* Bad received headers (roosync?) */
  446. uint rx_badseq; /* Mismatched rx sequence number */
  447. uint fc_rcvd; /* Number of flow-control events received */
  448. uint fc_xoff; /* Number which turned on flow-control */
  449. uint fc_xon; /* Number which turned off flow-control */
  450. uint rxglomfail; /* Failed deglom attempts */
  451. uint rxglomframes; /* Number of glom frames (superframes) */
  452. uint rxglompkts; /* Number of packets from glom frames */
  453. uint f2rxhdrs; /* Number of header reads */
  454. uint f2rxdata; /* Number of frame data reads */
  455. uint f2txdata; /* Number of f2 frame writes */
  456. uint f1regdata; /* Number of f1 register accesses */
  457. u8 *ctrl_frame_buf;
  458. u32 ctrl_frame_len;
  459. bool ctrl_frame_stat;
  460. spinlock_t txqlock;
  461. wait_queue_head_t ctrl_wait;
  462. wait_queue_head_t dcmd_resp_wait;
  463. struct timer_list timer;
  464. struct completion watchdog_wait;
  465. struct task_struct *watchdog_tsk;
  466. bool wd_timer_valid;
  467. uint save_ms;
  468. struct task_struct *dpc_tsk;
  469. struct completion dpc_wait;
  470. struct semaphore sdsem;
  471. const char *fw_name;
  472. const struct firmware *firmware;
  473. const char *nv_name;
  474. u32 fw_ptr;
  475. };
  476. /* clkstate */
  477. #define CLK_NONE 0
  478. #define CLK_SDONLY 1
  479. #define CLK_PENDING 2 /* Not used yet */
  480. #define CLK_AVAIL 3
  481. #ifdef BCMDBG
  482. static int qcount[NUMPRIO];
  483. static int tx_packets[NUMPRIO];
  484. #endif /* BCMDBG */
  485. #define SDIO_DRIVE_STRENGTH 6 /* in milliamps */
  486. #define RETRYCHAN(chan) ((chan) == SDPCM_EVENT_CHANNEL)
  487. /* Retry count for register access failures */
  488. static const uint retry_limit = 2;
  489. /* Limit on rounding up frames */
  490. static const uint max_roundup = 512;
  491. #define ALIGNMENT 4
  492. static void pkt_align(struct sk_buff *p, int len, int align)
  493. {
  494. uint datalign;
  495. datalign = (unsigned long)(p->data);
  496. datalign = roundup(datalign, (align)) - datalign;
  497. if (datalign)
  498. skb_pull(p, datalign);
  499. __skb_trim(p, len);
  500. }
  501. /* To check if there's window offered */
  502. static bool data_ok(struct brcmf_bus *bus)
  503. {
  504. return (u8)(bus->tx_max - bus->tx_seq) != 0 &&
  505. ((u8)(bus->tx_max - bus->tx_seq) & 0x80) == 0;
  506. }
  507. /*
  508. * Reads a register in the SDIO hardware block. This block occupies a series of
  509. * adresses on the 32 bit backplane bus.
  510. */
  511. static void
  512. r_sdreg32(struct brcmf_bus *bus, u32 *regvar, u32 reg_offset, u32 *retryvar)
  513. {
  514. *retryvar = 0;
  515. do {
  516. *regvar = brcmf_sdcard_reg_read(bus->sdiodev,
  517. bus->ci->buscorebase + reg_offset, sizeof(u32));
  518. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  519. (++(*retryvar) <= retry_limit));
  520. if (*retryvar) {
  521. bus->regfails += (*retryvar-1);
  522. if (*retryvar > retry_limit) {
  523. brcmf_dbg(ERROR, "FAILED READ %Xh\n", reg_offset);
  524. *regvar = 0;
  525. }
  526. }
  527. }
  528. static void
  529. w_sdreg32(struct brcmf_bus *bus, u32 regval, u32 reg_offset, u32 *retryvar)
  530. {
  531. *retryvar = 0;
  532. do {
  533. brcmf_sdcard_reg_write(bus->sdiodev,
  534. bus->ci->buscorebase + reg_offset,
  535. sizeof(u32), regval);
  536. } while (brcmf_sdcard_regfail(bus->sdiodev) &&
  537. (++(*retryvar) <= retry_limit));
  538. if (*retryvar) {
  539. bus->regfails += (*retryvar-1);
  540. if (*retryvar > retry_limit)
  541. brcmf_dbg(ERROR, "FAILED REGISTER WRITE %Xh\n",
  542. reg_offset);
  543. }
  544. }
  545. #define PKT_AVAILABLE() (intstatus & I_HMB_FRAME_IND)
  546. #define HOSTINTMASK (I_HMB_SW_MASK | I_CHIPACTIVE)
  547. /* Packet free applicable unconditionally for sdio and sdspi.
  548. * Conditional if bufpool was present for gspi bus.
  549. */
  550. static void brcmf_sdbrcm_pktfree2(struct brcmf_bus *bus, struct sk_buff *pkt)
  551. {
  552. if (bus->usebufpool)
  553. brcmu_pkt_buf_free_skb(pkt);
  554. }
  555. /* Turn backplane clock on or off */
  556. static int brcmf_sdbrcm_htclk(struct brcmf_bus *bus, bool on, bool pendok)
  557. {
  558. int err;
  559. u8 clkctl, clkreq, devctl;
  560. unsigned long timeout;
  561. brcmf_dbg(TRACE, "Enter\n");
  562. clkctl = 0;
  563. if (on) {
  564. /* Request HT Avail */
  565. clkreq =
  566. bus->alp_only ? SBSDIO_ALP_AVAIL_REQ : SBSDIO_HT_AVAIL_REQ;
  567. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  568. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  569. if (err) {
  570. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  571. return -EBADE;
  572. }
  573. if (pendok && ((bus->ci->buscoretype == PCMCIA_CORE_ID)
  574. && (bus->ci->buscorerev == 9))) {
  575. u32 dummy, retries;
  576. r_sdreg32(bus, &dummy,
  577. offsetof(struct sdpcmd_regs, clockctlstatus),
  578. &retries);
  579. }
  580. /* Check current status */
  581. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  582. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  583. if (err) {
  584. brcmf_dbg(ERROR, "HT Avail read error: %d\n", err);
  585. return -EBADE;
  586. }
  587. /* Go to pending and await interrupt if appropriate */
  588. if (!SBSDIO_CLKAV(clkctl, bus->alp_only) && pendok) {
  589. /* Allow only clock-available interrupt */
  590. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  591. SDIO_FUNC_1,
  592. SBSDIO_DEVICE_CTL, &err);
  593. if (err) {
  594. brcmf_dbg(ERROR, "Devctl error setting CA: %d\n",
  595. err);
  596. return -EBADE;
  597. }
  598. devctl |= SBSDIO_DEVCTL_CA_INT_ONLY;
  599. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  600. SBSDIO_DEVICE_CTL, devctl, &err);
  601. brcmf_dbg(INFO, "CLKCTL: set PENDING\n");
  602. bus->clkstate = CLK_PENDING;
  603. return 0;
  604. } else if (bus->clkstate == CLK_PENDING) {
  605. /* Cancel CA-only interrupt filter */
  606. devctl =
  607. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  608. SBSDIO_DEVICE_CTL, &err);
  609. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  610. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  611. SBSDIO_DEVICE_CTL, devctl, &err);
  612. }
  613. /* Otherwise, wait here (polling) for HT Avail */
  614. timeout = jiffies +
  615. msecs_to_jiffies(PMU_MAX_TRANSITION_DLY/1000);
  616. while (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  617. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  618. SDIO_FUNC_1,
  619. SBSDIO_FUNC1_CHIPCLKCSR,
  620. &err);
  621. if (time_after(jiffies, timeout))
  622. break;
  623. else
  624. usleep_range(5000, 10000);
  625. }
  626. if (err) {
  627. brcmf_dbg(ERROR, "HT Avail request error: %d\n", err);
  628. return -EBADE;
  629. }
  630. if (!SBSDIO_CLKAV(clkctl, bus->alp_only)) {
  631. brcmf_dbg(ERROR, "HT Avail timeout (%d): clkctl 0x%02x\n",
  632. PMU_MAX_TRANSITION_DLY, clkctl);
  633. return -EBADE;
  634. }
  635. /* Mark clock available */
  636. bus->clkstate = CLK_AVAIL;
  637. brcmf_dbg(INFO, "CLKCTL: turned ON\n");
  638. #if defined(BCMDBG)
  639. if (bus->alp_only != true) {
  640. if (SBSDIO_ALPONLY(clkctl))
  641. brcmf_dbg(ERROR, "HT Clock should be on\n");
  642. }
  643. #endif /* defined (BCMDBG) */
  644. bus->activity = true;
  645. } else {
  646. clkreq = 0;
  647. if (bus->clkstate == CLK_PENDING) {
  648. /* Cancel CA-only interrupt filter */
  649. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  650. SDIO_FUNC_1,
  651. SBSDIO_DEVICE_CTL, &err);
  652. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  653. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  654. SBSDIO_DEVICE_CTL, devctl, &err);
  655. }
  656. bus->clkstate = CLK_SDONLY;
  657. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  658. SBSDIO_FUNC1_CHIPCLKCSR, clkreq, &err);
  659. brcmf_dbg(INFO, "CLKCTL: turned OFF\n");
  660. if (err) {
  661. brcmf_dbg(ERROR, "Failed access turning clock off: %d\n",
  662. err);
  663. return -EBADE;
  664. }
  665. }
  666. return 0;
  667. }
  668. /* Change idle/active SD state */
  669. static int brcmf_sdbrcm_sdclk(struct brcmf_bus *bus, bool on)
  670. {
  671. brcmf_dbg(TRACE, "Enter\n");
  672. if (on)
  673. bus->clkstate = CLK_SDONLY;
  674. else
  675. bus->clkstate = CLK_NONE;
  676. return 0;
  677. }
  678. /* Transition SD and backplane clock readiness */
  679. static int brcmf_sdbrcm_clkctl(struct brcmf_bus *bus, uint target, bool pendok)
  680. {
  681. #ifdef BCMDBG
  682. uint oldstate = bus->clkstate;
  683. #endif /* BCMDBG */
  684. brcmf_dbg(TRACE, "Enter\n");
  685. /* Early exit if we're already there */
  686. if (bus->clkstate == target) {
  687. if (target == CLK_AVAIL) {
  688. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  689. bus->activity = true;
  690. }
  691. return 0;
  692. }
  693. switch (target) {
  694. case CLK_AVAIL:
  695. /* Make sure SD clock is available */
  696. if (bus->clkstate == CLK_NONE)
  697. brcmf_sdbrcm_sdclk(bus, true);
  698. /* Now request HT Avail on the backplane */
  699. brcmf_sdbrcm_htclk(bus, true, pendok);
  700. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  701. bus->activity = true;
  702. break;
  703. case CLK_SDONLY:
  704. /* Remove HT request, or bring up SD clock */
  705. if (bus->clkstate == CLK_NONE)
  706. brcmf_sdbrcm_sdclk(bus, true);
  707. else if (bus->clkstate == CLK_AVAIL)
  708. brcmf_sdbrcm_htclk(bus, false, false);
  709. else
  710. brcmf_dbg(ERROR, "request for %d -> %d\n",
  711. bus->clkstate, target);
  712. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  713. break;
  714. case CLK_NONE:
  715. /* Make sure to remove HT request */
  716. if (bus->clkstate == CLK_AVAIL)
  717. brcmf_sdbrcm_htclk(bus, false, false);
  718. /* Now remove the SD clock */
  719. brcmf_sdbrcm_sdclk(bus, false);
  720. brcmf_sdbrcm_wd_timer(bus, 0);
  721. break;
  722. }
  723. #ifdef BCMDBG
  724. brcmf_dbg(INFO, "%d -> %d\n", oldstate, bus->clkstate);
  725. #endif /* BCMDBG */
  726. return 0;
  727. }
  728. static int brcmf_sdbrcm_bussleep(struct brcmf_bus *bus, bool sleep)
  729. {
  730. uint retries = 0;
  731. brcmf_dbg(INFO, "request %s (currently %s)\n",
  732. sleep ? "SLEEP" : "WAKE",
  733. bus->sleeping ? "SLEEP" : "WAKE");
  734. /* Done if we're already in the requested state */
  735. if (sleep == bus->sleeping)
  736. return 0;
  737. /* Going to sleep: set the alarm and turn off the lights... */
  738. if (sleep) {
  739. /* Don't sleep if something is pending */
  740. if (bus->dpc_sched || bus->rxskip || pktq_len(&bus->txq))
  741. return -EBUSY;
  742. /* Make sure the controller has the bus up */
  743. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  744. /* Tell device to start using OOB wakeup */
  745. w_sdreg32(bus, SMB_USE_OOB,
  746. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  747. if (retries > retry_limit)
  748. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP, WILL NOT WAKE UP!!\n");
  749. /* Turn off our contribution to the HT clock request */
  750. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  751. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  752. SBSDIO_FUNC1_CHIPCLKCSR,
  753. SBSDIO_FORCE_HW_CLKREQ_OFF, NULL);
  754. /* Isolate the bus */
  755. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  756. SBSDIO_DEVICE_CTL,
  757. SBSDIO_DEVCTL_PADS_ISO, NULL);
  758. /* Change state */
  759. bus->sleeping = true;
  760. } else {
  761. /* Waking up: bus power up is ok, set local state */
  762. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  763. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  764. /* Force pad isolation off if possible
  765. (in case power never toggled) */
  766. if ((bus->ci->buscoretype == PCMCIA_CORE_ID)
  767. && (bus->ci->buscorerev >= 10))
  768. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  769. SBSDIO_DEVICE_CTL, 0, NULL);
  770. /* Make sure the controller has the bus up */
  771. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  772. /* Send misc interrupt to indicate OOB not needed */
  773. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, tosbmailboxdata),
  774. &retries);
  775. if (retries <= retry_limit)
  776. w_sdreg32(bus, SMB_DEV_INT,
  777. offsetof(struct sdpcmd_regs, tosbmailbox),
  778. &retries);
  779. if (retries > retry_limit)
  780. brcmf_dbg(ERROR, "CANNOT SIGNAL CHIP TO CLEAR OOB!!\n");
  781. /* Make sure we have SD bus access */
  782. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  783. /* Change state */
  784. bus->sleeping = false;
  785. }
  786. return 0;
  787. }
  788. static void bus_wake(struct brcmf_bus *bus)
  789. {
  790. if (bus->sleeping)
  791. brcmf_sdbrcm_bussleep(bus, false);
  792. }
  793. static u32 brcmf_sdbrcm_hostmail(struct brcmf_bus *bus)
  794. {
  795. u32 intstatus = 0;
  796. u32 hmb_data;
  797. u8 fcbits;
  798. uint retries = 0;
  799. brcmf_dbg(TRACE, "Enter\n");
  800. /* Read mailbox data and ack that we did so */
  801. r_sdreg32(bus, &hmb_data,
  802. offsetof(struct sdpcmd_regs, tohostmailboxdata), &retries);
  803. if (retries <= retry_limit)
  804. w_sdreg32(bus, SMB_INT_ACK,
  805. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  806. bus->f1regdata += 2;
  807. /* Dongle recomposed rx frames, accept them again */
  808. if (hmb_data & HMB_DATA_NAKHANDLED) {
  809. brcmf_dbg(INFO, "Dongle reports NAK handled, expect rtx of %d\n",
  810. bus->rx_seq);
  811. if (!bus->rxskip)
  812. brcmf_dbg(ERROR, "unexpected NAKHANDLED!\n");
  813. bus->rxskip = false;
  814. intstatus |= I_HMB_FRAME_IND;
  815. }
  816. /*
  817. * DEVREADY does not occur with gSPI.
  818. */
  819. if (hmb_data & (HMB_DATA_DEVREADY | HMB_DATA_FWREADY)) {
  820. bus->sdpcm_ver =
  821. (hmb_data & HMB_DATA_VERSION_MASK) >>
  822. HMB_DATA_VERSION_SHIFT;
  823. if (bus->sdpcm_ver != SDPCM_PROT_VERSION)
  824. brcmf_dbg(ERROR, "Version mismatch, dongle reports %d, "
  825. "expecting %d\n",
  826. bus->sdpcm_ver, SDPCM_PROT_VERSION);
  827. else
  828. brcmf_dbg(INFO, "Dongle ready, protocol version %d\n",
  829. bus->sdpcm_ver);
  830. }
  831. /*
  832. * Flow Control has been moved into the RX headers and this out of band
  833. * method isn't used any more.
  834. * remaining backward compatible with older dongles.
  835. */
  836. if (hmb_data & HMB_DATA_FC) {
  837. fcbits = (hmb_data & HMB_DATA_FCDATA_MASK) >>
  838. HMB_DATA_FCDATA_SHIFT;
  839. if (fcbits & ~bus->flowcontrol)
  840. bus->fc_xoff++;
  841. if (bus->flowcontrol & ~fcbits)
  842. bus->fc_xon++;
  843. bus->fc_rcvd++;
  844. bus->flowcontrol = fcbits;
  845. }
  846. /* Shouldn't be any others */
  847. if (hmb_data & ~(HMB_DATA_DEVREADY |
  848. HMB_DATA_NAKHANDLED |
  849. HMB_DATA_FC |
  850. HMB_DATA_FWREADY |
  851. HMB_DATA_FCDATA_MASK | HMB_DATA_VERSION_MASK))
  852. brcmf_dbg(ERROR, "Unknown mailbox data content: 0x%02x\n",
  853. hmb_data);
  854. return intstatus;
  855. }
  856. static void brcmf_sdbrcm_rxfail(struct brcmf_bus *bus, bool abort, bool rtx)
  857. {
  858. uint retries = 0;
  859. u16 lastrbc;
  860. u8 hi, lo;
  861. int err;
  862. brcmf_dbg(ERROR, "%sterminate frame%s\n",
  863. abort ? "abort command, " : "",
  864. rtx ? ", send NAK" : "");
  865. if (abort)
  866. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  867. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  868. SBSDIO_FUNC1_FRAMECTRL,
  869. SFC_RF_TERM, &err);
  870. bus->f1regdata++;
  871. /* Wait until the packet has been flushed (device/FIFO stable) */
  872. for (lastrbc = retries = 0xffff; retries > 0; retries--) {
  873. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  874. SBSDIO_FUNC1_RFRAMEBCHI, NULL);
  875. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  876. SBSDIO_FUNC1_RFRAMEBCLO, NULL);
  877. bus->f1regdata += 2;
  878. if ((hi == 0) && (lo == 0))
  879. break;
  880. if ((hi > (lastrbc >> 8)) && (lo > (lastrbc & 0x00ff))) {
  881. brcmf_dbg(ERROR, "count growing: last 0x%04x now 0x%04x\n",
  882. lastrbc, (hi << 8) + lo);
  883. }
  884. lastrbc = (hi << 8) + lo;
  885. }
  886. if (!retries)
  887. brcmf_dbg(ERROR, "count never zeroed: last 0x%04x\n", lastrbc);
  888. else
  889. brcmf_dbg(INFO, "flush took %d iterations\n", 0xffff - retries);
  890. if (rtx) {
  891. bus->rxrtx++;
  892. w_sdreg32(bus, SMB_NAK,
  893. offsetof(struct sdpcmd_regs, tosbmailbox), &retries);
  894. bus->f1regdata++;
  895. if (retries <= retry_limit)
  896. bus->rxskip = true;
  897. }
  898. /* Clear partial in any case */
  899. bus->nextlen = 0;
  900. /* If we can't reach the device, signal failure */
  901. if (err || brcmf_sdcard_regfail(bus->sdiodev))
  902. bus->drvr->busstate = BRCMF_BUS_DOWN;
  903. }
  904. /* copy a buffer into a pkt buffer chain */
  905. static uint brcmf_sdbrcm_glom_from_buf(struct brcmf_bus *bus, uint len)
  906. {
  907. uint n, ret = 0;
  908. struct sk_buff *p;
  909. u8 *buf;
  910. buf = bus->dataptr;
  911. /* copy the data */
  912. skb_queue_walk(&bus->glom, p) {
  913. n = min_t(uint, p->len, len);
  914. memcpy(p->data, buf, n);
  915. buf += n;
  916. len -= n;
  917. ret += n;
  918. if (!len)
  919. break;
  920. }
  921. return ret;
  922. }
  923. static u8 brcmf_sdbrcm_rxglom(struct brcmf_bus *bus, u8 rxseq)
  924. {
  925. u16 dlen, totlen;
  926. u8 *dptr, num = 0;
  927. u16 sublen, check;
  928. struct sk_buff *pfirst, *plast, *pnext, *save_pfirst;
  929. int errcode;
  930. u8 chan, seq, doff, sfdoff;
  931. u8 txmax;
  932. int ifidx = 0;
  933. bool usechain = bus->use_rxchain;
  934. /* If packets, issue read(s) and send up packet chain */
  935. /* Return sequence numbers consumed? */
  936. brcmf_dbg(TRACE, "start: glomd %p glom %p\n",
  937. bus->glomd, skb_peek(&bus->glom));
  938. /* If there's a descriptor, generate the packet chain */
  939. if (bus->glomd) {
  940. pfirst = plast = pnext = NULL;
  941. dlen = (u16) (bus->glomd->len);
  942. dptr = bus->glomd->data;
  943. if (!dlen || (dlen & 1)) {
  944. brcmf_dbg(ERROR, "bad glomd len(%d), ignore descriptor\n",
  945. dlen);
  946. dlen = 0;
  947. }
  948. for (totlen = num = 0; dlen; num++) {
  949. /* Get (and move past) next length */
  950. sublen = get_unaligned_le16(dptr);
  951. dlen -= sizeof(u16);
  952. dptr += sizeof(u16);
  953. if ((sublen < SDPCM_HDRLEN) ||
  954. ((num == 0) && (sublen < (2 * SDPCM_HDRLEN)))) {
  955. brcmf_dbg(ERROR, "descriptor len %d bad: %d\n",
  956. num, sublen);
  957. pnext = NULL;
  958. break;
  959. }
  960. if (sublen % BRCMF_SDALIGN) {
  961. brcmf_dbg(ERROR, "sublen %d not multiple of %d\n",
  962. sublen, BRCMF_SDALIGN);
  963. usechain = false;
  964. }
  965. totlen += sublen;
  966. /* For last frame, adjust read len so total
  967. is a block multiple */
  968. if (!dlen) {
  969. sublen +=
  970. (roundup(totlen, bus->blocksize) - totlen);
  971. totlen = roundup(totlen, bus->blocksize);
  972. }
  973. /* Allocate/chain packet for next subframe */
  974. pnext = brcmu_pkt_buf_get_skb(sublen + BRCMF_SDALIGN);
  975. if (pnext == NULL) {
  976. brcmf_dbg(ERROR, "bcm_pkt_buf_get_skb failed, num %d len %d\n",
  977. num, sublen);
  978. break;
  979. }
  980. skb_queue_tail(&bus->glom, pnext);
  981. /* Adhere to start alignment requirements */
  982. pkt_align(pnext, sublen, BRCMF_SDALIGN);
  983. }
  984. /* If all allocations succeeded, save packet chain
  985. in bus structure */
  986. if (pnext) {
  987. brcmf_dbg(GLOM, "allocated %d-byte packet chain for %d subframes\n",
  988. totlen, num);
  989. if (BRCMF_GLOM_ON() && bus->nextlen &&
  990. totlen != bus->nextlen) {
  991. brcmf_dbg(GLOM, "glomdesc mismatch: nextlen %d glomdesc %d rxseq %d\n",
  992. bus->nextlen, totlen, rxseq);
  993. }
  994. pfirst = pnext = NULL;
  995. } else {
  996. if (!skb_queue_empty(&bus->glom))
  997. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  998. skb_unlink(pfirst, &bus->glom);
  999. brcmu_pkt_buf_free_skb(pfirst);
  1000. }
  1001. num = 0;
  1002. }
  1003. /* Done with descriptor packet */
  1004. brcmu_pkt_buf_free_skb(bus->glomd);
  1005. bus->glomd = NULL;
  1006. bus->nextlen = 0;
  1007. }
  1008. /* Ok -- either we just generated a packet chain,
  1009. or had one from before */
  1010. if (!skb_queue_empty(&bus->glom)) {
  1011. if (BRCMF_GLOM_ON()) {
  1012. brcmf_dbg(GLOM, "try superframe read, packet chain:\n");
  1013. skb_queue_walk(&bus->glom, pnext) {
  1014. brcmf_dbg(GLOM, " %p: %p len 0x%04x (%d)\n",
  1015. pnext, (u8 *) (pnext->data),
  1016. pnext->len, pnext->len);
  1017. }
  1018. }
  1019. pfirst = skb_peek(&bus->glom);
  1020. dlen = (u16) brcmu_pkttotlen(pfirst);
  1021. /* Do an SDIO read for the superframe. Configurable iovar to
  1022. * read directly into the chained packet, or allocate a large
  1023. * packet and and copy into the chain.
  1024. */
  1025. if (usechain) {
  1026. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1027. bus->sdiodev->sbwad,
  1028. SDIO_FUNC_2,
  1029. F2SYNC, (u8 *) pfirst->data, dlen,
  1030. pfirst);
  1031. } else if (bus->dataptr) {
  1032. errcode = brcmf_sdcard_recv_buf(bus->sdiodev,
  1033. bus->sdiodev->sbwad,
  1034. SDIO_FUNC_2,
  1035. F2SYNC, bus->dataptr, dlen,
  1036. NULL);
  1037. sublen = (u16) brcmf_sdbrcm_glom_from_buf(bus, dlen);
  1038. if (sublen != dlen) {
  1039. brcmf_dbg(ERROR, "FAILED TO COPY, dlen %d sublen %d\n",
  1040. dlen, sublen);
  1041. errcode = -1;
  1042. }
  1043. pnext = NULL;
  1044. } else {
  1045. brcmf_dbg(ERROR, "COULDN'T ALLOC %d-BYTE GLOM, FORCE FAILURE\n",
  1046. dlen);
  1047. errcode = -1;
  1048. }
  1049. bus->f2rxdata++;
  1050. /* On failure, kill the superframe, allow a couple retries */
  1051. if (errcode < 0) {
  1052. brcmf_dbg(ERROR, "glom read of %d bytes failed: %d\n",
  1053. dlen, errcode);
  1054. bus->drvr->rx_errors++;
  1055. if (bus->glomerr++ < 3) {
  1056. brcmf_sdbrcm_rxfail(bus, true, true);
  1057. } else {
  1058. bus->glomerr = 0;
  1059. brcmf_sdbrcm_rxfail(bus, true, false);
  1060. bus->rxglomfail++;
  1061. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1062. skb_unlink(pfirst, &bus->glom);
  1063. brcmu_pkt_buf_free_skb(pfirst);
  1064. }
  1065. }
  1066. return 0;
  1067. }
  1068. #ifdef BCMDBG
  1069. if (BRCMF_GLOM_ON()) {
  1070. printk(KERN_DEBUG "SUPERFRAME:\n");
  1071. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1072. pfirst->data, min_t(int, pfirst->len, 48));
  1073. }
  1074. #endif
  1075. /* Validate the superframe header */
  1076. dptr = (u8 *) (pfirst->data);
  1077. sublen = get_unaligned_le16(dptr);
  1078. check = get_unaligned_le16(dptr + sizeof(u16));
  1079. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1080. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1081. bus->nextlen = dptr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1082. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1083. brcmf_dbg(INFO, "nextlen too large (%d) seq %d\n",
  1084. bus->nextlen, seq);
  1085. bus->nextlen = 0;
  1086. }
  1087. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1088. txmax = SDPCM_WINDOW_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1089. errcode = 0;
  1090. if ((u16)~(sublen ^ check)) {
  1091. brcmf_dbg(ERROR, "(superframe): HW hdr error: len/check 0x%04x/0x%04x\n",
  1092. sublen, check);
  1093. errcode = -1;
  1094. } else if (roundup(sublen, bus->blocksize) != dlen) {
  1095. brcmf_dbg(ERROR, "(superframe): len 0x%04x, rounded 0x%04x, expect 0x%04x\n",
  1096. sublen, roundup(sublen, bus->blocksize),
  1097. dlen);
  1098. errcode = -1;
  1099. } else if (SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]) !=
  1100. SDPCM_GLOM_CHANNEL) {
  1101. brcmf_dbg(ERROR, "(superframe): bad channel %d\n",
  1102. SDPCM_PACKET_CHANNEL(
  1103. &dptr[SDPCM_FRAMETAG_LEN]));
  1104. errcode = -1;
  1105. } else if (SDPCM_GLOMDESC(&dptr[SDPCM_FRAMETAG_LEN])) {
  1106. brcmf_dbg(ERROR, "(superframe): got 2nd descriptor?\n");
  1107. errcode = -1;
  1108. } else if ((doff < SDPCM_HDRLEN) ||
  1109. (doff > (pfirst->len - SDPCM_HDRLEN))) {
  1110. brcmf_dbg(ERROR, "(superframe): Bad data offset %d: HW %d pkt %d min %d\n",
  1111. doff, sublen, pfirst->len, SDPCM_HDRLEN);
  1112. errcode = -1;
  1113. }
  1114. /* Check sequence number of superframe SW header */
  1115. if (rxseq != seq) {
  1116. brcmf_dbg(INFO, "(superframe) rx_seq %d, expected %d\n",
  1117. seq, rxseq);
  1118. bus->rx_badseq++;
  1119. rxseq = seq;
  1120. }
  1121. /* Check window for sanity */
  1122. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1123. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1124. txmax, bus->tx_seq);
  1125. txmax = bus->tx_seq + 2;
  1126. }
  1127. bus->tx_max = txmax;
  1128. /* Remove superframe header, remember offset */
  1129. skb_pull(pfirst, doff);
  1130. sfdoff = doff;
  1131. /* Validate all the subframe headers */
  1132. for (num = 0, pnext = pfirst; pnext && !errcode;
  1133. num++, pnext = pnext->next) {
  1134. dptr = (u8 *) (pnext->data);
  1135. dlen = (u16) (pnext->len);
  1136. sublen = get_unaligned_le16(dptr);
  1137. check = get_unaligned_le16(dptr + sizeof(u16));
  1138. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1139. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1140. #ifdef BCMDBG
  1141. if (BRCMF_GLOM_ON()) {
  1142. printk(KERN_DEBUG "subframe:\n");
  1143. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1144. dptr, 32);
  1145. }
  1146. #endif
  1147. if ((u16)~(sublen ^ check)) {
  1148. brcmf_dbg(ERROR, "(subframe %d): HW hdr error: len/check 0x%04x/0x%04x\n",
  1149. num, sublen, check);
  1150. errcode = -1;
  1151. } else if ((sublen > dlen) || (sublen < SDPCM_HDRLEN)) {
  1152. brcmf_dbg(ERROR, "(subframe %d): length mismatch: len 0x%04x, expect 0x%04x\n",
  1153. num, sublen, dlen);
  1154. errcode = -1;
  1155. } else if ((chan != SDPCM_DATA_CHANNEL) &&
  1156. (chan != SDPCM_EVENT_CHANNEL)) {
  1157. brcmf_dbg(ERROR, "(subframe %d): bad channel %d\n",
  1158. num, chan);
  1159. errcode = -1;
  1160. } else if ((doff < SDPCM_HDRLEN) || (doff > sublen)) {
  1161. brcmf_dbg(ERROR, "(subframe %d): Bad data offset %d: HW %d min %d\n",
  1162. num, doff, sublen, SDPCM_HDRLEN);
  1163. errcode = -1;
  1164. }
  1165. }
  1166. if (errcode) {
  1167. /* Terminate frame on error, request
  1168. a couple retries */
  1169. if (bus->glomerr++ < 3) {
  1170. /* Restore superframe header space */
  1171. skb_push(pfirst, sfdoff);
  1172. brcmf_sdbrcm_rxfail(bus, true, true);
  1173. } else {
  1174. bus->glomerr = 0;
  1175. brcmf_sdbrcm_rxfail(bus, true, false);
  1176. bus->rxglomfail++;
  1177. skb_queue_walk_safe(&bus->glom, pfirst, pnext) {
  1178. skb_unlink(pfirst, &bus->glom);
  1179. brcmu_pkt_buf_free_skb(pfirst);
  1180. }
  1181. }
  1182. bus->nextlen = 0;
  1183. return 0;
  1184. }
  1185. /* Basic SD framing looks ok - process each packet (header) */
  1186. save_pfirst = pfirst;
  1187. plast = NULL;
  1188. for (num = 0; pfirst; rxseq++, pfirst = pnext) {
  1189. pnext = pfirst->next;
  1190. pfirst->next = NULL;
  1191. dptr = (u8 *) (pfirst->data);
  1192. sublen = get_unaligned_le16(dptr);
  1193. chan = SDPCM_PACKET_CHANNEL(&dptr[SDPCM_FRAMETAG_LEN]);
  1194. seq = SDPCM_PACKET_SEQUENCE(&dptr[SDPCM_FRAMETAG_LEN]);
  1195. doff = SDPCM_DOFFSET_VALUE(&dptr[SDPCM_FRAMETAG_LEN]);
  1196. brcmf_dbg(GLOM, "Get subframe %d, %p(%p/%d), sublen %d chan %d seq %d\n",
  1197. num, pfirst, pfirst->data,
  1198. pfirst->len, sublen, chan, seq);
  1199. /* precondition: chan == SDPCM_DATA_CHANNEL ||
  1200. chan == SDPCM_EVENT_CHANNEL */
  1201. if (rxseq != seq) {
  1202. brcmf_dbg(GLOM, "rx_seq %d, expected %d\n",
  1203. seq, rxseq);
  1204. bus->rx_badseq++;
  1205. rxseq = seq;
  1206. }
  1207. #ifdef BCMDBG
  1208. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1209. printk(KERN_DEBUG "Rx Subframe Data:\n");
  1210. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1211. dptr, dlen);
  1212. }
  1213. #endif
  1214. __skb_trim(pfirst, sublen);
  1215. skb_pull(pfirst, doff);
  1216. if (pfirst->len == 0) {
  1217. brcmu_pkt_buf_free_skb(pfirst);
  1218. if (plast)
  1219. plast->next = pnext;
  1220. else
  1221. save_pfirst = pnext;
  1222. continue;
  1223. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx,
  1224. pfirst) != 0) {
  1225. brcmf_dbg(ERROR, "rx protocol error\n");
  1226. bus->drvr->rx_errors++;
  1227. brcmu_pkt_buf_free_skb(pfirst);
  1228. if (plast)
  1229. plast->next = pnext;
  1230. else
  1231. save_pfirst = pnext;
  1232. continue;
  1233. }
  1234. /* this packet will go up, link back into
  1235. chain and count it */
  1236. pfirst->next = pnext;
  1237. plast = pfirst;
  1238. num++;
  1239. #ifdef BCMDBG
  1240. if (BRCMF_GLOM_ON()) {
  1241. brcmf_dbg(GLOM, "subframe %d to stack, %p (%p/%d) nxt/lnk %p/%p\n",
  1242. num, pfirst, pfirst->data,
  1243. pfirst->len, pfirst->next,
  1244. pfirst->prev);
  1245. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1246. pfirst->data,
  1247. min_t(int, pfirst->len, 32));
  1248. }
  1249. #endif /* BCMDBG */
  1250. }
  1251. if (num) {
  1252. up(&bus->sdsem);
  1253. brcmf_rx_frame(bus->drvr, ifidx, save_pfirst, num);
  1254. down(&bus->sdsem);
  1255. }
  1256. bus->rxglomframes++;
  1257. bus->rxglompkts += num;
  1258. }
  1259. return num;
  1260. }
  1261. static int brcmf_sdbrcm_dcmd_resp_wait(struct brcmf_bus *bus, uint *condition,
  1262. bool *pending)
  1263. {
  1264. DECLARE_WAITQUEUE(wait, current);
  1265. int timeout = msecs_to_jiffies(DCMD_RESP_TIMEOUT);
  1266. /* Wait until control frame is available */
  1267. add_wait_queue(&bus->dcmd_resp_wait, &wait);
  1268. set_current_state(TASK_INTERRUPTIBLE);
  1269. while (!(*condition) && (!signal_pending(current) && timeout))
  1270. timeout = schedule_timeout(timeout);
  1271. if (signal_pending(current))
  1272. *pending = true;
  1273. set_current_state(TASK_RUNNING);
  1274. remove_wait_queue(&bus->dcmd_resp_wait, &wait);
  1275. return timeout;
  1276. }
  1277. static int brcmf_sdbrcm_dcmd_resp_wake(struct brcmf_bus *bus)
  1278. {
  1279. if (waitqueue_active(&bus->dcmd_resp_wait))
  1280. wake_up_interruptible(&bus->dcmd_resp_wait);
  1281. return 0;
  1282. }
  1283. static void
  1284. brcmf_sdbrcm_read_control(struct brcmf_bus *bus, u8 *hdr, uint len, uint doff)
  1285. {
  1286. uint rdlen, pad;
  1287. int sdret;
  1288. brcmf_dbg(TRACE, "Enter\n");
  1289. /* Set rxctl for frame (w/optional alignment) */
  1290. bus->rxctl = bus->rxbuf;
  1291. bus->rxctl += BRCMF_FIRSTREAD;
  1292. pad = ((unsigned long)bus->rxctl % BRCMF_SDALIGN);
  1293. if (pad)
  1294. bus->rxctl += (BRCMF_SDALIGN - pad);
  1295. bus->rxctl -= BRCMF_FIRSTREAD;
  1296. /* Copy the already-read portion over */
  1297. memcpy(bus->rxctl, hdr, BRCMF_FIRSTREAD);
  1298. if (len <= BRCMF_FIRSTREAD)
  1299. goto gotpkt;
  1300. /* Raise rdlen to next SDIO block to avoid tail command */
  1301. rdlen = len - BRCMF_FIRSTREAD;
  1302. if (bus->roundup && bus->blocksize && (rdlen > bus->blocksize)) {
  1303. pad = bus->blocksize - (rdlen % bus->blocksize);
  1304. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1305. ((len + pad) < bus->drvr->maxctl))
  1306. rdlen += pad;
  1307. } else if (rdlen % BRCMF_SDALIGN) {
  1308. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1309. }
  1310. /* Satisfy length-alignment requirements */
  1311. if (rdlen & (ALIGNMENT - 1))
  1312. rdlen = roundup(rdlen, ALIGNMENT);
  1313. /* Drop if the read is too big or it exceeds our maximum */
  1314. if ((rdlen + BRCMF_FIRSTREAD) > bus->drvr->maxctl) {
  1315. brcmf_dbg(ERROR, "%d-byte control read exceeds %d-byte buffer\n",
  1316. rdlen, bus->drvr->maxctl);
  1317. bus->drvr->rx_errors++;
  1318. brcmf_sdbrcm_rxfail(bus, false, false);
  1319. goto done;
  1320. }
  1321. if ((len - doff) > bus->drvr->maxctl) {
  1322. brcmf_dbg(ERROR, "%d-byte ctl frame (%d-byte ctl data) exceeds %d-byte limit\n",
  1323. len, len - doff, bus->drvr->maxctl);
  1324. bus->drvr->rx_errors++;
  1325. bus->rx_toolong++;
  1326. brcmf_sdbrcm_rxfail(bus, false, false);
  1327. goto done;
  1328. }
  1329. /* Read remainder of frame body into the rxctl buffer */
  1330. sdret = brcmf_sdcard_recv_buf(bus->sdiodev,
  1331. bus->sdiodev->sbwad,
  1332. SDIO_FUNC_2,
  1333. F2SYNC, (bus->rxctl + BRCMF_FIRSTREAD), rdlen,
  1334. NULL);
  1335. bus->f2rxdata++;
  1336. /* Control frame failures need retransmission */
  1337. if (sdret < 0) {
  1338. brcmf_dbg(ERROR, "read %d control bytes failed: %d\n",
  1339. rdlen, sdret);
  1340. bus->rxc_errors++;
  1341. brcmf_sdbrcm_rxfail(bus, true, true);
  1342. goto done;
  1343. }
  1344. gotpkt:
  1345. #ifdef BCMDBG
  1346. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  1347. printk(KERN_DEBUG "RxCtrl:\n");
  1348. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, bus->rxctl, len);
  1349. }
  1350. #endif
  1351. /* Point to valid data and indicate its length */
  1352. bus->rxctl += doff;
  1353. bus->rxlen = len - doff;
  1354. done:
  1355. /* Awake any waiters */
  1356. brcmf_sdbrcm_dcmd_resp_wake(bus);
  1357. }
  1358. /* Pad read to blocksize for efficiency */
  1359. static void brcmf_pad(struct brcmf_bus *bus, u16 *pad, u16 *rdlen)
  1360. {
  1361. if (bus->roundup && bus->blocksize && *rdlen > bus->blocksize) {
  1362. *pad = bus->blocksize - (*rdlen % bus->blocksize);
  1363. if (*pad <= bus->roundup && *pad < bus->blocksize &&
  1364. *rdlen + *pad + BRCMF_FIRSTREAD < MAX_RX_DATASZ)
  1365. *rdlen += *pad;
  1366. } else if (*rdlen % BRCMF_SDALIGN) {
  1367. *rdlen += BRCMF_SDALIGN - (*rdlen % BRCMF_SDALIGN);
  1368. }
  1369. }
  1370. static void
  1371. brcmf_alloc_pkt_and_read(struct brcmf_bus *bus, u16 rdlen,
  1372. struct sk_buff **pkt, u8 **rxbuf)
  1373. {
  1374. int sdret; /* Return code from calls */
  1375. *pkt = brcmu_pkt_buf_get_skb(rdlen + BRCMF_SDALIGN);
  1376. if (*pkt == NULL)
  1377. return;
  1378. pkt_align(*pkt, rdlen, BRCMF_SDALIGN);
  1379. *rxbuf = (u8 *) ((*pkt)->data);
  1380. /* Read the entire frame */
  1381. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1382. SDIO_FUNC_2, F2SYNC,
  1383. *rxbuf, rdlen, *pkt);
  1384. bus->f2rxdata++;
  1385. if (sdret < 0) {
  1386. brcmf_dbg(ERROR, "(nextlen): read %d bytes failed: %d\n",
  1387. rdlen, sdret);
  1388. brcmu_pkt_buf_free_skb(*pkt);
  1389. bus->drvr->rx_errors++;
  1390. /* Force retry w/normal header read.
  1391. * Don't attempt NAK for
  1392. * gSPI
  1393. */
  1394. brcmf_sdbrcm_rxfail(bus, true, true);
  1395. *pkt = NULL;
  1396. }
  1397. }
  1398. /* Checks the header */
  1399. static int
  1400. brcmf_check_rxbuf(struct brcmf_bus *bus, struct sk_buff *pkt, u8 *rxbuf,
  1401. u8 rxseq, u16 nextlen, u16 *len)
  1402. {
  1403. u16 check;
  1404. bool len_consistent; /* Result of comparing readahead len and
  1405. len from hw-hdr */
  1406. memcpy(bus->rxhdr, rxbuf, SDPCM_HDRLEN);
  1407. /* Extract hardware header fields */
  1408. *len = get_unaligned_le16(bus->rxhdr);
  1409. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1410. /* All zeros means readahead info was bad */
  1411. if (!(*len | check)) {
  1412. brcmf_dbg(INFO, "(nextlen): read zeros in HW header???\n");
  1413. goto fail;
  1414. }
  1415. /* Validate check bytes */
  1416. if ((u16)~(*len ^ check)) {
  1417. brcmf_dbg(ERROR, "(nextlen): HW hdr error: nextlen/len/check 0x%04x/0x%04x/0x%04x\n",
  1418. nextlen, *len, check);
  1419. bus->rx_badhdr++;
  1420. brcmf_sdbrcm_rxfail(bus, false, false);
  1421. goto fail;
  1422. }
  1423. /* Validate frame length */
  1424. if (*len < SDPCM_HDRLEN) {
  1425. brcmf_dbg(ERROR, "(nextlen): HW hdr length invalid: %d\n",
  1426. *len);
  1427. goto fail;
  1428. }
  1429. /* Check for consistency with readahead info */
  1430. len_consistent = (nextlen != (roundup(*len, 16) >> 4));
  1431. if (len_consistent) {
  1432. /* Mismatch, force retry w/normal
  1433. header (may be >4K) */
  1434. brcmf_dbg(ERROR, "(nextlen): mismatch, nextlen %d len %d rnd %d; expected rxseq %d\n",
  1435. nextlen, *len, roundup(*len, 16),
  1436. rxseq);
  1437. brcmf_sdbrcm_rxfail(bus, true, true);
  1438. goto fail;
  1439. }
  1440. return 0;
  1441. fail:
  1442. brcmf_sdbrcm_pktfree2(bus, pkt);
  1443. return -EINVAL;
  1444. }
  1445. /* Return true if there may be more frames to read */
  1446. static uint
  1447. brcmf_sdbrcm_readframes(struct brcmf_bus *bus, uint maxframes, bool *finished)
  1448. {
  1449. u16 len, check; /* Extracted hardware header fields */
  1450. u8 chan, seq, doff; /* Extracted software header fields */
  1451. u8 fcbits; /* Extracted fcbits from software header */
  1452. struct sk_buff *pkt; /* Packet for event or data frames */
  1453. u16 pad; /* Number of pad bytes to read */
  1454. u16 rdlen; /* Total number of bytes to read */
  1455. u8 rxseq; /* Next sequence number to expect */
  1456. uint rxleft = 0; /* Remaining number of frames allowed */
  1457. int sdret; /* Return code from calls */
  1458. u8 txmax; /* Maximum tx sequence offered */
  1459. u8 *rxbuf;
  1460. int ifidx = 0;
  1461. uint rxcount = 0; /* Total frames read */
  1462. brcmf_dbg(TRACE, "Enter\n");
  1463. /* Not finished unless we encounter no more frames indication */
  1464. *finished = false;
  1465. for (rxseq = bus->rx_seq, rxleft = maxframes;
  1466. !bus->rxskip && rxleft && bus->drvr->busstate != BRCMF_BUS_DOWN;
  1467. rxseq++, rxleft--) {
  1468. /* Handle glomming separately */
  1469. if (bus->glomd || !skb_queue_empty(&bus->glom)) {
  1470. u8 cnt;
  1471. brcmf_dbg(GLOM, "calling rxglom: glomd %p, glom %p\n",
  1472. bus->glomd, skb_peek(&bus->glom));
  1473. cnt = brcmf_sdbrcm_rxglom(bus, rxseq);
  1474. brcmf_dbg(GLOM, "rxglom returned %d\n", cnt);
  1475. rxseq += cnt - 1;
  1476. rxleft = (rxleft > cnt) ? (rxleft - cnt) : 1;
  1477. continue;
  1478. }
  1479. /* Try doing single read if we can */
  1480. if (bus->nextlen) {
  1481. u16 nextlen = bus->nextlen;
  1482. bus->nextlen = 0;
  1483. rdlen = len = nextlen << 4;
  1484. brcmf_pad(bus, &pad, &rdlen);
  1485. /*
  1486. * After the frame is received we have to
  1487. * distinguish whether it is data
  1488. * or non-data frame.
  1489. */
  1490. brcmf_alloc_pkt_and_read(bus, rdlen, &pkt, &rxbuf);
  1491. if (pkt == NULL) {
  1492. /* Give up on data, request rtx of events */
  1493. brcmf_dbg(ERROR, "(nextlen): brcmf_alloc_pkt_and_read failed: len %d rdlen %d expected rxseq %d\n",
  1494. len, rdlen, rxseq);
  1495. continue;
  1496. }
  1497. if (brcmf_check_rxbuf(bus, pkt, rxbuf, rxseq, nextlen,
  1498. &len) < 0)
  1499. continue;
  1500. /* Extract software header fields */
  1501. chan = SDPCM_PACKET_CHANNEL(
  1502. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1503. seq = SDPCM_PACKET_SEQUENCE(
  1504. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1505. doff = SDPCM_DOFFSET_VALUE(
  1506. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1507. txmax = SDPCM_WINDOW_VALUE(
  1508. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1509. bus->nextlen =
  1510. bus->rxhdr[SDPCM_FRAMETAG_LEN +
  1511. SDPCM_NEXTLEN_OFFSET];
  1512. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1513. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1514. bus->nextlen, seq);
  1515. bus->nextlen = 0;
  1516. }
  1517. bus->drvr->rx_readahead_cnt++;
  1518. /* Handle Flow Control */
  1519. fcbits = SDPCM_FCMASK_VALUE(
  1520. &bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1521. if (bus->flowcontrol != fcbits) {
  1522. if (~bus->flowcontrol & fcbits)
  1523. bus->fc_xoff++;
  1524. if (bus->flowcontrol & ~fcbits)
  1525. bus->fc_xon++;
  1526. bus->fc_rcvd++;
  1527. bus->flowcontrol = fcbits;
  1528. }
  1529. /* Check and update sequence number */
  1530. if (rxseq != seq) {
  1531. brcmf_dbg(INFO, "(nextlen): rx_seq %d, expected %d\n",
  1532. seq, rxseq);
  1533. bus->rx_badseq++;
  1534. rxseq = seq;
  1535. }
  1536. /* Check window for sanity */
  1537. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1538. brcmf_dbg(ERROR, "got unlikely tx max %d with tx_seq %d\n",
  1539. txmax, bus->tx_seq);
  1540. txmax = bus->tx_seq + 2;
  1541. }
  1542. bus->tx_max = txmax;
  1543. #ifdef BCMDBG
  1544. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1545. printk(KERN_DEBUG "Rx Data:\n");
  1546. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1547. rxbuf, len);
  1548. } else if (BRCMF_HDRS_ON()) {
  1549. printk(KERN_DEBUG "RxHdr:\n");
  1550. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1551. bus->rxhdr, SDPCM_HDRLEN);
  1552. }
  1553. #endif
  1554. if (chan == SDPCM_CONTROL_CHANNEL) {
  1555. brcmf_dbg(ERROR, "(nextlen): readahead on control packet %d?\n",
  1556. seq);
  1557. /* Force retry w/normal header read */
  1558. bus->nextlen = 0;
  1559. brcmf_sdbrcm_rxfail(bus, false, true);
  1560. brcmf_sdbrcm_pktfree2(bus, pkt);
  1561. continue;
  1562. }
  1563. /* Validate data offset */
  1564. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1565. brcmf_dbg(ERROR, "(nextlen): bad data offset %d: HW len %d min %d\n",
  1566. doff, len, SDPCM_HDRLEN);
  1567. brcmf_sdbrcm_rxfail(bus, false, false);
  1568. brcmf_sdbrcm_pktfree2(bus, pkt);
  1569. continue;
  1570. }
  1571. /* All done with this one -- now deliver the packet */
  1572. goto deliver;
  1573. }
  1574. /* Read frame header (hardware and software) */
  1575. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1576. SDIO_FUNC_2, F2SYNC, bus->rxhdr,
  1577. BRCMF_FIRSTREAD, NULL);
  1578. bus->f2rxhdrs++;
  1579. if (sdret < 0) {
  1580. brcmf_dbg(ERROR, "RXHEADER FAILED: %d\n", sdret);
  1581. bus->rx_hdrfail++;
  1582. brcmf_sdbrcm_rxfail(bus, true, true);
  1583. continue;
  1584. }
  1585. #ifdef BCMDBG
  1586. if (BRCMF_BYTES_ON() || BRCMF_HDRS_ON()) {
  1587. printk(KERN_DEBUG "RxHdr:\n");
  1588. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1589. bus->rxhdr, SDPCM_HDRLEN);
  1590. }
  1591. #endif
  1592. /* Extract hardware header fields */
  1593. len = get_unaligned_le16(bus->rxhdr);
  1594. check = get_unaligned_le16(bus->rxhdr + sizeof(u16));
  1595. /* All zeros means no more frames */
  1596. if (!(len | check)) {
  1597. *finished = true;
  1598. break;
  1599. }
  1600. /* Validate check bytes */
  1601. if ((u16) ~(len ^ check)) {
  1602. brcmf_dbg(ERROR, "HW hdr err: len/check 0x%04x/0x%04x\n",
  1603. len, check);
  1604. bus->rx_badhdr++;
  1605. brcmf_sdbrcm_rxfail(bus, false, false);
  1606. continue;
  1607. }
  1608. /* Validate frame length */
  1609. if (len < SDPCM_HDRLEN) {
  1610. brcmf_dbg(ERROR, "HW hdr length invalid: %d\n", len);
  1611. continue;
  1612. }
  1613. /* Extract software header fields */
  1614. chan = SDPCM_PACKET_CHANNEL(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1615. seq = SDPCM_PACKET_SEQUENCE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1616. doff = SDPCM_DOFFSET_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1617. txmax = SDPCM_WINDOW_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1618. /* Validate data offset */
  1619. if ((doff < SDPCM_HDRLEN) || (doff > len)) {
  1620. brcmf_dbg(ERROR, "Bad data offset %d: HW len %d, min %d seq %d\n",
  1621. doff, len, SDPCM_HDRLEN, seq);
  1622. bus->rx_badhdr++;
  1623. brcmf_sdbrcm_rxfail(bus, false, false);
  1624. continue;
  1625. }
  1626. /* Save the readahead length if there is one */
  1627. bus->nextlen =
  1628. bus->rxhdr[SDPCM_FRAMETAG_LEN + SDPCM_NEXTLEN_OFFSET];
  1629. if ((bus->nextlen << 4) > MAX_RX_DATASZ) {
  1630. brcmf_dbg(INFO, "(nextlen): got frame w/nextlen too large (%d), seq %d\n",
  1631. bus->nextlen, seq);
  1632. bus->nextlen = 0;
  1633. }
  1634. /* Handle Flow Control */
  1635. fcbits = SDPCM_FCMASK_VALUE(&bus->rxhdr[SDPCM_FRAMETAG_LEN]);
  1636. if (bus->flowcontrol != fcbits) {
  1637. if (~bus->flowcontrol & fcbits)
  1638. bus->fc_xoff++;
  1639. if (bus->flowcontrol & ~fcbits)
  1640. bus->fc_xon++;
  1641. bus->fc_rcvd++;
  1642. bus->flowcontrol = fcbits;
  1643. }
  1644. /* Check and update sequence number */
  1645. if (rxseq != seq) {
  1646. brcmf_dbg(INFO, "rx_seq %d, expected %d\n", seq, rxseq);
  1647. bus->rx_badseq++;
  1648. rxseq = seq;
  1649. }
  1650. /* Check window for sanity */
  1651. if ((u8) (txmax - bus->tx_seq) > 0x40) {
  1652. brcmf_dbg(ERROR, "unlikely tx max %d with tx_seq %d\n",
  1653. txmax, bus->tx_seq);
  1654. txmax = bus->tx_seq + 2;
  1655. }
  1656. bus->tx_max = txmax;
  1657. /* Call a separate function for control frames */
  1658. if (chan == SDPCM_CONTROL_CHANNEL) {
  1659. brcmf_sdbrcm_read_control(bus, bus->rxhdr, len, doff);
  1660. continue;
  1661. }
  1662. /* precondition: chan is either SDPCM_DATA_CHANNEL,
  1663. SDPCM_EVENT_CHANNEL, SDPCM_TEST_CHANNEL or
  1664. SDPCM_GLOM_CHANNEL */
  1665. /* Length to read */
  1666. rdlen = (len > BRCMF_FIRSTREAD) ? (len - BRCMF_FIRSTREAD) : 0;
  1667. /* May pad read to blocksize for efficiency */
  1668. if (bus->roundup && bus->blocksize &&
  1669. (rdlen > bus->blocksize)) {
  1670. pad = bus->blocksize - (rdlen % bus->blocksize);
  1671. if ((pad <= bus->roundup) && (pad < bus->blocksize) &&
  1672. ((rdlen + pad + BRCMF_FIRSTREAD) < MAX_RX_DATASZ))
  1673. rdlen += pad;
  1674. } else if (rdlen % BRCMF_SDALIGN) {
  1675. rdlen += BRCMF_SDALIGN - (rdlen % BRCMF_SDALIGN);
  1676. }
  1677. /* Satisfy length-alignment requirements */
  1678. if (rdlen & (ALIGNMENT - 1))
  1679. rdlen = roundup(rdlen, ALIGNMENT);
  1680. if ((rdlen + BRCMF_FIRSTREAD) > MAX_RX_DATASZ) {
  1681. /* Too long -- skip this frame */
  1682. brcmf_dbg(ERROR, "too long: len %d rdlen %d\n",
  1683. len, rdlen);
  1684. bus->drvr->rx_errors++;
  1685. bus->rx_toolong++;
  1686. brcmf_sdbrcm_rxfail(bus, false, false);
  1687. continue;
  1688. }
  1689. pkt = brcmu_pkt_buf_get_skb(rdlen +
  1690. BRCMF_FIRSTREAD + BRCMF_SDALIGN);
  1691. if (!pkt) {
  1692. /* Give up on data, request rtx of events */
  1693. brcmf_dbg(ERROR, "brcmu_pkt_buf_get_skb failed: rdlen %d chan %d\n",
  1694. rdlen, chan);
  1695. bus->drvr->rx_dropped++;
  1696. brcmf_sdbrcm_rxfail(bus, false, RETRYCHAN(chan));
  1697. continue;
  1698. }
  1699. /* Leave room for what we already read, and align remainder */
  1700. skb_pull(pkt, BRCMF_FIRSTREAD);
  1701. pkt_align(pkt, rdlen, BRCMF_SDALIGN);
  1702. /* Read the remaining frame data */
  1703. sdret = brcmf_sdcard_recv_buf(bus->sdiodev, bus->sdiodev->sbwad,
  1704. SDIO_FUNC_2, F2SYNC, ((u8 *) (pkt->data)),
  1705. rdlen, pkt);
  1706. bus->f2rxdata++;
  1707. if (sdret < 0) {
  1708. brcmf_dbg(ERROR, "read %d %s bytes failed: %d\n", rdlen,
  1709. ((chan == SDPCM_EVENT_CHANNEL) ? "event"
  1710. : ((chan == SDPCM_DATA_CHANNEL) ? "data"
  1711. : "test")), sdret);
  1712. brcmu_pkt_buf_free_skb(pkt);
  1713. bus->drvr->rx_errors++;
  1714. brcmf_sdbrcm_rxfail(bus, true, RETRYCHAN(chan));
  1715. continue;
  1716. }
  1717. /* Copy the already-read portion */
  1718. skb_push(pkt, BRCMF_FIRSTREAD);
  1719. memcpy(pkt->data, bus->rxhdr, BRCMF_FIRSTREAD);
  1720. #ifdef BCMDBG
  1721. if (BRCMF_BYTES_ON() && BRCMF_DATA_ON()) {
  1722. printk(KERN_DEBUG "Rx Data:\n");
  1723. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1724. pkt->data, len);
  1725. }
  1726. #endif
  1727. deliver:
  1728. /* Save superframe descriptor and allocate packet frame */
  1729. if (chan == SDPCM_GLOM_CHANNEL) {
  1730. if (SDPCM_GLOMDESC(&bus->rxhdr[SDPCM_FRAMETAG_LEN])) {
  1731. brcmf_dbg(GLOM, "glom descriptor, %d bytes:\n",
  1732. len);
  1733. #ifdef BCMDBG
  1734. if (BRCMF_GLOM_ON()) {
  1735. printk(KERN_DEBUG "Glom Data:\n");
  1736. print_hex_dump_bytes("",
  1737. DUMP_PREFIX_OFFSET,
  1738. pkt->data, len);
  1739. }
  1740. #endif
  1741. __skb_trim(pkt, len);
  1742. skb_pull(pkt, SDPCM_HDRLEN);
  1743. bus->glomd = pkt;
  1744. } else {
  1745. brcmf_dbg(ERROR, "%s: glom superframe w/o "
  1746. "descriptor!\n", __func__);
  1747. brcmf_sdbrcm_rxfail(bus, false, false);
  1748. }
  1749. continue;
  1750. }
  1751. /* Fill in packet len and prio, deliver upward */
  1752. __skb_trim(pkt, len);
  1753. skb_pull(pkt, doff);
  1754. if (pkt->len == 0) {
  1755. brcmu_pkt_buf_free_skb(pkt);
  1756. continue;
  1757. } else if (brcmf_proto_hdrpull(bus->drvr, &ifidx, pkt) != 0) {
  1758. brcmf_dbg(ERROR, "rx protocol error\n");
  1759. brcmu_pkt_buf_free_skb(pkt);
  1760. bus->drvr->rx_errors++;
  1761. continue;
  1762. }
  1763. /* Unlock during rx call */
  1764. up(&bus->sdsem);
  1765. brcmf_rx_frame(bus->drvr, ifidx, pkt, 1);
  1766. down(&bus->sdsem);
  1767. }
  1768. rxcount = maxframes - rxleft;
  1769. #ifdef BCMDBG
  1770. /* Message if we hit the limit */
  1771. if (!rxleft)
  1772. brcmf_dbg(DATA, "hit rx limit of %d frames\n",
  1773. maxframes);
  1774. else
  1775. #endif /* BCMDBG */
  1776. brcmf_dbg(DATA, "processed %d frames\n", rxcount);
  1777. /* Back off rxseq if awaiting rtx, update rx_seq */
  1778. if (bus->rxskip)
  1779. rxseq--;
  1780. bus->rx_seq = rxseq;
  1781. return rxcount;
  1782. }
  1783. static int
  1784. brcmf_sdbrcm_send_buf(struct brcmf_bus *bus, u32 addr, uint fn, uint flags,
  1785. u8 *buf, uint nbytes, struct sk_buff *pkt)
  1786. {
  1787. return brcmf_sdcard_send_buf
  1788. (bus->sdiodev, addr, fn, flags, buf, nbytes, pkt);
  1789. }
  1790. static void
  1791. brcmf_sdbrcm_wait_for_event(struct brcmf_bus *bus, bool *lockvar)
  1792. {
  1793. up(&bus->sdsem);
  1794. wait_event_interruptible_timeout(bus->ctrl_wait,
  1795. (*lockvar == false), HZ * 2);
  1796. down(&bus->sdsem);
  1797. return;
  1798. }
  1799. static void
  1800. brcmf_sdbrcm_wait_event_wakeup(struct brcmf_bus *bus)
  1801. {
  1802. if (waitqueue_active(&bus->ctrl_wait))
  1803. wake_up_interruptible(&bus->ctrl_wait);
  1804. return;
  1805. }
  1806. /* Writes a HW/SW header into the packet and sends it. */
  1807. /* Assumes: (a) header space already there, (b) caller holds lock */
  1808. static int brcmf_sdbrcm_txpkt(struct brcmf_bus *bus, struct sk_buff *pkt,
  1809. uint chan, bool free_pkt)
  1810. {
  1811. int ret;
  1812. u8 *frame;
  1813. u16 len, pad = 0;
  1814. u32 swheader;
  1815. struct sk_buff *new;
  1816. int i;
  1817. brcmf_dbg(TRACE, "Enter\n");
  1818. frame = (u8 *) (pkt->data);
  1819. /* Add alignment padding, allocate new packet if needed */
  1820. pad = ((unsigned long)frame % BRCMF_SDALIGN);
  1821. if (pad) {
  1822. if (skb_headroom(pkt) < pad) {
  1823. brcmf_dbg(INFO, "insufficient headroom %d for %d pad\n",
  1824. skb_headroom(pkt), pad);
  1825. bus->drvr->tx_realloc++;
  1826. new = brcmu_pkt_buf_get_skb(pkt->len + BRCMF_SDALIGN);
  1827. if (!new) {
  1828. brcmf_dbg(ERROR, "couldn't allocate new %d-byte packet\n",
  1829. pkt->len + BRCMF_SDALIGN);
  1830. ret = -ENOMEM;
  1831. goto done;
  1832. }
  1833. pkt_align(new, pkt->len, BRCMF_SDALIGN);
  1834. memcpy(new->data, pkt->data, pkt->len);
  1835. if (free_pkt)
  1836. brcmu_pkt_buf_free_skb(pkt);
  1837. /* free the pkt if canned one is not used */
  1838. free_pkt = true;
  1839. pkt = new;
  1840. frame = (u8 *) (pkt->data);
  1841. /* precondition: (frame % BRCMF_SDALIGN) == 0) */
  1842. pad = 0;
  1843. } else {
  1844. skb_push(pkt, pad);
  1845. frame = (u8 *) (pkt->data);
  1846. /* precondition: pad + SDPCM_HDRLEN <= pkt->len */
  1847. memset(frame, 0, pad + SDPCM_HDRLEN);
  1848. }
  1849. }
  1850. /* precondition: pad < BRCMF_SDALIGN */
  1851. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  1852. len = (u16) (pkt->len);
  1853. *(__le16 *) frame = cpu_to_le16(len);
  1854. *(((__le16 *) frame) + 1) = cpu_to_le16(~len);
  1855. /* Software tag: channel, sequence number, data offset */
  1856. swheader =
  1857. ((chan << SDPCM_CHANNEL_SHIFT) & SDPCM_CHANNEL_MASK) | bus->tx_seq |
  1858. (((pad +
  1859. SDPCM_HDRLEN) << SDPCM_DOFFSET_SHIFT) & SDPCM_DOFFSET_MASK);
  1860. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  1861. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  1862. #ifdef BCMDBG
  1863. tx_packets[pkt->priority]++;
  1864. if (BRCMF_BYTES_ON() &&
  1865. (((BRCMF_CTL_ON() && (chan == SDPCM_CONTROL_CHANNEL)) ||
  1866. (BRCMF_DATA_ON() && (chan != SDPCM_CONTROL_CHANNEL))))) {
  1867. printk(KERN_DEBUG "Tx Frame:\n");
  1868. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET, frame, len);
  1869. } else if (BRCMF_HDRS_ON()) {
  1870. printk(KERN_DEBUG "TxHdr:\n");
  1871. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  1872. frame, min_t(u16, len, 16));
  1873. }
  1874. #endif
  1875. /* Raise len to next SDIO block to eliminate tail command */
  1876. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  1877. u16 pad = bus->blocksize - (len % bus->blocksize);
  1878. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  1879. len += pad;
  1880. } else if (len % BRCMF_SDALIGN) {
  1881. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  1882. }
  1883. /* Some controllers have trouble with odd bytes -- round to even */
  1884. if (len & (ALIGNMENT - 1))
  1885. len = roundup(len, ALIGNMENT);
  1886. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  1887. SDIO_FUNC_2, F2SYNC, frame,
  1888. len, pkt);
  1889. bus->f2txdata++;
  1890. if (ret < 0) {
  1891. /* On failure, abort the command and terminate the frame */
  1892. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  1893. ret);
  1894. bus->tx_sderrs++;
  1895. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  1896. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  1897. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  1898. NULL);
  1899. bus->f1regdata++;
  1900. for (i = 0; i < 3; i++) {
  1901. u8 hi, lo;
  1902. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  1903. SDIO_FUNC_1,
  1904. SBSDIO_FUNC1_WFRAMEBCHI,
  1905. NULL);
  1906. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  1907. SDIO_FUNC_1,
  1908. SBSDIO_FUNC1_WFRAMEBCLO,
  1909. NULL);
  1910. bus->f1regdata += 2;
  1911. if ((hi == 0) && (lo == 0))
  1912. break;
  1913. }
  1914. }
  1915. if (ret == 0)
  1916. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  1917. done:
  1918. /* restore pkt buffer pointer before calling tx complete routine */
  1919. skb_pull(pkt, SDPCM_HDRLEN + pad);
  1920. up(&bus->sdsem);
  1921. brcmf_txcomplete(bus->drvr, pkt, ret != 0);
  1922. down(&bus->sdsem);
  1923. if (free_pkt)
  1924. brcmu_pkt_buf_free_skb(pkt);
  1925. return ret;
  1926. }
  1927. static uint brcmf_sdbrcm_sendfromq(struct brcmf_bus *bus, uint maxframes)
  1928. {
  1929. struct sk_buff *pkt;
  1930. u32 intstatus = 0;
  1931. uint retries = 0;
  1932. int ret = 0, prec_out;
  1933. uint cnt = 0;
  1934. uint datalen;
  1935. u8 tx_prec_map;
  1936. struct brcmf_pub *drvr = bus->drvr;
  1937. brcmf_dbg(TRACE, "Enter\n");
  1938. tx_prec_map = ~bus->flowcontrol;
  1939. /* Send frames until the limit or some other event */
  1940. for (cnt = 0; (cnt < maxframes) && data_ok(bus); cnt++) {
  1941. spin_lock_bh(&bus->txqlock);
  1942. pkt = brcmu_pktq_mdeq(&bus->txq, tx_prec_map, &prec_out);
  1943. if (pkt == NULL) {
  1944. spin_unlock_bh(&bus->txqlock);
  1945. break;
  1946. }
  1947. spin_unlock_bh(&bus->txqlock);
  1948. datalen = pkt->len - SDPCM_HDRLEN;
  1949. ret = brcmf_sdbrcm_txpkt(bus, pkt, SDPCM_DATA_CHANNEL, true);
  1950. if (ret)
  1951. bus->drvr->tx_errors++;
  1952. else
  1953. bus->drvr->dstats.tx_bytes += datalen;
  1954. /* In poll mode, need to check for other events */
  1955. if (!bus->intr && cnt) {
  1956. /* Check device status, signal pending interrupt */
  1957. r_sdreg32(bus, &intstatus,
  1958. offsetof(struct sdpcmd_regs, intstatus),
  1959. &retries);
  1960. bus->f2txdata++;
  1961. if (brcmf_sdcard_regfail(bus->sdiodev))
  1962. break;
  1963. if (intstatus & bus->hostintmask)
  1964. bus->ipend = true;
  1965. }
  1966. }
  1967. /* Deflow-control stack if needed */
  1968. if (drvr->up && (drvr->busstate == BRCMF_BUS_DATA) &&
  1969. drvr->txoff && (pktq_len(&bus->txq) < TXLOW))
  1970. brcmf_txflowcontrol(drvr, 0, OFF);
  1971. return cnt;
  1972. }
  1973. static bool brcmf_sdbrcm_dpc(struct brcmf_bus *bus)
  1974. {
  1975. u32 intstatus, newstatus = 0;
  1976. uint retries = 0;
  1977. uint rxlimit = bus->rxbound; /* Rx frames to read before resched */
  1978. uint txlimit = bus->txbound; /* Tx frames to send before resched */
  1979. uint framecnt = 0; /* Temporary counter of tx/rx frames */
  1980. bool rxdone = true; /* Flag for no more read data */
  1981. bool resched = false; /* Flag indicating resched wanted */
  1982. brcmf_dbg(TRACE, "Enter\n");
  1983. /* Start with leftover status bits */
  1984. intstatus = bus->intstatus;
  1985. down(&bus->sdsem);
  1986. /* If waiting for HTAVAIL, check status */
  1987. if (bus->clkstate == CLK_PENDING) {
  1988. int err;
  1989. u8 clkctl, devctl = 0;
  1990. #ifdef BCMDBG
  1991. /* Check for inconsistent device control */
  1992. devctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  1993. SBSDIO_DEVICE_CTL, &err);
  1994. if (err) {
  1995. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n", err);
  1996. bus->drvr->busstate = BRCMF_BUS_DOWN;
  1997. }
  1998. #endif /* BCMDBG */
  1999. /* Read CSR, if clock on switch to AVAIL, else ignore */
  2000. clkctl = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2001. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2002. if (err) {
  2003. brcmf_dbg(ERROR, "error reading CSR: %d\n",
  2004. err);
  2005. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2006. }
  2007. brcmf_dbg(INFO, "DPC: PENDING, devctl 0x%02x clkctl 0x%02x\n",
  2008. devctl, clkctl);
  2009. if (SBSDIO_HTAV(clkctl)) {
  2010. devctl = brcmf_sdcard_cfg_read(bus->sdiodev,
  2011. SDIO_FUNC_1,
  2012. SBSDIO_DEVICE_CTL, &err);
  2013. if (err) {
  2014. brcmf_dbg(ERROR, "error reading DEVCTL: %d\n",
  2015. err);
  2016. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2017. }
  2018. devctl &= ~SBSDIO_DEVCTL_CA_INT_ONLY;
  2019. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2020. SBSDIO_DEVICE_CTL, devctl, &err);
  2021. if (err) {
  2022. brcmf_dbg(ERROR, "error writing DEVCTL: %d\n",
  2023. err);
  2024. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2025. }
  2026. bus->clkstate = CLK_AVAIL;
  2027. } else {
  2028. goto clkwait;
  2029. }
  2030. }
  2031. bus_wake(bus);
  2032. /* Make sure backplane clock is on */
  2033. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, true);
  2034. if (bus->clkstate == CLK_PENDING)
  2035. goto clkwait;
  2036. /* Pending interrupt indicates new device status */
  2037. if (bus->ipend) {
  2038. bus->ipend = false;
  2039. r_sdreg32(bus, &newstatus,
  2040. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2041. bus->f1regdata++;
  2042. if (brcmf_sdcard_regfail(bus->sdiodev))
  2043. newstatus = 0;
  2044. newstatus &= bus->hostintmask;
  2045. bus->fcstate = !!(newstatus & I_HMB_FC_STATE);
  2046. if (newstatus) {
  2047. w_sdreg32(bus, newstatus,
  2048. offsetof(struct sdpcmd_regs, intstatus),
  2049. &retries);
  2050. bus->f1regdata++;
  2051. }
  2052. }
  2053. /* Merge new bits with previous */
  2054. intstatus |= newstatus;
  2055. bus->intstatus = 0;
  2056. /* Handle flow-control change: read new state in case our ack
  2057. * crossed another change interrupt. If change still set, assume
  2058. * FC ON for safety, let next loop through do the debounce.
  2059. */
  2060. if (intstatus & I_HMB_FC_CHANGE) {
  2061. intstatus &= ~I_HMB_FC_CHANGE;
  2062. w_sdreg32(bus, I_HMB_FC_CHANGE,
  2063. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2064. r_sdreg32(bus, &newstatus,
  2065. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2066. bus->f1regdata += 2;
  2067. bus->fcstate =
  2068. !!(newstatus & (I_HMB_FC_STATE | I_HMB_FC_CHANGE));
  2069. intstatus |= (newstatus & bus->hostintmask);
  2070. }
  2071. /* Handle host mailbox indication */
  2072. if (intstatus & I_HMB_HOST_INT) {
  2073. intstatus &= ~I_HMB_HOST_INT;
  2074. intstatus |= brcmf_sdbrcm_hostmail(bus);
  2075. }
  2076. /* Generally don't ask for these, can get CRC errors... */
  2077. if (intstatus & I_WR_OOSYNC) {
  2078. brcmf_dbg(ERROR, "Dongle reports WR_OOSYNC\n");
  2079. intstatus &= ~I_WR_OOSYNC;
  2080. }
  2081. if (intstatus & I_RD_OOSYNC) {
  2082. brcmf_dbg(ERROR, "Dongle reports RD_OOSYNC\n");
  2083. intstatus &= ~I_RD_OOSYNC;
  2084. }
  2085. if (intstatus & I_SBINT) {
  2086. brcmf_dbg(ERROR, "Dongle reports SBINT\n");
  2087. intstatus &= ~I_SBINT;
  2088. }
  2089. /* Would be active due to wake-wlan in gSPI */
  2090. if (intstatus & I_CHIPACTIVE) {
  2091. brcmf_dbg(INFO, "Dongle reports CHIPACTIVE\n");
  2092. intstatus &= ~I_CHIPACTIVE;
  2093. }
  2094. /* Ignore frame indications if rxskip is set */
  2095. if (bus->rxskip)
  2096. intstatus &= ~I_HMB_FRAME_IND;
  2097. /* On frame indication, read available frames */
  2098. if (PKT_AVAILABLE()) {
  2099. framecnt = brcmf_sdbrcm_readframes(bus, rxlimit, &rxdone);
  2100. if (rxdone || bus->rxskip)
  2101. intstatus &= ~I_HMB_FRAME_IND;
  2102. rxlimit -= min(framecnt, rxlimit);
  2103. }
  2104. /* Keep still-pending events for next scheduling */
  2105. bus->intstatus = intstatus;
  2106. clkwait:
  2107. if (data_ok(bus) && bus->ctrl_frame_stat &&
  2108. (bus->clkstate == CLK_AVAIL)) {
  2109. int ret, i;
  2110. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  2111. SDIO_FUNC_2, F2SYNC, (u8 *) bus->ctrl_frame_buf,
  2112. (u32) bus->ctrl_frame_len, NULL);
  2113. if (ret < 0) {
  2114. /* On failure, abort the command and
  2115. terminate the frame */
  2116. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2117. ret);
  2118. bus->tx_sderrs++;
  2119. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2120. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2121. SBSDIO_FUNC1_FRAMECTRL, SFC_WF_TERM,
  2122. NULL);
  2123. bus->f1regdata++;
  2124. for (i = 0; i < 3; i++) {
  2125. u8 hi, lo;
  2126. hi = brcmf_sdcard_cfg_read(bus->sdiodev,
  2127. SDIO_FUNC_1,
  2128. SBSDIO_FUNC1_WFRAMEBCHI,
  2129. NULL);
  2130. lo = brcmf_sdcard_cfg_read(bus->sdiodev,
  2131. SDIO_FUNC_1,
  2132. SBSDIO_FUNC1_WFRAMEBCLO,
  2133. NULL);
  2134. bus->f1regdata += 2;
  2135. if ((hi == 0) && (lo == 0))
  2136. break;
  2137. }
  2138. }
  2139. if (ret == 0)
  2140. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2141. brcmf_dbg(INFO, "Return_dpc value is : %d\n", ret);
  2142. bus->ctrl_frame_stat = false;
  2143. brcmf_sdbrcm_wait_event_wakeup(bus);
  2144. }
  2145. /* Send queued frames (limit 1 if rx may still be pending) */
  2146. else if ((bus->clkstate == CLK_AVAIL) && !bus->fcstate &&
  2147. brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol) && txlimit
  2148. && data_ok(bus)) {
  2149. framecnt = rxdone ? txlimit : min(txlimit, bus->txminmax);
  2150. framecnt = brcmf_sdbrcm_sendfromq(bus, framecnt);
  2151. txlimit -= framecnt;
  2152. }
  2153. /* Resched if events or tx frames are pending,
  2154. else await next interrupt */
  2155. /* On failed register access, all bets are off:
  2156. no resched or interrupts */
  2157. if ((bus->drvr->busstate == BRCMF_BUS_DOWN) ||
  2158. brcmf_sdcard_regfail(bus->sdiodev)) {
  2159. brcmf_dbg(ERROR, "failed backplane access over SDIO, halting operation %d\n",
  2160. brcmf_sdcard_regfail(bus->sdiodev));
  2161. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2162. bus->intstatus = 0;
  2163. } else if (bus->clkstate == CLK_PENDING) {
  2164. brcmf_dbg(INFO, "rescheduled due to CLK_PENDING awaiting I_CHIPACTIVE interrupt\n");
  2165. resched = true;
  2166. } else if (bus->intstatus || bus->ipend ||
  2167. (!bus->fcstate && brcmu_pktq_mlen(&bus->txq, ~bus->flowcontrol)
  2168. && data_ok(bus)) || PKT_AVAILABLE()) {
  2169. resched = true;
  2170. }
  2171. bus->dpc_sched = resched;
  2172. /* If we're done for now, turn off clock request. */
  2173. if ((bus->clkstate != CLK_PENDING)
  2174. && bus->idletime == BRCMF_IDLE_IMMEDIATE) {
  2175. bus->activity = false;
  2176. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2177. }
  2178. up(&bus->sdsem);
  2179. return resched;
  2180. }
  2181. static int brcmf_sdbrcm_dpc_thread(void *data)
  2182. {
  2183. struct brcmf_bus *bus = (struct brcmf_bus *) data;
  2184. allow_signal(SIGTERM);
  2185. /* Run until signal received */
  2186. while (1) {
  2187. if (kthread_should_stop())
  2188. break;
  2189. if (!wait_for_completion_interruptible(&bus->dpc_wait)) {
  2190. /* Call bus dpc unless it indicated down
  2191. (then clean stop) */
  2192. if (bus->drvr->busstate != BRCMF_BUS_DOWN) {
  2193. if (brcmf_sdbrcm_dpc(bus))
  2194. complete(&bus->dpc_wait);
  2195. } else {
  2196. /* after stopping the bus, exit thread */
  2197. brcmf_sdbrcm_bus_stop(bus);
  2198. bus->dpc_tsk = NULL;
  2199. break;
  2200. }
  2201. } else
  2202. break;
  2203. }
  2204. return 0;
  2205. }
  2206. int brcmf_sdbrcm_bus_txdata(struct brcmf_bus *bus, struct sk_buff *pkt)
  2207. {
  2208. int ret = -EBADE;
  2209. uint datalen, prec;
  2210. brcmf_dbg(TRACE, "Enter\n");
  2211. datalen = pkt->len;
  2212. /* Add space for the header */
  2213. skb_push(pkt, SDPCM_HDRLEN);
  2214. /* precondition: IS_ALIGNED((unsigned long)(pkt->data), 2) */
  2215. prec = prio2prec((pkt->priority & PRIOMASK));
  2216. /* Check for existing queue, current flow-control,
  2217. pending event, or pending clock */
  2218. brcmf_dbg(TRACE, "deferring pktq len %d\n", pktq_len(&bus->txq));
  2219. bus->fcqueued++;
  2220. /* Priority based enq */
  2221. spin_lock_bh(&bus->txqlock);
  2222. if (brcmf_c_prec_enq(bus->drvr, &bus->txq, pkt, prec) == false) {
  2223. skb_pull(pkt, SDPCM_HDRLEN);
  2224. brcmf_txcomplete(bus->drvr, pkt, false);
  2225. brcmu_pkt_buf_free_skb(pkt);
  2226. brcmf_dbg(ERROR, "out of bus->txq !!!\n");
  2227. ret = -ENOSR;
  2228. } else {
  2229. ret = 0;
  2230. }
  2231. spin_unlock_bh(&bus->txqlock);
  2232. if (pktq_len(&bus->txq) >= TXHI)
  2233. brcmf_txflowcontrol(bus->drvr, 0, ON);
  2234. #ifdef BCMDBG
  2235. if (pktq_plen(&bus->txq, prec) > qcount[prec])
  2236. qcount[prec] = pktq_plen(&bus->txq, prec);
  2237. #endif
  2238. /* Schedule DPC if needed to send queued packet(s) */
  2239. if (!bus->dpc_sched) {
  2240. bus->dpc_sched = true;
  2241. if (bus->dpc_tsk)
  2242. complete(&bus->dpc_wait);
  2243. }
  2244. return ret;
  2245. }
  2246. static int
  2247. brcmf_sdbrcm_membytes(struct brcmf_bus *bus, bool write, u32 address, u8 *data,
  2248. uint size)
  2249. {
  2250. int bcmerror = 0;
  2251. u32 sdaddr;
  2252. uint dsize;
  2253. /* Determine initial transfer parameters */
  2254. sdaddr = address & SBSDIO_SB_OFT_ADDR_MASK;
  2255. if ((sdaddr + size) & SBSDIO_SBWINDOW_MASK)
  2256. dsize = (SBSDIO_SB_OFT_ADDR_LIMIT - sdaddr);
  2257. else
  2258. dsize = size;
  2259. /* Set the backplane window to include the start address */
  2260. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev, address);
  2261. if (bcmerror) {
  2262. brcmf_dbg(ERROR, "window change failed\n");
  2263. goto xfer_done;
  2264. }
  2265. /* Do the transfer(s) */
  2266. while (size) {
  2267. brcmf_dbg(INFO, "%s %d bytes at offset 0x%08x in window 0x%08x\n",
  2268. write ? "write" : "read", dsize,
  2269. sdaddr, address & SBSDIO_SBWINDOW_MASK);
  2270. bcmerror = brcmf_sdcard_rwdata(bus->sdiodev, write,
  2271. sdaddr, data, dsize);
  2272. if (bcmerror) {
  2273. brcmf_dbg(ERROR, "membytes transfer failed\n");
  2274. break;
  2275. }
  2276. /* Adjust for next transfer (if any) */
  2277. size -= dsize;
  2278. if (size) {
  2279. data += dsize;
  2280. address += dsize;
  2281. bcmerror = brcmf_sdcard_set_sbaddr_window(bus->sdiodev,
  2282. address);
  2283. if (bcmerror) {
  2284. brcmf_dbg(ERROR, "window change failed\n");
  2285. break;
  2286. }
  2287. sdaddr = 0;
  2288. dsize = min_t(uint, SBSDIO_SB_OFT_ADDR_LIMIT, size);
  2289. }
  2290. }
  2291. xfer_done:
  2292. /* Return the window to backplane enumeration space for core access */
  2293. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, bus->sdiodev->sbwad))
  2294. brcmf_dbg(ERROR, "FAILED to set window back to 0x%x\n",
  2295. bus->sdiodev->sbwad);
  2296. return bcmerror;
  2297. }
  2298. #ifdef BCMDBG
  2299. #define CONSOLE_LINE_MAX 192
  2300. static int brcmf_sdbrcm_readconsole(struct brcmf_bus *bus)
  2301. {
  2302. struct brcmf_console *c = &bus->console;
  2303. u8 line[CONSOLE_LINE_MAX], ch;
  2304. u32 n, idx, addr;
  2305. int rv;
  2306. /* Don't do anything until FWREADY updates console address */
  2307. if (bus->console_addr == 0)
  2308. return 0;
  2309. /* Read console log struct */
  2310. addr = bus->console_addr + offsetof(struct rte_console, log_le);
  2311. rv = brcmf_sdbrcm_membytes(bus, false, addr, (u8 *)&c->log_le,
  2312. sizeof(c->log_le));
  2313. if (rv < 0)
  2314. return rv;
  2315. /* Allocate console buffer (one time only) */
  2316. if (c->buf == NULL) {
  2317. c->bufsize = le32_to_cpu(c->log_le.buf_size);
  2318. c->buf = kmalloc(c->bufsize, GFP_ATOMIC);
  2319. if (c->buf == NULL)
  2320. return -ENOMEM;
  2321. }
  2322. idx = le32_to_cpu(c->log_le.idx);
  2323. /* Protect against corrupt value */
  2324. if (idx > c->bufsize)
  2325. return -EBADE;
  2326. /* Skip reading the console buffer if the index pointer
  2327. has not moved */
  2328. if (idx == c->last)
  2329. return 0;
  2330. /* Read the console buffer */
  2331. addr = le32_to_cpu(c->log_le.buf);
  2332. rv = brcmf_sdbrcm_membytes(bus, false, addr, c->buf, c->bufsize);
  2333. if (rv < 0)
  2334. return rv;
  2335. while (c->last != idx) {
  2336. for (n = 0; n < CONSOLE_LINE_MAX - 2; n++) {
  2337. if (c->last == idx) {
  2338. /* This would output a partial line.
  2339. * Instead, back up
  2340. * the buffer pointer and output this
  2341. * line next time around.
  2342. */
  2343. if (c->last >= n)
  2344. c->last -= n;
  2345. else
  2346. c->last = c->bufsize - n;
  2347. goto break2;
  2348. }
  2349. ch = c->buf[c->last];
  2350. c->last = (c->last + 1) % c->bufsize;
  2351. if (ch == '\n')
  2352. break;
  2353. line[n] = ch;
  2354. }
  2355. if (n > 0) {
  2356. if (line[n - 1] == '\r')
  2357. n--;
  2358. line[n] = 0;
  2359. printk(KERN_DEBUG "CONSOLE: %s\n", line);
  2360. }
  2361. }
  2362. break2:
  2363. return 0;
  2364. }
  2365. #endif /* BCMDBG */
  2366. static int brcmf_tx_frame(struct brcmf_bus *bus, u8 *frame, u16 len)
  2367. {
  2368. int i;
  2369. int ret;
  2370. bus->ctrl_frame_stat = false;
  2371. ret = brcmf_sdbrcm_send_buf(bus, bus->sdiodev->sbwad,
  2372. SDIO_FUNC_2, F2SYNC, frame, len, NULL);
  2373. if (ret < 0) {
  2374. /* On failure, abort the command and terminate the frame */
  2375. brcmf_dbg(INFO, "sdio error %d, abort command and terminate frame\n",
  2376. ret);
  2377. bus->tx_sderrs++;
  2378. brcmf_sdcard_abort(bus->sdiodev, SDIO_FUNC_2);
  2379. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2380. SBSDIO_FUNC1_FRAMECTRL,
  2381. SFC_WF_TERM, NULL);
  2382. bus->f1regdata++;
  2383. for (i = 0; i < 3; i++) {
  2384. u8 hi, lo;
  2385. hi = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2386. SBSDIO_FUNC1_WFRAMEBCHI,
  2387. NULL);
  2388. lo = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2389. SBSDIO_FUNC1_WFRAMEBCLO,
  2390. NULL);
  2391. bus->f1regdata += 2;
  2392. if (hi == 0 && lo == 0)
  2393. break;
  2394. }
  2395. return ret;
  2396. }
  2397. bus->tx_seq = (bus->tx_seq + 1) % SDPCM_SEQUENCE_WRAP;
  2398. return ret;
  2399. }
  2400. int
  2401. brcmf_sdbrcm_bus_txctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
  2402. {
  2403. u8 *frame;
  2404. u16 len;
  2405. u32 swheader;
  2406. uint retries = 0;
  2407. u8 doff = 0;
  2408. int ret = -1;
  2409. brcmf_dbg(TRACE, "Enter\n");
  2410. /* Back the pointer to make a room for bus header */
  2411. frame = msg - SDPCM_HDRLEN;
  2412. len = (msglen += SDPCM_HDRLEN);
  2413. /* Add alignment padding (optional for ctl frames) */
  2414. doff = ((unsigned long)frame % BRCMF_SDALIGN);
  2415. if (doff) {
  2416. frame -= doff;
  2417. len += doff;
  2418. msglen += doff;
  2419. memset(frame, 0, doff + SDPCM_HDRLEN);
  2420. }
  2421. /* precondition: doff < BRCMF_SDALIGN */
  2422. doff += SDPCM_HDRLEN;
  2423. /* Round send length to next SDIO block */
  2424. if (bus->roundup && bus->blocksize && (len > bus->blocksize)) {
  2425. u16 pad = bus->blocksize - (len % bus->blocksize);
  2426. if ((pad <= bus->roundup) && (pad < bus->blocksize))
  2427. len += pad;
  2428. } else if (len % BRCMF_SDALIGN) {
  2429. len += BRCMF_SDALIGN - (len % BRCMF_SDALIGN);
  2430. }
  2431. /* Satisfy length-alignment requirements */
  2432. if (len & (ALIGNMENT - 1))
  2433. len = roundup(len, ALIGNMENT);
  2434. /* precondition: IS_ALIGNED((unsigned long)frame, 2) */
  2435. /* Need to lock here to protect txseq and SDIO tx calls */
  2436. down(&bus->sdsem);
  2437. bus_wake(bus);
  2438. /* Make sure backplane clock is on */
  2439. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2440. /* Hardware tag: 2 byte len followed by 2 byte ~len check (all LE) */
  2441. *(__le16 *) frame = cpu_to_le16((u16) msglen);
  2442. *(((__le16 *) frame) + 1) = cpu_to_le16(~msglen);
  2443. /* Software tag: channel, sequence number, data offset */
  2444. swheader =
  2445. ((SDPCM_CONTROL_CHANNEL << SDPCM_CHANNEL_SHIFT) &
  2446. SDPCM_CHANNEL_MASK)
  2447. | bus->tx_seq | ((doff << SDPCM_DOFFSET_SHIFT) &
  2448. SDPCM_DOFFSET_MASK);
  2449. put_unaligned_le32(swheader, frame + SDPCM_FRAMETAG_LEN);
  2450. put_unaligned_le32(0, frame + SDPCM_FRAMETAG_LEN + sizeof(swheader));
  2451. if (!data_ok(bus)) {
  2452. brcmf_dbg(INFO, "No bus credit bus->tx_max %d, bus->tx_seq %d\n",
  2453. bus->tx_max, bus->tx_seq);
  2454. bus->ctrl_frame_stat = true;
  2455. /* Send from dpc */
  2456. bus->ctrl_frame_buf = frame;
  2457. bus->ctrl_frame_len = len;
  2458. brcmf_sdbrcm_wait_for_event(bus, &bus->ctrl_frame_stat);
  2459. if (bus->ctrl_frame_stat == false) {
  2460. brcmf_dbg(INFO, "ctrl_frame_stat == false\n");
  2461. ret = 0;
  2462. } else {
  2463. brcmf_dbg(INFO, "ctrl_frame_stat == true\n");
  2464. ret = -1;
  2465. }
  2466. }
  2467. if (ret == -1) {
  2468. #ifdef BCMDBG
  2469. if (BRCMF_BYTES_ON() && BRCMF_CTL_ON()) {
  2470. printk(KERN_DEBUG "Tx Frame:\n");
  2471. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2472. frame, len);
  2473. } else if (BRCMF_HDRS_ON()) {
  2474. printk(KERN_DEBUG "TxHdr:\n");
  2475. print_hex_dump_bytes("", DUMP_PREFIX_OFFSET,
  2476. frame, min_t(u16, len, 16));
  2477. }
  2478. #endif
  2479. do {
  2480. ret = brcmf_tx_frame(bus, frame, len);
  2481. } while (ret < 0 && retries++ < TXRETRIES);
  2482. }
  2483. if ((bus->idletime == BRCMF_IDLE_IMMEDIATE) && !bus->dpc_sched) {
  2484. bus->activity = false;
  2485. brcmf_sdbrcm_clkctl(bus, CLK_NONE, true);
  2486. }
  2487. up(&bus->sdsem);
  2488. if (ret)
  2489. bus->drvr->tx_ctlerrs++;
  2490. else
  2491. bus->drvr->tx_ctlpkts++;
  2492. return ret ? -EIO : 0;
  2493. }
  2494. int
  2495. brcmf_sdbrcm_bus_rxctl(struct brcmf_bus *bus, unsigned char *msg, uint msglen)
  2496. {
  2497. int timeleft;
  2498. uint rxlen = 0;
  2499. bool pending;
  2500. brcmf_dbg(TRACE, "Enter\n");
  2501. /* Wait until control frame is available */
  2502. timeleft = brcmf_sdbrcm_dcmd_resp_wait(bus, &bus->rxlen, &pending);
  2503. down(&bus->sdsem);
  2504. rxlen = bus->rxlen;
  2505. memcpy(msg, bus->rxctl, min(msglen, rxlen));
  2506. bus->rxlen = 0;
  2507. up(&bus->sdsem);
  2508. if (rxlen) {
  2509. brcmf_dbg(CTL, "resumed on rxctl frame, got %d expected %d\n",
  2510. rxlen, msglen);
  2511. } else if (timeleft == 0) {
  2512. brcmf_dbg(ERROR, "resumed on timeout\n");
  2513. } else if (pending == true) {
  2514. brcmf_dbg(CTL, "cancelled\n");
  2515. return -ERESTARTSYS;
  2516. } else {
  2517. brcmf_dbg(CTL, "resumed for unknown reason?\n");
  2518. }
  2519. if (rxlen)
  2520. bus->drvr->rx_ctlpkts++;
  2521. else
  2522. bus->drvr->rx_ctlerrs++;
  2523. return rxlen ? (int)rxlen : -ETIMEDOUT;
  2524. }
  2525. static int brcmf_sdbrcm_downloadvars(struct brcmf_bus *bus, void *arg, int len)
  2526. {
  2527. int bcmerror = 0;
  2528. brcmf_dbg(TRACE, "Enter\n");
  2529. /* Basic sanity checks */
  2530. if (bus->drvr->up) {
  2531. bcmerror = -EISCONN;
  2532. goto err;
  2533. }
  2534. if (!len) {
  2535. bcmerror = -EOVERFLOW;
  2536. goto err;
  2537. }
  2538. /* Free the old ones and replace with passed variables */
  2539. kfree(bus->vars);
  2540. bus->vars = kmalloc(len, GFP_ATOMIC);
  2541. bus->varsz = bus->vars ? len : 0;
  2542. if (bus->vars == NULL) {
  2543. bcmerror = -ENOMEM;
  2544. goto err;
  2545. }
  2546. /* Copy the passed variables, which should include the
  2547. terminating double-null */
  2548. memcpy(bus->vars, arg, bus->varsz);
  2549. err:
  2550. return bcmerror;
  2551. }
  2552. static int brcmf_sdbrcm_write_vars(struct brcmf_bus *bus)
  2553. {
  2554. int bcmerror = 0;
  2555. u32 varsize;
  2556. u32 varaddr;
  2557. u8 *vbuffer;
  2558. u32 varsizew;
  2559. __le32 varsizew_le;
  2560. #ifdef BCMDBG
  2561. char *nvram_ularray;
  2562. #endif /* BCMDBG */
  2563. /* Even if there are no vars are to be written, we still
  2564. need to set the ramsize. */
  2565. varsize = bus->varsz ? roundup(bus->varsz, 4) : 0;
  2566. varaddr = (bus->ramsize - 4) - varsize;
  2567. if (bus->vars) {
  2568. vbuffer = kzalloc(varsize, GFP_ATOMIC);
  2569. if (!vbuffer)
  2570. return -ENOMEM;
  2571. memcpy(vbuffer, bus->vars, bus->varsz);
  2572. /* Write the vars list */
  2573. bcmerror =
  2574. brcmf_sdbrcm_membytes(bus, true, varaddr, vbuffer, varsize);
  2575. #ifdef BCMDBG
  2576. /* Verify NVRAM bytes */
  2577. brcmf_dbg(INFO, "Compare NVRAM dl & ul; varsize=%d\n", varsize);
  2578. nvram_ularray = kmalloc(varsize, GFP_ATOMIC);
  2579. if (!nvram_ularray)
  2580. return -ENOMEM;
  2581. /* Upload image to verify downloaded contents. */
  2582. memset(nvram_ularray, 0xaa, varsize);
  2583. /* Read the vars list to temp buffer for comparison */
  2584. bcmerror =
  2585. brcmf_sdbrcm_membytes(bus, false, varaddr, nvram_ularray,
  2586. varsize);
  2587. if (bcmerror) {
  2588. brcmf_dbg(ERROR, "error %d on reading %d nvram bytes at 0x%08x\n",
  2589. bcmerror, varsize, varaddr);
  2590. }
  2591. /* Compare the org NVRAM with the one read from RAM */
  2592. if (memcmp(vbuffer, nvram_ularray, varsize))
  2593. brcmf_dbg(ERROR, "Downloaded NVRAM image is corrupted\n");
  2594. else
  2595. brcmf_dbg(ERROR, "Download/Upload/Compare of NVRAM ok\n");
  2596. kfree(nvram_ularray);
  2597. #endif /* BCMDBG */
  2598. kfree(vbuffer);
  2599. }
  2600. /* adjust to the user specified RAM */
  2601. brcmf_dbg(INFO, "Physical memory size: %d\n", bus->ramsize);
  2602. brcmf_dbg(INFO, "Vars are at %d, orig varsize is %d\n",
  2603. varaddr, varsize);
  2604. varsize = ((bus->ramsize - 4) - varaddr);
  2605. /*
  2606. * Determine the length token:
  2607. * Varsize, converted to words, in lower 16-bits, checksum
  2608. * in upper 16-bits.
  2609. */
  2610. if (bcmerror) {
  2611. varsizew = 0;
  2612. varsizew_le = cpu_to_le32(0);
  2613. } else {
  2614. varsizew = varsize / 4;
  2615. varsizew = (~varsizew << 16) | (varsizew & 0x0000FFFF);
  2616. varsizew_le = cpu_to_le32(varsizew);
  2617. }
  2618. brcmf_dbg(INFO, "New varsize is %d, length token=0x%08x\n",
  2619. varsize, varsizew);
  2620. /* Write the length token to the last word */
  2621. bcmerror = brcmf_sdbrcm_membytes(bus, true, (bus->ramsize - 4),
  2622. (u8 *)&varsizew_le, 4);
  2623. return bcmerror;
  2624. }
  2625. static int brcmf_sdbrcm_download_state(struct brcmf_bus *bus, bool enter)
  2626. {
  2627. uint retries;
  2628. int bcmerror = 0;
  2629. /* To enter download state, disable ARM and reset SOCRAM.
  2630. * To exit download state, simply reset ARM (default is RAM boot).
  2631. */
  2632. if (enter) {
  2633. bus->alp_only = true;
  2634. brcmf_sdio_chip_coredisable(bus->sdiodev,
  2635. bus->ci->armcorebase);
  2636. brcmf_sdio_chip_resetcore(bus->sdiodev, bus->ci->ramcorebase);
  2637. /* Clear the top bit of memory */
  2638. if (bus->ramsize) {
  2639. u32 zeros = 0;
  2640. brcmf_sdbrcm_membytes(bus, true, bus->ramsize - 4,
  2641. (u8 *)&zeros, 4);
  2642. }
  2643. } else {
  2644. if (!brcmf_sdio_chip_iscoreup(bus->sdiodev,
  2645. bus->ci->ramcorebase)) {
  2646. brcmf_dbg(ERROR, "SOCRAM core is down after reset?\n");
  2647. bcmerror = -EBADE;
  2648. goto fail;
  2649. }
  2650. bcmerror = brcmf_sdbrcm_write_vars(bus);
  2651. if (bcmerror) {
  2652. brcmf_dbg(ERROR, "no vars written to RAM\n");
  2653. bcmerror = 0;
  2654. }
  2655. w_sdreg32(bus, 0xFFFFFFFF,
  2656. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2657. brcmf_sdio_chip_resetcore(bus->sdiodev, bus->ci->armcorebase);
  2658. /* Allow HT Clock now that the ARM is running. */
  2659. bus->alp_only = false;
  2660. bus->drvr->busstate = BRCMF_BUS_LOAD;
  2661. }
  2662. fail:
  2663. return bcmerror;
  2664. }
  2665. static int brcmf_sdbrcm_get_image(char *buf, int len, struct brcmf_bus *bus)
  2666. {
  2667. if (bus->firmware->size < bus->fw_ptr + len)
  2668. len = bus->firmware->size - bus->fw_ptr;
  2669. memcpy(buf, &bus->firmware->data[bus->fw_ptr], len);
  2670. bus->fw_ptr += len;
  2671. return len;
  2672. }
  2673. MODULE_FIRMWARE(BCM4329_FW_NAME);
  2674. MODULE_FIRMWARE(BCM4329_NV_NAME);
  2675. static int brcmf_sdbrcm_download_code_file(struct brcmf_bus *bus)
  2676. {
  2677. int offset = 0;
  2678. uint len;
  2679. u8 *memblock = NULL, *memptr;
  2680. int ret;
  2681. brcmf_dbg(INFO, "Enter\n");
  2682. bus->fw_name = BCM4329_FW_NAME;
  2683. ret = request_firmware(&bus->firmware, bus->fw_name,
  2684. &bus->sdiodev->func[2]->dev);
  2685. if (ret) {
  2686. brcmf_dbg(ERROR, "Fail to request firmware %d\n", ret);
  2687. return ret;
  2688. }
  2689. bus->fw_ptr = 0;
  2690. memptr = memblock = kmalloc(MEMBLOCK + BRCMF_SDALIGN, GFP_ATOMIC);
  2691. if (memblock == NULL) {
  2692. ret = -ENOMEM;
  2693. goto err;
  2694. }
  2695. if ((u32)(unsigned long)memblock % BRCMF_SDALIGN)
  2696. memptr += (BRCMF_SDALIGN -
  2697. ((u32)(unsigned long)memblock % BRCMF_SDALIGN));
  2698. /* Download image */
  2699. while ((len =
  2700. brcmf_sdbrcm_get_image((char *)memptr, MEMBLOCK, bus))) {
  2701. ret = brcmf_sdbrcm_membytes(bus, true, offset, memptr, len);
  2702. if (ret) {
  2703. brcmf_dbg(ERROR, "error %d on writing %d membytes at 0x%08x\n",
  2704. ret, MEMBLOCK, offset);
  2705. goto err;
  2706. }
  2707. offset += MEMBLOCK;
  2708. }
  2709. err:
  2710. kfree(memblock);
  2711. release_firmware(bus->firmware);
  2712. bus->fw_ptr = 0;
  2713. return ret;
  2714. }
  2715. /*
  2716. * ProcessVars:Takes a buffer of "<var>=<value>\n" lines read from a file
  2717. * and ending in a NUL.
  2718. * Removes carriage returns, empty lines, comment lines, and converts
  2719. * newlines to NULs.
  2720. * Shortens buffer as needed and pads with NULs. End of buffer is marked
  2721. * by two NULs.
  2722. */
  2723. static uint brcmf_process_nvram_vars(char *varbuf, uint len)
  2724. {
  2725. char *dp;
  2726. bool findNewline;
  2727. int column;
  2728. uint buf_len, n;
  2729. dp = varbuf;
  2730. findNewline = false;
  2731. column = 0;
  2732. for (n = 0; n < len; n++) {
  2733. if (varbuf[n] == 0)
  2734. break;
  2735. if (varbuf[n] == '\r')
  2736. continue;
  2737. if (findNewline && varbuf[n] != '\n')
  2738. continue;
  2739. findNewline = false;
  2740. if (varbuf[n] == '#') {
  2741. findNewline = true;
  2742. continue;
  2743. }
  2744. if (varbuf[n] == '\n') {
  2745. if (column == 0)
  2746. continue;
  2747. *dp++ = 0;
  2748. column = 0;
  2749. continue;
  2750. }
  2751. *dp++ = varbuf[n];
  2752. column++;
  2753. }
  2754. buf_len = dp - varbuf;
  2755. while (dp < varbuf + n)
  2756. *dp++ = 0;
  2757. return buf_len;
  2758. }
  2759. static int brcmf_sdbrcm_download_nvram(struct brcmf_bus *bus)
  2760. {
  2761. uint len;
  2762. char *memblock = NULL;
  2763. char *bufp;
  2764. int ret;
  2765. bus->nv_name = BCM4329_NV_NAME;
  2766. ret = request_firmware(&bus->firmware, bus->nv_name,
  2767. &bus->sdiodev->func[2]->dev);
  2768. if (ret) {
  2769. brcmf_dbg(ERROR, "Fail to request nvram %d\n", ret);
  2770. return ret;
  2771. }
  2772. bus->fw_ptr = 0;
  2773. memblock = kmalloc(MEMBLOCK, GFP_ATOMIC);
  2774. if (memblock == NULL) {
  2775. ret = -ENOMEM;
  2776. goto err;
  2777. }
  2778. len = brcmf_sdbrcm_get_image(memblock, MEMBLOCK, bus);
  2779. if (len > 0 && len < MEMBLOCK) {
  2780. bufp = (char *)memblock;
  2781. bufp[len] = 0;
  2782. len = brcmf_process_nvram_vars(bufp, len);
  2783. bufp += len;
  2784. *bufp++ = 0;
  2785. if (len)
  2786. ret = brcmf_sdbrcm_downloadvars(bus, memblock, len + 1);
  2787. if (ret)
  2788. brcmf_dbg(ERROR, "error downloading vars: %d\n", ret);
  2789. } else {
  2790. brcmf_dbg(ERROR, "error reading nvram file: %d\n", len);
  2791. ret = -EIO;
  2792. }
  2793. err:
  2794. kfree(memblock);
  2795. release_firmware(bus->firmware);
  2796. bus->fw_ptr = 0;
  2797. return ret;
  2798. }
  2799. static int _brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
  2800. {
  2801. int bcmerror = -1;
  2802. /* Keep arm in reset */
  2803. if (brcmf_sdbrcm_download_state(bus, true)) {
  2804. brcmf_dbg(ERROR, "error placing ARM core in reset\n");
  2805. goto err;
  2806. }
  2807. /* External image takes precedence if specified */
  2808. if (brcmf_sdbrcm_download_code_file(bus)) {
  2809. brcmf_dbg(ERROR, "dongle image file download failed\n");
  2810. goto err;
  2811. }
  2812. /* External nvram takes precedence if specified */
  2813. if (brcmf_sdbrcm_download_nvram(bus))
  2814. brcmf_dbg(ERROR, "dongle nvram file download failed\n");
  2815. /* Take arm out of reset */
  2816. if (brcmf_sdbrcm_download_state(bus, false)) {
  2817. brcmf_dbg(ERROR, "error getting out of ARM core reset\n");
  2818. goto err;
  2819. }
  2820. bcmerror = 0;
  2821. err:
  2822. return bcmerror;
  2823. }
  2824. static bool
  2825. brcmf_sdbrcm_download_firmware(struct brcmf_bus *bus)
  2826. {
  2827. bool ret;
  2828. /* Download the firmware */
  2829. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2830. ret = _brcmf_sdbrcm_download_firmware(bus) == 0;
  2831. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2832. return ret;
  2833. }
  2834. void brcmf_sdbrcm_bus_stop(struct brcmf_bus *bus)
  2835. {
  2836. u32 local_hostintmask;
  2837. u8 saveclk;
  2838. uint retries;
  2839. int err;
  2840. struct sk_buff *cur;
  2841. struct sk_buff *next;
  2842. brcmf_dbg(TRACE, "Enter\n");
  2843. if (bus->watchdog_tsk) {
  2844. send_sig(SIGTERM, bus->watchdog_tsk, 1);
  2845. kthread_stop(bus->watchdog_tsk);
  2846. bus->watchdog_tsk = NULL;
  2847. }
  2848. if (bus->dpc_tsk && bus->dpc_tsk != current) {
  2849. send_sig(SIGTERM, bus->dpc_tsk, 1);
  2850. kthread_stop(bus->dpc_tsk);
  2851. bus->dpc_tsk = NULL;
  2852. }
  2853. down(&bus->sdsem);
  2854. bus_wake(bus);
  2855. /* Enable clock for device interrupts */
  2856. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2857. /* Disable and clear interrupts at the chip level also */
  2858. w_sdreg32(bus, 0, offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2859. local_hostintmask = bus->hostintmask;
  2860. bus->hostintmask = 0;
  2861. /* Change our idea of bus state */
  2862. bus->drvr->busstate = BRCMF_BUS_DOWN;
  2863. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2864. saveclk = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2865. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2866. if (!err) {
  2867. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2868. SBSDIO_FUNC1_CHIPCLKCSR,
  2869. (saveclk | SBSDIO_FORCE_HT), &err);
  2870. }
  2871. if (err)
  2872. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2873. /* Turn off the bus (F2), free any pending packets */
  2874. brcmf_dbg(INTR, "disable SDIO interrupts\n");
  2875. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2876. SDIO_FUNC_ENABLE_1, NULL);
  2877. /* Clear any pending interrupts now that F2 is disabled */
  2878. w_sdreg32(bus, local_hostintmask,
  2879. offsetof(struct sdpcmd_regs, intstatus), &retries);
  2880. /* Turn off the backplane clock (only) */
  2881. brcmf_sdbrcm_clkctl(bus, CLK_SDONLY, false);
  2882. /* Clear the data packet queues */
  2883. brcmu_pktq_flush(&bus->txq, true, NULL, NULL);
  2884. /* Clear any held glomming stuff */
  2885. if (bus->glomd)
  2886. brcmu_pkt_buf_free_skb(bus->glomd);
  2887. if (!skb_queue_empty(&bus->glom))
  2888. skb_queue_walk_safe(&bus->glom, cur, next) {
  2889. skb_unlink(cur, &bus->glom);
  2890. brcmu_pkt_buf_free_skb(cur);
  2891. }
  2892. /* Clear rx control and wake any waiters */
  2893. bus->rxlen = 0;
  2894. brcmf_sdbrcm_dcmd_resp_wake(bus);
  2895. /* Reset some F2 state stuff */
  2896. bus->rxskip = false;
  2897. bus->tx_seq = bus->rx_seq = 0;
  2898. up(&bus->sdsem);
  2899. }
  2900. int brcmf_sdbrcm_bus_init(struct brcmf_pub *drvr)
  2901. {
  2902. struct brcmf_bus *bus = drvr->bus;
  2903. unsigned long timeout;
  2904. uint retries = 0;
  2905. u8 ready, enable;
  2906. int err, ret = 0;
  2907. u8 saveclk;
  2908. brcmf_dbg(TRACE, "Enter\n");
  2909. /* try to download image and nvram to the dongle */
  2910. if (drvr->busstate == BRCMF_BUS_DOWN) {
  2911. if (!(brcmf_sdbrcm_download_firmware(bus)))
  2912. return -1;
  2913. }
  2914. if (!bus->drvr)
  2915. return 0;
  2916. /* Start the watchdog timer */
  2917. bus->drvr->tickcnt = 0;
  2918. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  2919. down(&bus->sdsem);
  2920. /* Make sure backplane clock is on, needed to generate F2 interrupt */
  2921. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  2922. if (bus->clkstate != CLK_AVAIL)
  2923. goto exit;
  2924. /* Force clocks on backplane to be sure F2 interrupt propagates */
  2925. saveclk =
  2926. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  2927. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  2928. if (!err) {
  2929. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2930. SBSDIO_FUNC1_CHIPCLKCSR,
  2931. (saveclk | SBSDIO_FORCE_HT), &err);
  2932. }
  2933. if (err) {
  2934. brcmf_dbg(ERROR, "Failed to force clock for F2: err %d\n", err);
  2935. goto exit;
  2936. }
  2937. /* Enable function 2 (frame transfers) */
  2938. w_sdreg32(bus, SDPCM_PROT_VERSION << SMB_DATA_VERSION_SHIFT,
  2939. offsetof(struct sdpcmd_regs, tosbmailboxdata), &retries);
  2940. enable = (SDIO_FUNC_ENABLE_1 | SDIO_FUNC_ENABLE_2);
  2941. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  2942. enable, NULL);
  2943. timeout = jiffies + msecs_to_jiffies(BRCMF_WAIT_F2RDY);
  2944. ready = 0;
  2945. while (enable != ready) {
  2946. ready = brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_0,
  2947. SDIO_CCCR_IORx, NULL);
  2948. if (time_after(jiffies, timeout))
  2949. break;
  2950. else if (time_after(jiffies, timeout - BRCMF_WAIT_F2RDY + 50))
  2951. /* prevent busy waiting if it takes too long */
  2952. msleep_interruptible(20);
  2953. }
  2954. brcmf_dbg(INFO, "enable 0x%02x, ready 0x%02x\n", enable, ready);
  2955. /* If F2 successfully enabled, set core and enable interrupts */
  2956. if (ready == enable) {
  2957. /* Set up the interrupt mask and enable interrupts */
  2958. bus->hostintmask = HOSTINTMASK;
  2959. w_sdreg32(bus, bus->hostintmask,
  2960. offsetof(struct sdpcmd_regs, hostintmask), &retries);
  2961. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2962. SBSDIO_WATERMARK, 8, &err);
  2963. /* Set bus state according to enable result */
  2964. drvr->busstate = BRCMF_BUS_DATA;
  2965. }
  2966. else {
  2967. /* Disable F2 again */
  2968. enable = SDIO_FUNC_ENABLE_1;
  2969. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0,
  2970. SDIO_CCCR_IOEx, enable, NULL);
  2971. }
  2972. /* Restore previous clock setting */
  2973. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  2974. SBSDIO_FUNC1_CHIPCLKCSR, saveclk, &err);
  2975. /* If we didn't come up, turn off backplane clock */
  2976. if (drvr->busstate != BRCMF_BUS_DATA)
  2977. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  2978. exit:
  2979. up(&bus->sdsem);
  2980. return ret;
  2981. }
  2982. void brcmf_sdbrcm_isr(void *arg)
  2983. {
  2984. struct brcmf_bus *bus = (struct brcmf_bus *) arg;
  2985. brcmf_dbg(TRACE, "Enter\n");
  2986. if (!bus) {
  2987. brcmf_dbg(ERROR, "bus is null pointer, exiting\n");
  2988. return;
  2989. }
  2990. if (bus->drvr->busstate == BRCMF_BUS_DOWN) {
  2991. brcmf_dbg(ERROR, "bus is down. we have nothing to do\n");
  2992. return;
  2993. }
  2994. /* Count the interrupt call */
  2995. bus->intrcount++;
  2996. bus->ipend = true;
  2997. /* Shouldn't get this interrupt if we're sleeping? */
  2998. if (bus->sleeping) {
  2999. brcmf_dbg(ERROR, "INTERRUPT WHILE SLEEPING??\n");
  3000. return;
  3001. }
  3002. /* Disable additional interrupts (is this needed now)? */
  3003. if (!bus->intr)
  3004. brcmf_dbg(ERROR, "isr w/o interrupt configured!\n");
  3005. bus->dpc_sched = true;
  3006. if (bus->dpc_tsk)
  3007. complete(&bus->dpc_wait);
  3008. }
  3009. static bool brcmf_sdbrcm_bus_watchdog(struct brcmf_pub *drvr)
  3010. {
  3011. struct brcmf_bus *bus;
  3012. brcmf_dbg(TIMER, "Enter\n");
  3013. bus = drvr->bus;
  3014. /* Ignore the timer if simulating bus down */
  3015. if (bus->sleeping)
  3016. return false;
  3017. down(&bus->sdsem);
  3018. /* Poll period: check device if appropriate. */
  3019. if (bus->poll && (++bus->polltick >= bus->pollrate)) {
  3020. u32 intstatus = 0;
  3021. /* Reset poll tick */
  3022. bus->polltick = 0;
  3023. /* Check device if no interrupts */
  3024. if (!bus->intr || (bus->intrcount == bus->lastintrs)) {
  3025. if (!bus->dpc_sched) {
  3026. u8 devpend;
  3027. devpend = brcmf_sdcard_cfg_read(bus->sdiodev,
  3028. SDIO_FUNC_0, SDIO_CCCR_INTx,
  3029. NULL);
  3030. intstatus =
  3031. devpend & (INTR_STATUS_FUNC1 |
  3032. INTR_STATUS_FUNC2);
  3033. }
  3034. /* If there is something, make like the ISR and
  3035. schedule the DPC */
  3036. if (intstatus) {
  3037. bus->pollcnt++;
  3038. bus->ipend = true;
  3039. bus->dpc_sched = true;
  3040. if (bus->dpc_tsk)
  3041. complete(&bus->dpc_wait);
  3042. }
  3043. }
  3044. /* Update interrupt tracking */
  3045. bus->lastintrs = bus->intrcount;
  3046. }
  3047. #ifdef BCMDBG
  3048. /* Poll for console output periodically */
  3049. if (drvr->busstate == BRCMF_BUS_DATA && bus->console_interval != 0) {
  3050. bus->console.count += BRCMF_WD_POLL_MS;
  3051. if (bus->console.count >= bus->console_interval) {
  3052. bus->console.count -= bus->console_interval;
  3053. /* Make sure backplane clock is on */
  3054. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3055. if (brcmf_sdbrcm_readconsole(bus) < 0)
  3056. /* stop on error */
  3057. bus->console_interval = 0;
  3058. }
  3059. }
  3060. #endif /* BCMDBG */
  3061. /* On idle timeout clear activity flag and/or turn off clock */
  3062. if ((bus->idletime > 0) && (bus->clkstate == CLK_AVAIL)) {
  3063. if (++bus->idlecount >= bus->idletime) {
  3064. bus->idlecount = 0;
  3065. if (bus->activity) {
  3066. bus->activity = false;
  3067. brcmf_sdbrcm_wd_timer(bus, BRCMF_WD_POLL_MS);
  3068. } else {
  3069. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3070. }
  3071. }
  3072. }
  3073. up(&bus->sdsem);
  3074. return bus->ipend;
  3075. }
  3076. static bool brcmf_sdbrcm_chipmatch(u16 chipid)
  3077. {
  3078. if (chipid == BCM4329_CHIP_ID)
  3079. return true;
  3080. return false;
  3081. }
  3082. static void brcmf_sdbrcm_release_malloc(struct brcmf_bus *bus)
  3083. {
  3084. brcmf_dbg(TRACE, "Enter\n");
  3085. kfree(bus->rxbuf);
  3086. bus->rxctl = bus->rxbuf = NULL;
  3087. bus->rxlen = 0;
  3088. kfree(bus->databuf);
  3089. bus->databuf = NULL;
  3090. }
  3091. static bool brcmf_sdbrcm_probe_malloc(struct brcmf_bus *bus)
  3092. {
  3093. brcmf_dbg(TRACE, "Enter\n");
  3094. if (bus->drvr->maxctl) {
  3095. bus->rxblen =
  3096. roundup((bus->drvr->maxctl + SDPCM_HDRLEN),
  3097. ALIGNMENT) + BRCMF_SDALIGN;
  3098. bus->rxbuf = kmalloc(bus->rxblen, GFP_ATOMIC);
  3099. if (!(bus->rxbuf))
  3100. goto fail;
  3101. }
  3102. /* Allocate buffer to receive glomed packet */
  3103. bus->databuf = kmalloc(MAX_DATA_BUF, GFP_ATOMIC);
  3104. if (!(bus->databuf)) {
  3105. /* release rxbuf which was already located as above */
  3106. if (!bus->rxblen)
  3107. kfree(bus->rxbuf);
  3108. goto fail;
  3109. }
  3110. /* Align the buffer */
  3111. if ((unsigned long)bus->databuf % BRCMF_SDALIGN)
  3112. bus->dataptr = bus->databuf + (BRCMF_SDALIGN -
  3113. ((unsigned long)bus->databuf % BRCMF_SDALIGN));
  3114. else
  3115. bus->dataptr = bus->databuf;
  3116. return true;
  3117. fail:
  3118. return false;
  3119. }
  3120. /* SDIO Pad drive strength to select value mappings */
  3121. struct sdiod_drive_str {
  3122. u8 strength; /* Pad Drive Strength in mA */
  3123. u8 sel; /* Chip-specific select value */
  3124. };
  3125. /* SDIO Drive Strength to sel value table for PMU Rev 1 */
  3126. static const struct sdiod_drive_str sdiod_drive_strength_tab1[] = {
  3127. {
  3128. 4, 0x2}, {
  3129. 2, 0x3}, {
  3130. 1, 0x0}, {
  3131. 0, 0x0}
  3132. };
  3133. /* SDIO Drive Strength to sel value table for PMU Rev 2, 3 */
  3134. static const struct sdiod_drive_str sdiod_drive_strength_tab2[] = {
  3135. {
  3136. 12, 0x7}, {
  3137. 10, 0x6}, {
  3138. 8, 0x5}, {
  3139. 6, 0x4}, {
  3140. 4, 0x2}, {
  3141. 2, 0x1}, {
  3142. 0, 0x0}
  3143. };
  3144. /* SDIO Drive Strength to sel value table for PMU Rev 8 (1.8V) */
  3145. static const struct sdiod_drive_str sdiod_drive_strength_tab3[] = {
  3146. {
  3147. 32, 0x7}, {
  3148. 26, 0x6}, {
  3149. 22, 0x5}, {
  3150. 16, 0x4}, {
  3151. 12, 0x3}, {
  3152. 8, 0x2}, {
  3153. 4, 0x1}, {
  3154. 0, 0x0}
  3155. };
  3156. #define SDIOD_DRVSTR_KEY(chip, pmu) (((chip) << 16) | (pmu))
  3157. static char *brcmf_chipname(uint chipid, char *buf, uint len)
  3158. {
  3159. const char *fmt;
  3160. fmt = ((chipid > 0xa000) || (chipid < 0x4000)) ? "%d" : "%x";
  3161. snprintf(buf, len, fmt, chipid);
  3162. return buf;
  3163. }
  3164. static void brcmf_sdbrcm_sdiod_drive_strength_init(struct brcmf_bus *bus,
  3165. u32 drivestrength) {
  3166. struct sdiod_drive_str *str_tab = NULL;
  3167. u32 str_mask = 0;
  3168. u32 str_shift = 0;
  3169. char chn[8];
  3170. if (!(bus->ci->cccaps & CC_CAP_PMU))
  3171. return;
  3172. switch (SDIOD_DRVSTR_KEY(bus->ci->chip, bus->ci->pmurev)) {
  3173. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 1):
  3174. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab1;
  3175. str_mask = 0x30000000;
  3176. str_shift = 28;
  3177. break;
  3178. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 2):
  3179. case SDIOD_DRVSTR_KEY(BCM4325_CHIP_ID, 3):
  3180. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab2;
  3181. str_mask = 0x00003800;
  3182. str_shift = 11;
  3183. break;
  3184. case SDIOD_DRVSTR_KEY(BCM4336_CHIP_ID, 8):
  3185. str_tab = (struct sdiod_drive_str *)&sdiod_drive_strength_tab3;
  3186. str_mask = 0x00003800;
  3187. str_shift = 11;
  3188. break;
  3189. default:
  3190. brcmf_dbg(ERROR, "No SDIO Drive strength init done for chip %s rev %d pmurev %d\n",
  3191. brcmf_chipname(bus->ci->chip, chn, 8),
  3192. bus->ci->chiprev, bus->ci->pmurev);
  3193. break;
  3194. }
  3195. if (str_tab != NULL) {
  3196. u32 drivestrength_sel = 0;
  3197. u32 cc_data_temp;
  3198. int i;
  3199. for (i = 0; str_tab[i].strength != 0; i++) {
  3200. if (drivestrength >= str_tab[i].strength) {
  3201. drivestrength_sel = str_tab[i].sel;
  3202. break;
  3203. }
  3204. }
  3205. brcmf_sdcard_reg_write(bus->sdiodev,
  3206. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
  3207. 4, 1);
  3208. cc_data_temp = brcmf_sdcard_reg_read(bus->sdiodev,
  3209. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr), 4);
  3210. cc_data_temp &= ~str_mask;
  3211. drivestrength_sel <<= str_shift;
  3212. cc_data_temp |= drivestrength_sel;
  3213. brcmf_sdcard_reg_write(bus->sdiodev,
  3214. CORE_CC_REG(bus->ci->cccorebase, chipcontrol_addr),
  3215. 4, cc_data_temp);
  3216. brcmf_dbg(INFO, "SDIO: %dmA drive strength selected, set to 0x%08x\n",
  3217. drivestrength, cc_data_temp);
  3218. }
  3219. }
  3220. static bool
  3221. brcmf_sdbrcm_probe_attach(struct brcmf_bus *bus, u32 regsva)
  3222. {
  3223. u8 clkctl = 0;
  3224. int err = 0;
  3225. int reg_addr;
  3226. u32 reg_val;
  3227. bus->alp_only = true;
  3228. /* Return the window to backplane enumeration space for core access */
  3229. if (brcmf_sdcard_set_sbaddr_window(bus->sdiodev, SI_ENUM_BASE))
  3230. brcmf_dbg(ERROR, "FAILED to return to SI_ENUM_BASE\n");
  3231. #ifdef BCMDBG
  3232. printk(KERN_DEBUG "F1 signature read @0x18000000=0x%4x\n",
  3233. brcmf_sdcard_reg_read(bus->sdiodev, SI_ENUM_BASE, 4));
  3234. #endif /* BCMDBG */
  3235. /*
  3236. * Force PLL off until brcmf_sdio_chip_attach()
  3237. * programs PLL control regs
  3238. */
  3239. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3240. SBSDIO_FUNC1_CHIPCLKCSR,
  3241. BRCMF_INIT_CLKCTL1, &err);
  3242. if (!err)
  3243. clkctl =
  3244. brcmf_sdcard_cfg_read(bus->sdiodev, SDIO_FUNC_1,
  3245. SBSDIO_FUNC1_CHIPCLKCSR, &err);
  3246. if (err || ((clkctl & ~SBSDIO_AVBITS) != BRCMF_INIT_CLKCTL1)) {
  3247. brcmf_dbg(ERROR, "ChipClkCSR access: err %d wrote 0x%02x read 0x%02x\n",
  3248. err, BRCMF_INIT_CLKCTL1, clkctl);
  3249. goto fail;
  3250. }
  3251. if (brcmf_sdio_chip_attach(bus->sdiodev, &bus->ci, regsva)) {
  3252. brcmf_dbg(ERROR, "brcmf_sdio_chip_attach failed!\n");
  3253. goto fail;
  3254. }
  3255. if (!brcmf_sdbrcm_chipmatch((u16) bus->ci->chip)) {
  3256. brcmf_dbg(ERROR, "unsupported chip: 0x%04x\n", bus->ci->chip);
  3257. goto fail;
  3258. }
  3259. brcmf_sdbrcm_sdiod_drive_strength_init(bus, SDIO_DRIVE_STRENGTH);
  3260. /* Get info on the SOCRAM cores... */
  3261. bus->ramsize = bus->ci->ramsize;
  3262. if (!(bus->ramsize)) {
  3263. brcmf_dbg(ERROR, "failed to find SOCRAM memory!\n");
  3264. goto fail;
  3265. }
  3266. /* Set core control so an SDIO reset does a backplane reset */
  3267. reg_addr = bus->ci->buscorebase +
  3268. offsetof(struct sdpcmd_regs, corecontrol);
  3269. reg_val = brcmf_sdcard_reg_read(bus->sdiodev, reg_addr, sizeof(u32));
  3270. brcmf_sdcard_reg_write(bus->sdiodev, reg_addr, sizeof(u32),
  3271. reg_val | CC_BPRESEN);
  3272. brcmu_pktq_init(&bus->txq, (PRIOMASK + 1), TXQLEN);
  3273. /* Locate an appropriately-aligned portion of hdrbuf */
  3274. bus->rxhdr = (u8 *) roundup((unsigned long)&bus->hdrbuf[0],
  3275. BRCMF_SDALIGN);
  3276. /* Set the poll and/or interrupt flags */
  3277. bus->intr = true;
  3278. bus->poll = false;
  3279. if (bus->poll)
  3280. bus->pollrate = 1;
  3281. return true;
  3282. fail:
  3283. return false;
  3284. }
  3285. static bool brcmf_sdbrcm_probe_init(struct brcmf_bus *bus)
  3286. {
  3287. brcmf_dbg(TRACE, "Enter\n");
  3288. /* Disable F2 to clear any intermediate frame state on the dongle */
  3289. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_0, SDIO_CCCR_IOEx,
  3290. SDIO_FUNC_ENABLE_1, NULL);
  3291. bus->drvr->busstate = BRCMF_BUS_DOWN;
  3292. bus->sleeping = false;
  3293. bus->rxflow = false;
  3294. /* Done with backplane-dependent accesses, can drop clock... */
  3295. brcmf_sdcard_cfg_write(bus->sdiodev, SDIO_FUNC_1,
  3296. SBSDIO_FUNC1_CHIPCLKCSR, 0, NULL);
  3297. /* ...and initialize clock/power states */
  3298. bus->clkstate = CLK_SDONLY;
  3299. bus->idletime = BRCMF_IDLE_INTERVAL;
  3300. bus->idleclock = BRCMF_IDLE_ACTIVE;
  3301. /* Query the F2 block size, set roundup accordingly */
  3302. bus->blocksize = bus->sdiodev->func[2]->cur_blksize;
  3303. bus->roundup = min(max_roundup, bus->blocksize);
  3304. /* bus module does not support packet chaining */
  3305. bus->use_rxchain = false;
  3306. bus->sd_rxchain = false;
  3307. return true;
  3308. }
  3309. static int
  3310. brcmf_sdbrcm_watchdog_thread(void *data)
  3311. {
  3312. struct brcmf_bus *bus = (struct brcmf_bus *)data;
  3313. allow_signal(SIGTERM);
  3314. /* Run until signal received */
  3315. while (1) {
  3316. if (kthread_should_stop())
  3317. break;
  3318. if (!wait_for_completion_interruptible(&bus->watchdog_wait)) {
  3319. brcmf_sdbrcm_bus_watchdog(bus->drvr);
  3320. /* Count the tick for reference */
  3321. bus->drvr->tickcnt++;
  3322. } else
  3323. break;
  3324. }
  3325. return 0;
  3326. }
  3327. static void
  3328. brcmf_sdbrcm_watchdog(unsigned long data)
  3329. {
  3330. struct brcmf_bus *bus = (struct brcmf_bus *)data;
  3331. if (bus->watchdog_tsk) {
  3332. complete(&bus->watchdog_wait);
  3333. /* Reschedule the watchdog */
  3334. if (bus->wd_timer_valid)
  3335. mod_timer(&bus->timer,
  3336. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3337. }
  3338. }
  3339. static void
  3340. brcmf_sdbrcm_chip_detach(struct brcmf_bus *bus)
  3341. {
  3342. brcmf_dbg(TRACE, "Enter\n");
  3343. kfree(bus->ci);
  3344. bus->ci = NULL;
  3345. }
  3346. static void brcmf_sdbrcm_release_dongle(struct brcmf_bus *bus)
  3347. {
  3348. brcmf_dbg(TRACE, "Enter\n");
  3349. if (bus->ci) {
  3350. brcmf_sdbrcm_clkctl(bus, CLK_AVAIL, false);
  3351. brcmf_sdbrcm_clkctl(bus, CLK_NONE, false);
  3352. brcmf_sdbrcm_chip_detach(bus);
  3353. if (bus->vars && bus->varsz)
  3354. kfree(bus->vars);
  3355. bus->vars = NULL;
  3356. }
  3357. brcmf_dbg(TRACE, "Disconnected\n");
  3358. }
  3359. /* Detach and free everything */
  3360. static void brcmf_sdbrcm_release(struct brcmf_bus *bus)
  3361. {
  3362. brcmf_dbg(TRACE, "Enter\n");
  3363. if (bus) {
  3364. /* De-register interrupt handler */
  3365. brcmf_sdcard_intr_dereg(bus->sdiodev);
  3366. if (bus->drvr) {
  3367. brcmf_detach(bus->drvr);
  3368. brcmf_sdbrcm_release_dongle(bus);
  3369. bus->drvr = NULL;
  3370. }
  3371. brcmf_sdbrcm_release_malloc(bus);
  3372. kfree(bus);
  3373. }
  3374. brcmf_dbg(TRACE, "Disconnected\n");
  3375. }
  3376. void *brcmf_sdbrcm_probe(u16 bus_no, u16 slot, u16 func, uint bustype,
  3377. u32 regsva, struct brcmf_sdio_dev *sdiodev)
  3378. {
  3379. int ret;
  3380. struct brcmf_bus *bus;
  3381. /* Init global variables at run-time, not as part of the declaration.
  3382. * This is required to support init/de-init of the driver.
  3383. * Initialization
  3384. * of globals as part of the declaration results in non-deterministic
  3385. * behavior since the value of the globals may be different on the
  3386. * first time that the driver is initialized vs subsequent
  3387. * initializations.
  3388. */
  3389. brcmf_c_init();
  3390. brcmf_dbg(TRACE, "Enter\n");
  3391. /* We make an assumption about address window mappings:
  3392. * regsva == SI_ENUM_BASE*/
  3393. /* Allocate private bus interface state */
  3394. bus = kzalloc(sizeof(struct brcmf_bus), GFP_ATOMIC);
  3395. if (!bus)
  3396. goto fail;
  3397. bus->sdiodev = sdiodev;
  3398. sdiodev->bus = bus;
  3399. skb_queue_head_init(&bus->glom);
  3400. bus->txbound = BRCMF_TXBOUND;
  3401. bus->rxbound = BRCMF_RXBOUND;
  3402. bus->txminmax = BRCMF_TXMINMAX;
  3403. bus->tx_seq = SDPCM_SEQUENCE_WRAP - 1;
  3404. bus->usebufpool = false; /* Use bufpool if allocated,
  3405. else use locally malloced rxbuf */
  3406. /* attempt to attach to the dongle */
  3407. if (!(brcmf_sdbrcm_probe_attach(bus, regsva))) {
  3408. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_attach failed\n");
  3409. goto fail;
  3410. }
  3411. spin_lock_init(&bus->txqlock);
  3412. init_waitqueue_head(&bus->ctrl_wait);
  3413. init_waitqueue_head(&bus->dcmd_resp_wait);
  3414. /* Set up the watchdog timer */
  3415. init_timer(&bus->timer);
  3416. bus->timer.data = (unsigned long)bus;
  3417. bus->timer.function = brcmf_sdbrcm_watchdog;
  3418. /* Initialize thread based operation and lock */
  3419. sema_init(&bus->sdsem, 1);
  3420. /* Initialize watchdog thread */
  3421. init_completion(&bus->watchdog_wait);
  3422. bus->watchdog_tsk = kthread_run(brcmf_sdbrcm_watchdog_thread,
  3423. bus, "brcmf_watchdog");
  3424. if (IS_ERR(bus->watchdog_tsk)) {
  3425. printk(KERN_WARNING
  3426. "brcmf_watchdog thread failed to start\n");
  3427. bus->watchdog_tsk = NULL;
  3428. }
  3429. /* Initialize DPC thread */
  3430. init_completion(&bus->dpc_wait);
  3431. bus->dpc_tsk = kthread_run(brcmf_sdbrcm_dpc_thread,
  3432. bus, "brcmf_dpc");
  3433. if (IS_ERR(bus->dpc_tsk)) {
  3434. printk(KERN_WARNING
  3435. "brcmf_dpc thread failed to start\n");
  3436. bus->dpc_tsk = NULL;
  3437. }
  3438. /* Attach to the brcmf/OS/network interface */
  3439. bus->drvr = brcmf_attach(bus, SDPCM_RESERVE);
  3440. if (!bus->drvr) {
  3441. brcmf_dbg(ERROR, "brcmf_attach failed\n");
  3442. goto fail;
  3443. }
  3444. /* Allocate buffers */
  3445. if (!(brcmf_sdbrcm_probe_malloc(bus))) {
  3446. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_malloc failed\n");
  3447. goto fail;
  3448. }
  3449. if (!(brcmf_sdbrcm_probe_init(bus))) {
  3450. brcmf_dbg(ERROR, "brcmf_sdbrcm_probe_init failed\n");
  3451. goto fail;
  3452. }
  3453. /* Register interrupt callback, but mask it (not operational yet). */
  3454. brcmf_dbg(INTR, "disable SDIO interrupts (not interested yet)\n");
  3455. ret = brcmf_sdcard_intr_reg(bus->sdiodev);
  3456. if (ret != 0) {
  3457. brcmf_dbg(ERROR, "FAILED: sdcard_intr_reg returned %d\n", ret);
  3458. goto fail;
  3459. }
  3460. brcmf_dbg(INTR, "registered SDIO interrupt function ok\n");
  3461. brcmf_dbg(INFO, "completed!!\n");
  3462. /* if firmware path present try to download and bring up bus */
  3463. ret = brcmf_bus_start(bus->drvr);
  3464. if (ret != 0) {
  3465. if (ret == -ENOLINK) {
  3466. brcmf_dbg(ERROR, "dongle is not responding\n");
  3467. goto fail;
  3468. }
  3469. }
  3470. /* add interface and open for business */
  3471. if (brcmf_add_if((struct brcmf_info *)bus->drvr, 0, "wlan%d", NULL)) {
  3472. brcmf_dbg(ERROR, "Add primary net device interface failed!!\n");
  3473. goto fail;
  3474. }
  3475. return bus;
  3476. fail:
  3477. brcmf_sdbrcm_release(bus);
  3478. return NULL;
  3479. }
  3480. void brcmf_sdbrcm_disconnect(void *ptr)
  3481. {
  3482. struct brcmf_bus *bus = (struct brcmf_bus *)ptr;
  3483. brcmf_dbg(TRACE, "Enter\n");
  3484. if (bus)
  3485. brcmf_sdbrcm_release(bus);
  3486. brcmf_dbg(TRACE, "Disconnected\n");
  3487. }
  3488. struct device *brcmf_bus_get_device(struct brcmf_bus *bus)
  3489. {
  3490. return &bus->sdiodev->func[2]->dev;
  3491. }
  3492. void
  3493. brcmf_sdbrcm_wd_timer(struct brcmf_bus *bus, uint wdtick)
  3494. {
  3495. /* Totally stop the timer */
  3496. if (!wdtick && bus->wd_timer_valid == true) {
  3497. del_timer_sync(&bus->timer);
  3498. bus->wd_timer_valid = false;
  3499. bus->save_ms = wdtick;
  3500. return;
  3501. }
  3502. /* don't start the wd until fw is loaded */
  3503. if (bus->drvr->busstate == BRCMF_BUS_DOWN)
  3504. return;
  3505. if (wdtick) {
  3506. if (bus->save_ms != BRCMF_WD_POLL_MS) {
  3507. if (bus->wd_timer_valid == true)
  3508. /* Stop timer and restart at new value */
  3509. del_timer_sync(&bus->timer);
  3510. /* Create timer again when watchdog period is
  3511. dynamically changed or in the first instance
  3512. */
  3513. bus->timer.expires =
  3514. jiffies + BRCMF_WD_POLL_MS * HZ / 1000;
  3515. add_timer(&bus->timer);
  3516. } else {
  3517. /* Re arm the timer, at last watchdog period */
  3518. mod_timer(&bus->timer,
  3519. jiffies + BRCMF_WD_POLL_MS * HZ / 1000);
  3520. }
  3521. bus->wd_timer_valid = true;
  3522. bus->save_ms = wdtick;
  3523. }
  3524. }