resource_tracker.c 68 KB

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  1. /*
  2. * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved.
  3. * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies.
  4. * All rights reserved.
  5. * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved.
  6. *
  7. * This software is available to you under a choice of one of two
  8. * licenses. You may choose to be licensed under the terms of the GNU
  9. * General Public License (GPL) Version 2, available from the file
  10. * COPYING in the main directory of this source tree, or the
  11. * OpenIB.org BSD license below:
  12. *
  13. * Redistribution and use in source and binary forms, with or
  14. * without modification, are permitted provided that the following
  15. * conditions are met:
  16. *
  17. * - Redistributions of source code must retain the above
  18. * copyright notice, this list of conditions and the following
  19. * disclaimer.
  20. *
  21. * - Redistributions in binary form must reproduce the above
  22. * copyright notice, this list of conditions and the following
  23. * disclaimer in the documentation and/or other materials
  24. * provided with the distribution.
  25. *
  26. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  27. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  28. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  29. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  30. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  31. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  32. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  33. * SOFTWARE.
  34. */
  35. #include <linux/sched.h>
  36. #include <linux/pci.h>
  37. #include <linux/errno.h>
  38. #include <linux/kernel.h>
  39. #include <linux/io.h>
  40. #include <linux/mlx4/cmd.h>
  41. #include <linux/mlx4/qp.h>
  42. #include "mlx4.h"
  43. #include "fw.h"
  44. #define MLX4_MAC_VALID (1ull << 63)
  45. #define MLX4_MAC_MASK 0x7fffffffffffffffULL
  46. #define ETH_ALEN 6
  47. struct mac_res {
  48. struct list_head list;
  49. u64 mac;
  50. u8 port;
  51. };
  52. struct res_common {
  53. struct list_head list;
  54. u32 res_id;
  55. int owner;
  56. int state;
  57. int from_state;
  58. int to_state;
  59. int removing;
  60. };
  61. enum {
  62. RES_ANY_BUSY = 1
  63. };
  64. struct res_gid {
  65. struct list_head list;
  66. u8 gid[16];
  67. enum mlx4_protocol prot;
  68. };
  69. enum res_qp_states {
  70. RES_QP_BUSY = RES_ANY_BUSY,
  71. /* QP number was allocated */
  72. RES_QP_RESERVED,
  73. /* ICM memory for QP context was mapped */
  74. RES_QP_MAPPED,
  75. /* QP is in hw ownership */
  76. RES_QP_HW
  77. };
  78. static inline const char *qp_states_str(enum res_qp_states state)
  79. {
  80. switch (state) {
  81. case RES_QP_BUSY: return "RES_QP_BUSY";
  82. case RES_QP_RESERVED: return "RES_QP_RESERVED";
  83. case RES_QP_MAPPED: return "RES_QP_MAPPED";
  84. case RES_QP_HW: return "RES_QP_HW";
  85. default: return "Unknown";
  86. }
  87. }
  88. struct res_qp {
  89. struct res_common com;
  90. struct res_mtt *mtt;
  91. struct res_cq *rcq;
  92. struct res_cq *scq;
  93. struct res_srq *srq;
  94. struct list_head mcg_list;
  95. spinlock_t mcg_spl;
  96. int local_qpn;
  97. };
  98. enum res_mtt_states {
  99. RES_MTT_BUSY = RES_ANY_BUSY,
  100. RES_MTT_ALLOCATED,
  101. };
  102. static inline const char *mtt_states_str(enum res_mtt_states state)
  103. {
  104. switch (state) {
  105. case RES_MTT_BUSY: return "RES_MTT_BUSY";
  106. case RES_MTT_ALLOCATED: return "RES_MTT_ALLOCATED";
  107. default: return "Unknown";
  108. }
  109. }
  110. struct res_mtt {
  111. struct res_common com;
  112. int order;
  113. atomic_t ref_count;
  114. };
  115. enum res_mpt_states {
  116. RES_MPT_BUSY = RES_ANY_BUSY,
  117. RES_MPT_RESERVED,
  118. RES_MPT_MAPPED,
  119. RES_MPT_HW,
  120. };
  121. struct res_mpt {
  122. struct res_common com;
  123. struct res_mtt *mtt;
  124. int key;
  125. };
  126. enum res_eq_states {
  127. RES_EQ_BUSY = RES_ANY_BUSY,
  128. RES_EQ_RESERVED,
  129. RES_EQ_HW,
  130. };
  131. struct res_eq {
  132. struct res_common com;
  133. struct res_mtt *mtt;
  134. };
  135. enum res_cq_states {
  136. RES_CQ_BUSY = RES_ANY_BUSY,
  137. RES_CQ_ALLOCATED,
  138. RES_CQ_HW,
  139. };
  140. struct res_cq {
  141. struct res_common com;
  142. struct res_mtt *mtt;
  143. atomic_t ref_count;
  144. };
  145. enum res_srq_states {
  146. RES_SRQ_BUSY = RES_ANY_BUSY,
  147. RES_SRQ_ALLOCATED,
  148. RES_SRQ_HW,
  149. };
  150. static inline const char *srq_states_str(enum res_srq_states state)
  151. {
  152. switch (state) {
  153. case RES_SRQ_BUSY: return "RES_SRQ_BUSY";
  154. case RES_SRQ_ALLOCATED: return "RES_SRQ_ALLOCATED";
  155. case RES_SRQ_HW: return "RES_SRQ_HW";
  156. default: return "Unknown";
  157. }
  158. }
  159. struct res_srq {
  160. struct res_common com;
  161. struct res_mtt *mtt;
  162. struct res_cq *cq;
  163. atomic_t ref_count;
  164. };
  165. enum res_counter_states {
  166. RES_COUNTER_BUSY = RES_ANY_BUSY,
  167. RES_COUNTER_ALLOCATED,
  168. };
  169. static inline const char *counter_states_str(enum res_counter_states state)
  170. {
  171. switch (state) {
  172. case RES_COUNTER_BUSY: return "RES_COUNTER_BUSY";
  173. case RES_COUNTER_ALLOCATED: return "RES_COUNTER_ALLOCATED";
  174. default: return "Unknown";
  175. }
  176. }
  177. struct res_counter {
  178. struct res_common com;
  179. int port;
  180. };
  181. /* For Debug uses */
  182. static const char *ResourceType(enum mlx4_resource rt)
  183. {
  184. switch (rt) {
  185. case RES_QP: return "RES_QP";
  186. case RES_CQ: return "RES_CQ";
  187. case RES_SRQ: return "RES_SRQ";
  188. case RES_MPT: return "RES_MPT";
  189. case RES_MTT: return "RES_MTT";
  190. case RES_MAC: return "RES_MAC";
  191. case RES_EQ: return "RES_EQ";
  192. case RES_COUNTER: return "RES_COUNTER";
  193. default: return "Unknown resource type !!!";
  194. };
  195. }
  196. int mlx4_init_resource_tracker(struct mlx4_dev *dev)
  197. {
  198. struct mlx4_priv *priv = mlx4_priv(dev);
  199. int i;
  200. int t;
  201. priv->mfunc.master.res_tracker.slave_list =
  202. kzalloc(dev->num_slaves * sizeof(struct slave_list),
  203. GFP_KERNEL);
  204. if (!priv->mfunc.master.res_tracker.slave_list)
  205. return -ENOMEM;
  206. for (i = 0 ; i < dev->num_slaves; i++) {
  207. for (t = 0; t < MLX4_NUM_OF_RESOURCE_TYPE; ++t)
  208. INIT_LIST_HEAD(&priv->mfunc.master.res_tracker.
  209. slave_list[i].res_list[t]);
  210. mutex_init(&priv->mfunc.master.res_tracker.slave_list[i].mutex);
  211. }
  212. mlx4_dbg(dev, "Started init_resource_tracker: %ld slaves\n",
  213. dev->num_slaves);
  214. for (i = 0 ; i < MLX4_NUM_OF_RESOURCE_TYPE; i++)
  215. INIT_RADIX_TREE(&priv->mfunc.master.res_tracker.res_tree[i],
  216. GFP_ATOMIC|__GFP_NOWARN);
  217. spin_lock_init(&priv->mfunc.master.res_tracker.lock);
  218. return 0 ;
  219. }
  220. void mlx4_free_resource_tracker(struct mlx4_dev *dev)
  221. {
  222. struct mlx4_priv *priv = mlx4_priv(dev);
  223. int i;
  224. if (priv->mfunc.master.res_tracker.slave_list) {
  225. for (i = 0 ; i < dev->num_slaves; i++)
  226. mlx4_delete_all_resources_for_slave(dev, i);
  227. kfree(priv->mfunc.master.res_tracker.slave_list);
  228. }
  229. }
  230. static void update_ud_gid(struct mlx4_dev *dev,
  231. struct mlx4_qp_context *qp_ctx, u8 slave)
  232. {
  233. u32 ts = (be32_to_cpu(qp_ctx->flags) >> 16) & 0xff;
  234. if (MLX4_QP_ST_UD == ts)
  235. qp_ctx->pri_path.mgid_index = 0x80 | slave;
  236. mlx4_dbg(dev, "slave %d, new gid index: 0x%x ",
  237. slave, qp_ctx->pri_path.mgid_index);
  238. }
  239. static int mpt_mask(struct mlx4_dev *dev)
  240. {
  241. return dev->caps.num_mpts - 1;
  242. }
  243. static void *find_res(struct mlx4_dev *dev, int res_id,
  244. enum mlx4_resource type)
  245. {
  246. struct mlx4_priv *priv = mlx4_priv(dev);
  247. return radix_tree_lookup(&priv->mfunc.master.res_tracker.res_tree[type],
  248. res_id);
  249. }
  250. static int get_res(struct mlx4_dev *dev, int slave, int res_id,
  251. enum mlx4_resource type,
  252. void *res)
  253. {
  254. struct res_common *r;
  255. int err = 0;
  256. spin_lock_irq(mlx4_tlock(dev));
  257. r = find_res(dev, res_id, type);
  258. if (!r) {
  259. err = -ENONET;
  260. goto exit;
  261. }
  262. if (r->state == RES_ANY_BUSY) {
  263. err = -EBUSY;
  264. goto exit;
  265. }
  266. if (r->owner != slave) {
  267. err = -EPERM;
  268. goto exit;
  269. }
  270. r->from_state = r->state;
  271. r->state = RES_ANY_BUSY;
  272. mlx4_dbg(dev, "res %s id 0x%x to busy\n",
  273. ResourceType(type), r->res_id);
  274. if (res)
  275. *((struct res_common **)res) = r;
  276. exit:
  277. spin_unlock_irq(mlx4_tlock(dev));
  278. return err;
  279. }
  280. int mlx4_get_slave_from_resource_id(struct mlx4_dev *dev,
  281. enum mlx4_resource type,
  282. int res_id, int *slave)
  283. {
  284. struct res_common *r;
  285. int err = -ENOENT;
  286. int id = res_id;
  287. if (type == RES_QP)
  288. id &= 0x7fffff;
  289. spin_lock_irq(mlx4_tlock(dev));
  290. r = find_res(dev, id, type);
  291. if (r) {
  292. *slave = r->owner;
  293. err = 0;
  294. }
  295. spin_unlock_irq(mlx4_tlock(dev));
  296. return err;
  297. }
  298. static void put_res(struct mlx4_dev *dev, int slave, int res_id,
  299. enum mlx4_resource type)
  300. {
  301. struct res_common *r;
  302. spin_lock_irq(mlx4_tlock(dev));
  303. r = find_res(dev, res_id, type);
  304. if (r)
  305. r->state = r->from_state;
  306. spin_unlock_irq(mlx4_tlock(dev));
  307. }
  308. static struct res_common *alloc_qp_tr(int id)
  309. {
  310. struct res_qp *ret;
  311. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  312. if (!ret)
  313. return NULL;
  314. ret->com.res_id = id;
  315. ret->com.state = RES_QP_RESERVED;
  316. INIT_LIST_HEAD(&ret->mcg_list);
  317. spin_lock_init(&ret->mcg_spl);
  318. return &ret->com;
  319. }
  320. static struct res_common *alloc_mtt_tr(int id, int order)
  321. {
  322. struct res_mtt *ret;
  323. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  324. if (!ret)
  325. return NULL;
  326. ret->com.res_id = id;
  327. ret->order = order;
  328. ret->com.state = RES_MTT_ALLOCATED;
  329. atomic_set(&ret->ref_count, 0);
  330. return &ret->com;
  331. }
  332. static struct res_common *alloc_mpt_tr(int id, int key)
  333. {
  334. struct res_mpt *ret;
  335. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  336. if (!ret)
  337. return NULL;
  338. ret->com.res_id = id;
  339. ret->com.state = RES_MPT_RESERVED;
  340. ret->key = key;
  341. return &ret->com;
  342. }
  343. static struct res_common *alloc_eq_tr(int id)
  344. {
  345. struct res_eq *ret;
  346. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  347. if (!ret)
  348. return NULL;
  349. ret->com.res_id = id;
  350. ret->com.state = RES_EQ_RESERVED;
  351. return &ret->com;
  352. }
  353. static struct res_common *alloc_cq_tr(int id)
  354. {
  355. struct res_cq *ret;
  356. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  357. if (!ret)
  358. return NULL;
  359. ret->com.res_id = id;
  360. ret->com.state = RES_CQ_ALLOCATED;
  361. atomic_set(&ret->ref_count, 0);
  362. return &ret->com;
  363. }
  364. static struct res_common *alloc_srq_tr(int id)
  365. {
  366. struct res_srq *ret;
  367. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  368. if (!ret)
  369. return NULL;
  370. ret->com.res_id = id;
  371. ret->com.state = RES_SRQ_ALLOCATED;
  372. atomic_set(&ret->ref_count, 0);
  373. return &ret->com;
  374. }
  375. static struct res_common *alloc_counter_tr(int id)
  376. {
  377. struct res_counter *ret;
  378. ret = kzalloc(sizeof *ret, GFP_KERNEL);
  379. if (!ret)
  380. return NULL;
  381. ret->com.res_id = id;
  382. ret->com.state = RES_COUNTER_ALLOCATED;
  383. return &ret->com;
  384. }
  385. static struct res_common *alloc_tr(int id, enum mlx4_resource type, int slave,
  386. int extra)
  387. {
  388. struct res_common *ret;
  389. switch (type) {
  390. case RES_QP:
  391. ret = alloc_qp_tr(id);
  392. break;
  393. case RES_MPT:
  394. ret = alloc_mpt_tr(id, extra);
  395. break;
  396. case RES_MTT:
  397. ret = alloc_mtt_tr(id, extra);
  398. break;
  399. case RES_EQ:
  400. ret = alloc_eq_tr(id);
  401. break;
  402. case RES_CQ:
  403. ret = alloc_cq_tr(id);
  404. break;
  405. case RES_SRQ:
  406. ret = alloc_srq_tr(id);
  407. break;
  408. case RES_MAC:
  409. printk(KERN_ERR "implementation missing\n");
  410. return NULL;
  411. case RES_COUNTER:
  412. ret = alloc_counter_tr(id);
  413. break;
  414. default:
  415. return NULL;
  416. }
  417. if (ret)
  418. ret->owner = slave;
  419. return ret;
  420. }
  421. static int add_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  422. enum mlx4_resource type, int extra)
  423. {
  424. int i;
  425. int err;
  426. struct mlx4_priv *priv = mlx4_priv(dev);
  427. struct res_common **res_arr;
  428. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  429. struct radix_tree_root *root = &tracker->res_tree[type];
  430. res_arr = kzalloc(count * sizeof *res_arr, GFP_KERNEL);
  431. if (!res_arr)
  432. return -ENOMEM;
  433. for (i = 0; i < count; ++i) {
  434. res_arr[i] = alloc_tr(base + i, type, slave, extra);
  435. if (!res_arr[i]) {
  436. for (--i; i >= 0; --i)
  437. kfree(res_arr[i]);
  438. kfree(res_arr);
  439. return -ENOMEM;
  440. }
  441. }
  442. spin_lock_irq(mlx4_tlock(dev));
  443. for (i = 0; i < count; ++i) {
  444. if (find_res(dev, base + i, type)) {
  445. err = -EEXIST;
  446. goto undo;
  447. }
  448. err = radix_tree_insert(root, base + i, res_arr[i]);
  449. if (err)
  450. goto undo;
  451. list_add_tail(&res_arr[i]->list,
  452. &tracker->slave_list[slave].res_list[type]);
  453. }
  454. spin_unlock_irq(mlx4_tlock(dev));
  455. kfree(res_arr);
  456. return 0;
  457. undo:
  458. for (--i; i >= base; --i)
  459. radix_tree_delete(&tracker->res_tree[type], i);
  460. spin_unlock_irq(mlx4_tlock(dev));
  461. for (i = 0; i < count; ++i)
  462. kfree(res_arr[i]);
  463. kfree(res_arr);
  464. return err;
  465. }
  466. static int remove_qp_ok(struct res_qp *res)
  467. {
  468. if (res->com.state == RES_QP_BUSY)
  469. return -EBUSY;
  470. else if (res->com.state != RES_QP_RESERVED)
  471. return -EPERM;
  472. return 0;
  473. }
  474. static int remove_mtt_ok(struct res_mtt *res, int order)
  475. {
  476. if (res->com.state == RES_MTT_BUSY ||
  477. atomic_read(&res->ref_count)) {
  478. printk(KERN_DEBUG "%s-%d: state %s, ref_count %d\n",
  479. __func__, __LINE__,
  480. mtt_states_str(res->com.state),
  481. atomic_read(&res->ref_count));
  482. return -EBUSY;
  483. } else if (res->com.state != RES_MTT_ALLOCATED)
  484. return -EPERM;
  485. else if (res->order != order)
  486. return -EINVAL;
  487. return 0;
  488. }
  489. static int remove_mpt_ok(struct res_mpt *res)
  490. {
  491. if (res->com.state == RES_MPT_BUSY)
  492. return -EBUSY;
  493. else if (res->com.state != RES_MPT_RESERVED)
  494. return -EPERM;
  495. return 0;
  496. }
  497. static int remove_eq_ok(struct res_eq *res)
  498. {
  499. if (res->com.state == RES_MPT_BUSY)
  500. return -EBUSY;
  501. else if (res->com.state != RES_MPT_RESERVED)
  502. return -EPERM;
  503. return 0;
  504. }
  505. static int remove_counter_ok(struct res_counter *res)
  506. {
  507. if (res->com.state == RES_COUNTER_BUSY)
  508. return -EBUSY;
  509. else if (res->com.state != RES_COUNTER_ALLOCATED)
  510. return -EPERM;
  511. return 0;
  512. }
  513. static int remove_cq_ok(struct res_cq *res)
  514. {
  515. if (res->com.state == RES_CQ_BUSY)
  516. return -EBUSY;
  517. else if (res->com.state != RES_CQ_ALLOCATED)
  518. return -EPERM;
  519. return 0;
  520. }
  521. static int remove_srq_ok(struct res_srq *res)
  522. {
  523. if (res->com.state == RES_SRQ_BUSY)
  524. return -EBUSY;
  525. else if (res->com.state != RES_SRQ_ALLOCATED)
  526. return -EPERM;
  527. return 0;
  528. }
  529. static int remove_ok(struct res_common *res, enum mlx4_resource type, int extra)
  530. {
  531. switch (type) {
  532. case RES_QP:
  533. return remove_qp_ok((struct res_qp *)res);
  534. case RES_CQ:
  535. return remove_cq_ok((struct res_cq *)res);
  536. case RES_SRQ:
  537. return remove_srq_ok((struct res_srq *)res);
  538. case RES_MPT:
  539. return remove_mpt_ok((struct res_mpt *)res);
  540. case RES_MTT:
  541. return remove_mtt_ok((struct res_mtt *)res, extra);
  542. case RES_MAC:
  543. return -ENOSYS;
  544. case RES_EQ:
  545. return remove_eq_ok((struct res_eq *)res);
  546. case RES_COUNTER:
  547. return remove_counter_ok((struct res_counter *)res);
  548. default:
  549. return -EINVAL;
  550. }
  551. }
  552. static int rem_res_range(struct mlx4_dev *dev, int slave, int base, int count,
  553. enum mlx4_resource type, int extra)
  554. {
  555. int i;
  556. int err;
  557. struct mlx4_priv *priv = mlx4_priv(dev);
  558. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  559. struct res_common *r;
  560. spin_lock_irq(mlx4_tlock(dev));
  561. for (i = base; i < base + count; ++i) {
  562. r = radix_tree_lookup(&tracker->res_tree[type], i);
  563. if (!r) {
  564. err = -ENOENT;
  565. goto out;
  566. }
  567. if (r->owner != slave) {
  568. err = -EPERM;
  569. goto out;
  570. }
  571. err = remove_ok(r, type, extra);
  572. if (err)
  573. goto out;
  574. }
  575. for (i = base; i < base + count; ++i) {
  576. r = radix_tree_lookup(&tracker->res_tree[type], i);
  577. radix_tree_delete(&tracker->res_tree[type], i);
  578. list_del(&r->list);
  579. kfree(r);
  580. }
  581. err = 0;
  582. out:
  583. spin_unlock_irq(mlx4_tlock(dev));
  584. return err;
  585. }
  586. static int qp_res_start_move_to(struct mlx4_dev *dev, int slave, int qpn,
  587. enum res_qp_states state, struct res_qp **qp,
  588. int alloc)
  589. {
  590. struct mlx4_priv *priv = mlx4_priv(dev);
  591. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  592. struct res_qp *r;
  593. int err = 0;
  594. spin_lock_irq(mlx4_tlock(dev));
  595. r = radix_tree_lookup(&tracker->res_tree[RES_QP], qpn);
  596. if (!r)
  597. err = -ENOENT;
  598. else if (r->com.owner != slave)
  599. err = -EPERM;
  600. else {
  601. switch (state) {
  602. case RES_QP_BUSY:
  603. mlx4_dbg(dev, "%s: failed RES_QP, 0x%x\n",
  604. __func__, r->com.res_id);
  605. err = -EBUSY;
  606. break;
  607. case RES_QP_RESERVED:
  608. if (r->com.state == RES_QP_MAPPED && !alloc)
  609. break;
  610. mlx4_dbg(dev, "failed RES_QP, 0x%x\n", r->com.res_id);
  611. err = -EINVAL;
  612. break;
  613. case RES_QP_MAPPED:
  614. if ((r->com.state == RES_QP_RESERVED && alloc) ||
  615. r->com.state == RES_QP_HW)
  616. break;
  617. else {
  618. mlx4_dbg(dev, "failed RES_QP, 0x%x\n",
  619. r->com.res_id);
  620. err = -EINVAL;
  621. }
  622. break;
  623. case RES_QP_HW:
  624. if (r->com.state != RES_QP_MAPPED)
  625. err = -EINVAL;
  626. break;
  627. default:
  628. err = -EINVAL;
  629. }
  630. if (!err) {
  631. r->com.from_state = r->com.state;
  632. r->com.to_state = state;
  633. r->com.state = RES_QP_BUSY;
  634. if (qp)
  635. *qp = (struct res_qp *)r;
  636. }
  637. }
  638. spin_unlock_irq(mlx4_tlock(dev));
  639. return err;
  640. }
  641. static int mr_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  642. enum res_mpt_states state, struct res_mpt **mpt)
  643. {
  644. struct mlx4_priv *priv = mlx4_priv(dev);
  645. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  646. struct res_mpt *r;
  647. int err = 0;
  648. spin_lock_irq(mlx4_tlock(dev));
  649. r = radix_tree_lookup(&tracker->res_tree[RES_MPT], index);
  650. if (!r)
  651. err = -ENOENT;
  652. else if (r->com.owner != slave)
  653. err = -EPERM;
  654. else {
  655. switch (state) {
  656. case RES_MPT_BUSY:
  657. err = -EINVAL;
  658. break;
  659. case RES_MPT_RESERVED:
  660. if (r->com.state != RES_MPT_MAPPED)
  661. err = -EINVAL;
  662. break;
  663. case RES_MPT_MAPPED:
  664. if (r->com.state != RES_MPT_RESERVED &&
  665. r->com.state != RES_MPT_HW)
  666. err = -EINVAL;
  667. break;
  668. case RES_MPT_HW:
  669. if (r->com.state != RES_MPT_MAPPED)
  670. err = -EINVAL;
  671. break;
  672. default:
  673. err = -EINVAL;
  674. }
  675. if (!err) {
  676. r->com.from_state = r->com.state;
  677. r->com.to_state = state;
  678. r->com.state = RES_MPT_BUSY;
  679. if (mpt)
  680. *mpt = (struct res_mpt *)r;
  681. }
  682. }
  683. spin_unlock_irq(mlx4_tlock(dev));
  684. return err;
  685. }
  686. static int eq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  687. enum res_eq_states state, struct res_eq **eq)
  688. {
  689. struct mlx4_priv *priv = mlx4_priv(dev);
  690. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  691. struct res_eq *r;
  692. int err = 0;
  693. spin_lock_irq(mlx4_tlock(dev));
  694. r = radix_tree_lookup(&tracker->res_tree[RES_EQ], index);
  695. if (!r)
  696. err = -ENOENT;
  697. else if (r->com.owner != slave)
  698. err = -EPERM;
  699. else {
  700. switch (state) {
  701. case RES_EQ_BUSY:
  702. err = -EINVAL;
  703. break;
  704. case RES_EQ_RESERVED:
  705. if (r->com.state != RES_EQ_HW)
  706. err = -EINVAL;
  707. break;
  708. case RES_EQ_HW:
  709. if (r->com.state != RES_EQ_RESERVED)
  710. err = -EINVAL;
  711. break;
  712. default:
  713. err = -EINVAL;
  714. }
  715. if (!err) {
  716. r->com.from_state = r->com.state;
  717. r->com.to_state = state;
  718. r->com.state = RES_EQ_BUSY;
  719. if (eq)
  720. *eq = r;
  721. }
  722. }
  723. spin_unlock_irq(mlx4_tlock(dev));
  724. return err;
  725. }
  726. static int cq_res_start_move_to(struct mlx4_dev *dev, int slave, int cqn,
  727. enum res_cq_states state, struct res_cq **cq)
  728. {
  729. struct mlx4_priv *priv = mlx4_priv(dev);
  730. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  731. struct res_cq *r;
  732. int err;
  733. spin_lock_irq(mlx4_tlock(dev));
  734. r = radix_tree_lookup(&tracker->res_tree[RES_CQ], cqn);
  735. if (!r)
  736. err = -ENOENT;
  737. else if (r->com.owner != slave)
  738. err = -EPERM;
  739. else {
  740. switch (state) {
  741. case RES_CQ_BUSY:
  742. err = -EBUSY;
  743. break;
  744. case RES_CQ_ALLOCATED:
  745. if (r->com.state != RES_CQ_HW)
  746. err = -EINVAL;
  747. else if (atomic_read(&r->ref_count))
  748. err = -EBUSY;
  749. else
  750. err = 0;
  751. break;
  752. case RES_CQ_HW:
  753. if (r->com.state != RES_CQ_ALLOCATED)
  754. err = -EINVAL;
  755. else
  756. err = 0;
  757. break;
  758. default:
  759. err = -EINVAL;
  760. }
  761. if (!err) {
  762. r->com.from_state = r->com.state;
  763. r->com.to_state = state;
  764. r->com.state = RES_CQ_BUSY;
  765. if (cq)
  766. *cq = r;
  767. }
  768. }
  769. spin_unlock_irq(mlx4_tlock(dev));
  770. return err;
  771. }
  772. static int srq_res_start_move_to(struct mlx4_dev *dev, int slave, int index,
  773. enum res_cq_states state, struct res_srq **srq)
  774. {
  775. struct mlx4_priv *priv = mlx4_priv(dev);
  776. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  777. struct res_srq *r;
  778. int err = 0;
  779. spin_lock_irq(mlx4_tlock(dev));
  780. r = radix_tree_lookup(&tracker->res_tree[RES_SRQ], index);
  781. if (!r)
  782. err = -ENOENT;
  783. else if (r->com.owner != slave)
  784. err = -EPERM;
  785. else {
  786. switch (state) {
  787. case RES_SRQ_BUSY:
  788. err = -EINVAL;
  789. break;
  790. case RES_SRQ_ALLOCATED:
  791. if (r->com.state != RES_SRQ_HW)
  792. err = -EINVAL;
  793. else if (atomic_read(&r->ref_count))
  794. err = -EBUSY;
  795. break;
  796. case RES_SRQ_HW:
  797. if (r->com.state != RES_SRQ_ALLOCATED)
  798. err = -EINVAL;
  799. break;
  800. default:
  801. err = -EINVAL;
  802. }
  803. if (!err) {
  804. r->com.from_state = r->com.state;
  805. r->com.to_state = state;
  806. r->com.state = RES_SRQ_BUSY;
  807. if (srq)
  808. *srq = r;
  809. }
  810. }
  811. spin_unlock_irq(mlx4_tlock(dev));
  812. return err;
  813. }
  814. static void res_abort_move(struct mlx4_dev *dev, int slave,
  815. enum mlx4_resource type, int id)
  816. {
  817. struct mlx4_priv *priv = mlx4_priv(dev);
  818. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  819. struct res_common *r;
  820. spin_lock_irq(mlx4_tlock(dev));
  821. r = radix_tree_lookup(&tracker->res_tree[type], id);
  822. if (r && (r->owner == slave))
  823. r->state = r->from_state;
  824. spin_unlock_irq(mlx4_tlock(dev));
  825. }
  826. static void res_end_move(struct mlx4_dev *dev, int slave,
  827. enum mlx4_resource type, int id)
  828. {
  829. struct mlx4_priv *priv = mlx4_priv(dev);
  830. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  831. struct res_common *r;
  832. spin_lock_irq(mlx4_tlock(dev));
  833. r = radix_tree_lookup(&tracker->res_tree[type], id);
  834. if (r && (r->owner == slave))
  835. r->state = r->to_state;
  836. spin_unlock_irq(mlx4_tlock(dev));
  837. }
  838. static int valid_reserved(struct mlx4_dev *dev, int slave, int qpn)
  839. {
  840. return mlx4_is_qp_reserved(dev, qpn);
  841. }
  842. static int qp_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  843. u64 in_param, u64 *out_param)
  844. {
  845. int err;
  846. int count;
  847. int align;
  848. int base;
  849. int qpn;
  850. switch (op) {
  851. case RES_OP_RESERVE:
  852. count = get_param_l(&in_param);
  853. align = get_param_h(&in_param);
  854. err = __mlx4_qp_reserve_range(dev, count, align, &base);
  855. if (err)
  856. return err;
  857. err = add_res_range(dev, slave, base, count, RES_QP, 0);
  858. if (err) {
  859. __mlx4_qp_release_range(dev, base, count);
  860. return err;
  861. }
  862. set_param_l(out_param, base);
  863. break;
  864. case RES_OP_MAP_ICM:
  865. qpn = get_param_l(&in_param) & 0x7fffff;
  866. if (valid_reserved(dev, slave, qpn)) {
  867. err = add_res_range(dev, slave, qpn, 1, RES_QP, 0);
  868. if (err)
  869. return err;
  870. }
  871. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED,
  872. NULL, 1);
  873. if (err)
  874. return err;
  875. if (!valid_reserved(dev, slave, qpn)) {
  876. err = __mlx4_qp_alloc_icm(dev, qpn);
  877. if (err) {
  878. res_abort_move(dev, slave, RES_QP, qpn);
  879. return err;
  880. }
  881. }
  882. res_end_move(dev, slave, RES_QP, qpn);
  883. break;
  884. default:
  885. err = -EINVAL;
  886. break;
  887. }
  888. return err;
  889. }
  890. static int mtt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  891. u64 in_param, u64 *out_param)
  892. {
  893. int err = -EINVAL;
  894. int base;
  895. int order;
  896. if (op != RES_OP_RESERVE_AND_MAP)
  897. return err;
  898. order = get_param_l(&in_param);
  899. base = __mlx4_alloc_mtt_range(dev, order);
  900. if (base == -1)
  901. return -ENOMEM;
  902. err = add_res_range(dev, slave, base, 1, RES_MTT, order);
  903. if (err)
  904. __mlx4_free_mtt_range(dev, base, order);
  905. else
  906. set_param_l(out_param, base);
  907. return err;
  908. }
  909. static int mpt_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  910. u64 in_param, u64 *out_param)
  911. {
  912. int err = -EINVAL;
  913. int index;
  914. int id;
  915. struct res_mpt *mpt;
  916. switch (op) {
  917. case RES_OP_RESERVE:
  918. index = __mlx4_mr_reserve(dev);
  919. if (index == -1)
  920. break;
  921. id = index & mpt_mask(dev);
  922. err = add_res_range(dev, slave, id, 1, RES_MPT, index);
  923. if (err) {
  924. __mlx4_mr_release(dev, index);
  925. break;
  926. }
  927. set_param_l(out_param, index);
  928. break;
  929. case RES_OP_MAP_ICM:
  930. index = get_param_l(&in_param);
  931. id = index & mpt_mask(dev);
  932. err = mr_res_start_move_to(dev, slave, id,
  933. RES_MPT_MAPPED, &mpt);
  934. if (err)
  935. return err;
  936. err = __mlx4_mr_alloc_icm(dev, mpt->key);
  937. if (err) {
  938. res_abort_move(dev, slave, RES_MPT, id);
  939. return err;
  940. }
  941. res_end_move(dev, slave, RES_MPT, id);
  942. break;
  943. }
  944. return err;
  945. }
  946. static int cq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  947. u64 in_param, u64 *out_param)
  948. {
  949. int cqn;
  950. int err;
  951. switch (op) {
  952. case RES_OP_RESERVE_AND_MAP:
  953. err = __mlx4_cq_alloc_icm(dev, &cqn);
  954. if (err)
  955. break;
  956. err = add_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  957. if (err) {
  958. __mlx4_cq_free_icm(dev, cqn);
  959. break;
  960. }
  961. set_param_l(out_param, cqn);
  962. break;
  963. default:
  964. err = -EINVAL;
  965. }
  966. return err;
  967. }
  968. static int srq_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  969. u64 in_param, u64 *out_param)
  970. {
  971. int srqn;
  972. int err;
  973. switch (op) {
  974. case RES_OP_RESERVE_AND_MAP:
  975. err = __mlx4_srq_alloc_icm(dev, &srqn);
  976. if (err)
  977. break;
  978. err = add_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  979. if (err) {
  980. __mlx4_srq_free_icm(dev, srqn);
  981. break;
  982. }
  983. set_param_l(out_param, srqn);
  984. break;
  985. default:
  986. err = -EINVAL;
  987. }
  988. return err;
  989. }
  990. static int mac_add_to_slave(struct mlx4_dev *dev, int slave, u64 mac, int port)
  991. {
  992. struct mlx4_priv *priv = mlx4_priv(dev);
  993. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  994. struct mac_res *res;
  995. res = kzalloc(sizeof *res, GFP_KERNEL);
  996. if (!res)
  997. return -ENOMEM;
  998. res->mac = mac;
  999. res->port = (u8) port;
  1000. list_add_tail(&res->list,
  1001. &tracker->slave_list[slave].res_list[RES_MAC]);
  1002. return 0;
  1003. }
  1004. static void mac_del_from_slave(struct mlx4_dev *dev, int slave, u64 mac,
  1005. int port)
  1006. {
  1007. struct mlx4_priv *priv = mlx4_priv(dev);
  1008. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1009. struct list_head *mac_list =
  1010. &tracker->slave_list[slave].res_list[RES_MAC];
  1011. struct mac_res *res, *tmp;
  1012. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1013. if (res->mac == mac && res->port == (u8) port) {
  1014. list_del(&res->list);
  1015. kfree(res);
  1016. break;
  1017. }
  1018. }
  1019. }
  1020. static void rem_slave_macs(struct mlx4_dev *dev, int slave)
  1021. {
  1022. struct mlx4_priv *priv = mlx4_priv(dev);
  1023. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1024. struct list_head *mac_list =
  1025. &tracker->slave_list[slave].res_list[RES_MAC];
  1026. struct mac_res *res, *tmp;
  1027. list_for_each_entry_safe(res, tmp, mac_list, list) {
  1028. list_del(&res->list);
  1029. __mlx4_unregister_mac(dev, res->port, res->mac);
  1030. kfree(res);
  1031. }
  1032. }
  1033. static int mac_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1034. u64 in_param, u64 *out_param)
  1035. {
  1036. int err = -EINVAL;
  1037. int port;
  1038. u64 mac;
  1039. if (op != RES_OP_RESERVE_AND_MAP)
  1040. return err;
  1041. port = get_param_l(out_param);
  1042. mac = in_param;
  1043. err = __mlx4_register_mac(dev, port, mac);
  1044. if (err >= 0) {
  1045. set_param_l(out_param, err);
  1046. err = 0;
  1047. }
  1048. if (!err) {
  1049. err = mac_add_to_slave(dev, slave, mac, port);
  1050. if (err)
  1051. __mlx4_unregister_mac(dev, port, mac);
  1052. }
  1053. return err;
  1054. }
  1055. static int vlan_alloc_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1056. u64 in_param, u64 *out_param)
  1057. {
  1058. return 0;
  1059. }
  1060. int mlx4_ALLOC_RES_wrapper(struct mlx4_dev *dev, int slave,
  1061. struct mlx4_vhcr *vhcr,
  1062. struct mlx4_cmd_mailbox *inbox,
  1063. struct mlx4_cmd_mailbox *outbox,
  1064. struct mlx4_cmd_info *cmd)
  1065. {
  1066. int err;
  1067. int alop = vhcr->op_modifier;
  1068. switch (vhcr->in_modifier) {
  1069. case RES_QP:
  1070. err = qp_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1071. vhcr->in_param, &vhcr->out_param);
  1072. break;
  1073. case RES_MTT:
  1074. err = mtt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1075. vhcr->in_param, &vhcr->out_param);
  1076. break;
  1077. case RES_MPT:
  1078. err = mpt_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1079. vhcr->in_param, &vhcr->out_param);
  1080. break;
  1081. case RES_CQ:
  1082. err = cq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1083. vhcr->in_param, &vhcr->out_param);
  1084. break;
  1085. case RES_SRQ:
  1086. err = srq_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1087. vhcr->in_param, &vhcr->out_param);
  1088. break;
  1089. case RES_MAC:
  1090. err = mac_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1091. vhcr->in_param, &vhcr->out_param);
  1092. break;
  1093. case RES_VLAN:
  1094. err = vlan_alloc_res(dev, slave, vhcr->op_modifier, alop,
  1095. vhcr->in_param, &vhcr->out_param);
  1096. break;
  1097. default:
  1098. err = -EINVAL;
  1099. break;
  1100. }
  1101. return err;
  1102. }
  1103. static int qp_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1104. u64 in_param)
  1105. {
  1106. int err;
  1107. int count;
  1108. int base;
  1109. int qpn;
  1110. switch (op) {
  1111. case RES_OP_RESERVE:
  1112. base = get_param_l(&in_param) & 0x7fffff;
  1113. count = get_param_h(&in_param);
  1114. err = rem_res_range(dev, slave, base, count, RES_QP, 0);
  1115. if (err)
  1116. break;
  1117. __mlx4_qp_release_range(dev, base, count);
  1118. break;
  1119. case RES_OP_MAP_ICM:
  1120. qpn = get_param_l(&in_param) & 0x7fffff;
  1121. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_RESERVED,
  1122. NULL, 0);
  1123. if (err)
  1124. return err;
  1125. if (!valid_reserved(dev, slave, qpn))
  1126. __mlx4_qp_free_icm(dev, qpn);
  1127. res_end_move(dev, slave, RES_QP, qpn);
  1128. if (valid_reserved(dev, slave, qpn))
  1129. err = rem_res_range(dev, slave, qpn, 1, RES_QP, 0);
  1130. break;
  1131. default:
  1132. err = -EINVAL;
  1133. break;
  1134. }
  1135. return err;
  1136. }
  1137. static int mtt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1138. u64 in_param, u64 *out_param)
  1139. {
  1140. int err = -EINVAL;
  1141. int base;
  1142. int order;
  1143. if (op != RES_OP_RESERVE_AND_MAP)
  1144. return err;
  1145. base = get_param_l(&in_param);
  1146. order = get_param_h(&in_param);
  1147. err = rem_res_range(dev, slave, base, 1, RES_MTT, order);
  1148. if (!err)
  1149. __mlx4_free_mtt_range(dev, base, order);
  1150. return err;
  1151. }
  1152. static int mpt_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1153. u64 in_param)
  1154. {
  1155. int err = -EINVAL;
  1156. int index;
  1157. int id;
  1158. struct res_mpt *mpt;
  1159. switch (op) {
  1160. case RES_OP_RESERVE:
  1161. index = get_param_l(&in_param);
  1162. id = index & mpt_mask(dev);
  1163. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1164. if (err)
  1165. break;
  1166. index = mpt->key;
  1167. put_res(dev, slave, id, RES_MPT);
  1168. err = rem_res_range(dev, slave, id, 1, RES_MPT, 0);
  1169. if (err)
  1170. break;
  1171. __mlx4_mr_release(dev, index);
  1172. break;
  1173. case RES_OP_MAP_ICM:
  1174. index = get_param_l(&in_param);
  1175. id = index & mpt_mask(dev);
  1176. err = mr_res_start_move_to(dev, slave, id,
  1177. RES_MPT_RESERVED, &mpt);
  1178. if (err)
  1179. return err;
  1180. __mlx4_mr_free_icm(dev, mpt->key);
  1181. res_end_move(dev, slave, RES_MPT, id);
  1182. return err;
  1183. break;
  1184. default:
  1185. err = -EINVAL;
  1186. break;
  1187. }
  1188. return err;
  1189. }
  1190. static int cq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1191. u64 in_param, u64 *out_param)
  1192. {
  1193. int cqn;
  1194. int err;
  1195. switch (op) {
  1196. case RES_OP_RESERVE_AND_MAP:
  1197. cqn = get_param_l(&in_param);
  1198. err = rem_res_range(dev, slave, cqn, 1, RES_CQ, 0);
  1199. if (err)
  1200. break;
  1201. __mlx4_cq_free_icm(dev, cqn);
  1202. break;
  1203. default:
  1204. err = -EINVAL;
  1205. break;
  1206. }
  1207. return err;
  1208. }
  1209. static int srq_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1210. u64 in_param, u64 *out_param)
  1211. {
  1212. int srqn;
  1213. int err;
  1214. switch (op) {
  1215. case RES_OP_RESERVE_AND_MAP:
  1216. srqn = get_param_l(&in_param);
  1217. err = rem_res_range(dev, slave, srqn, 1, RES_SRQ, 0);
  1218. if (err)
  1219. break;
  1220. __mlx4_srq_free_icm(dev, srqn);
  1221. break;
  1222. default:
  1223. err = -EINVAL;
  1224. break;
  1225. }
  1226. return err;
  1227. }
  1228. static int mac_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1229. u64 in_param, u64 *out_param)
  1230. {
  1231. int port;
  1232. int err = 0;
  1233. switch (op) {
  1234. case RES_OP_RESERVE_AND_MAP:
  1235. port = get_param_l(out_param);
  1236. mac_del_from_slave(dev, slave, in_param, port);
  1237. __mlx4_unregister_mac(dev, port, in_param);
  1238. break;
  1239. default:
  1240. err = -EINVAL;
  1241. break;
  1242. }
  1243. return err;
  1244. }
  1245. static int vlan_free_res(struct mlx4_dev *dev, int slave, int op, int cmd,
  1246. u64 in_param, u64 *out_param)
  1247. {
  1248. return 0;
  1249. }
  1250. int mlx4_FREE_RES_wrapper(struct mlx4_dev *dev, int slave,
  1251. struct mlx4_vhcr *vhcr,
  1252. struct mlx4_cmd_mailbox *inbox,
  1253. struct mlx4_cmd_mailbox *outbox,
  1254. struct mlx4_cmd_info *cmd)
  1255. {
  1256. int err = -EINVAL;
  1257. int alop = vhcr->op_modifier;
  1258. switch (vhcr->in_modifier) {
  1259. case RES_QP:
  1260. err = qp_free_res(dev, slave, vhcr->op_modifier, alop,
  1261. vhcr->in_param);
  1262. break;
  1263. case RES_MTT:
  1264. err = mtt_free_res(dev, slave, vhcr->op_modifier, alop,
  1265. vhcr->in_param, &vhcr->out_param);
  1266. break;
  1267. case RES_MPT:
  1268. err = mpt_free_res(dev, slave, vhcr->op_modifier, alop,
  1269. vhcr->in_param);
  1270. break;
  1271. case RES_CQ:
  1272. err = cq_free_res(dev, slave, vhcr->op_modifier, alop,
  1273. vhcr->in_param, &vhcr->out_param);
  1274. break;
  1275. case RES_SRQ:
  1276. err = srq_free_res(dev, slave, vhcr->op_modifier, alop,
  1277. vhcr->in_param, &vhcr->out_param);
  1278. break;
  1279. case RES_MAC:
  1280. err = mac_free_res(dev, slave, vhcr->op_modifier, alop,
  1281. vhcr->in_param, &vhcr->out_param);
  1282. break;
  1283. case RES_VLAN:
  1284. err = vlan_free_res(dev, slave, vhcr->op_modifier, alop,
  1285. vhcr->in_param, &vhcr->out_param);
  1286. break;
  1287. default:
  1288. break;
  1289. }
  1290. return err;
  1291. }
  1292. /* ugly but other choices are uglier */
  1293. static int mr_phys_mpt(struct mlx4_mpt_entry *mpt)
  1294. {
  1295. return (be32_to_cpu(mpt->flags) >> 9) & 1;
  1296. }
  1297. static int mr_get_mtt_addr(struct mlx4_mpt_entry *mpt)
  1298. {
  1299. return (int)be64_to_cpu(mpt->mtt_addr) & 0xfffffff8;
  1300. }
  1301. static int mr_get_mtt_size(struct mlx4_mpt_entry *mpt)
  1302. {
  1303. return be32_to_cpu(mpt->mtt_sz);
  1304. }
  1305. static int mr_get_pdn(struct mlx4_mpt_entry *mpt)
  1306. {
  1307. return be32_to_cpu(mpt->pd_flags) & 0xffffff;
  1308. }
  1309. static int qp_get_mtt_addr(struct mlx4_qp_context *qpc)
  1310. {
  1311. return be32_to_cpu(qpc->mtt_base_addr_l) & 0xfffffff8;
  1312. }
  1313. static int srq_get_mtt_addr(struct mlx4_srq_context *srqc)
  1314. {
  1315. return be32_to_cpu(srqc->mtt_base_addr_l) & 0xfffffff8;
  1316. }
  1317. static int qp_get_mtt_size(struct mlx4_qp_context *qpc)
  1318. {
  1319. int page_shift = (qpc->log_page_size & 0x3f) + 12;
  1320. int log_sq_size = (qpc->sq_size_stride >> 3) & 0xf;
  1321. int log_sq_sride = qpc->sq_size_stride & 7;
  1322. int log_rq_size = (qpc->rq_size_stride >> 3) & 0xf;
  1323. int log_rq_stride = qpc->rq_size_stride & 7;
  1324. int srq = (be32_to_cpu(qpc->srqn) >> 24) & 1;
  1325. int rss = (be32_to_cpu(qpc->flags) >> 13) & 1;
  1326. int xrc = (be32_to_cpu(qpc->local_qpn) >> 23) & 1;
  1327. int sq_size;
  1328. int rq_size;
  1329. int total_pages;
  1330. int total_mem;
  1331. int page_offset = (be32_to_cpu(qpc->params2) >> 6) & 0x3f;
  1332. sq_size = 1 << (log_sq_size + log_sq_sride + 4);
  1333. rq_size = (srq|rss|xrc) ? 0 : (1 << (log_rq_size + log_rq_stride + 4));
  1334. total_mem = sq_size + rq_size;
  1335. total_pages =
  1336. roundup_pow_of_two((total_mem + (page_offset << 6)) >>
  1337. page_shift);
  1338. return total_pages;
  1339. }
  1340. static int qp_get_pdn(struct mlx4_qp_context *qpc)
  1341. {
  1342. return be32_to_cpu(qpc->pd) & 0xffffff;
  1343. }
  1344. static int pdn2slave(int pdn)
  1345. {
  1346. return (pdn >> NOT_MASKED_PD_BITS) - 1;
  1347. }
  1348. static int check_mtt_range(struct mlx4_dev *dev, int slave, int start,
  1349. int size, struct res_mtt *mtt)
  1350. {
  1351. int res_start = mtt->com.res_id;
  1352. int res_size = (1 << mtt->order);
  1353. if (start < res_start || start + size > res_start + res_size)
  1354. return -EPERM;
  1355. return 0;
  1356. }
  1357. int mlx4_SW2HW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1358. struct mlx4_vhcr *vhcr,
  1359. struct mlx4_cmd_mailbox *inbox,
  1360. struct mlx4_cmd_mailbox *outbox,
  1361. struct mlx4_cmd_info *cmd)
  1362. {
  1363. int err;
  1364. int index = vhcr->in_modifier;
  1365. struct res_mtt *mtt;
  1366. struct res_mpt *mpt;
  1367. int mtt_base = mr_get_mtt_addr(inbox->buf) / dev->caps.mtt_entry_sz;
  1368. int phys;
  1369. int id;
  1370. id = index & mpt_mask(dev);
  1371. err = mr_res_start_move_to(dev, slave, id, RES_MPT_HW, &mpt);
  1372. if (err)
  1373. return err;
  1374. phys = mr_phys_mpt(inbox->buf);
  1375. if (!phys) {
  1376. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1377. if (err)
  1378. goto ex_abort;
  1379. err = check_mtt_range(dev, slave, mtt_base,
  1380. mr_get_mtt_size(inbox->buf), mtt);
  1381. if (err)
  1382. goto ex_put;
  1383. mpt->mtt = mtt;
  1384. }
  1385. if (pdn2slave(mr_get_pdn(inbox->buf)) != slave) {
  1386. err = -EPERM;
  1387. goto ex_put;
  1388. }
  1389. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1390. if (err)
  1391. goto ex_put;
  1392. if (!phys) {
  1393. atomic_inc(&mtt->ref_count);
  1394. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1395. }
  1396. res_end_move(dev, slave, RES_MPT, id);
  1397. return 0;
  1398. ex_put:
  1399. if (!phys)
  1400. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1401. ex_abort:
  1402. res_abort_move(dev, slave, RES_MPT, id);
  1403. return err;
  1404. }
  1405. int mlx4_HW2SW_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1406. struct mlx4_vhcr *vhcr,
  1407. struct mlx4_cmd_mailbox *inbox,
  1408. struct mlx4_cmd_mailbox *outbox,
  1409. struct mlx4_cmd_info *cmd)
  1410. {
  1411. int err;
  1412. int index = vhcr->in_modifier;
  1413. struct res_mpt *mpt;
  1414. int id;
  1415. id = index & mpt_mask(dev);
  1416. err = mr_res_start_move_to(dev, slave, id, RES_MPT_MAPPED, &mpt);
  1417. if (err)
  1418. return err;
  1419. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1420. if (err)
  1421. goto ex_abort;
  1422. if (mpt->mtt)
  1423. atomic_dec(&mpt->mtt->ref_count);
  1424. res_end_move(dev, slave, RES_MPT, id);
  1425. return 0;
  1426. ex_abort:
  1427. res_abort_move(dev, slave, RES_MPT, id);
  1428. return err;
  1429. }
  1430. int mlx4_QUERY_MPT_wrapper(struct mlx4_dev *dev, int slave,
  1431. struct mlx4_vhcr *vhcr,
  1432. struct mlx4_cmd_mailbox *inbox,
  1433. struct mlx4_cmd_mailbox *outbox,
  1434. struct mlx4_cmd_info *cmd)
  1435. {
  1436. int err;
  1437. int index = vhcr->in_modifier;
  1438. struct res_mpt *mpt;
  1439. int id;
  1440. id = index & mpt_mask(dev);
  1441. err = get_res(dev, slave, id, RES_MPT, &mpt);
  1442. if (err)
  1443. return err;
  1444. if (mpt->com.from_state != RES_MPT_HW) {
  1445. err = -EBUSY;
  1446. goto out;
  1447. }
  1448. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1449. out:
  1450. put_res(dev, slave, id, RES_MPT);
  1451. return err;
  1452. }
  1453. static int qp_get_rcqn(struct mlx4_qp_context *qpc)
  1454. {
  1455. return be32_to_cpu(qpc->cqn_recv) & 0xffffff;
  1456. }
  1457. static int qp_get_scqn(struct mlx4_qp_context *qpc)
  1458. {
  1459. return be32_to_cpu(qpc->cqn_send) & 0xffffff;
  1460. }
  1461. static u32 qp_get_srqn(struct mlx4_qp_context *qpc)
  1462. {
  1463. return be32_to_cpu(qpc->srqn) & 0x1ffffff;
  1464. }
  1465. int mlx4_RST2INIT_QP_wrapper(struct mlx4_dev *dev, int slave,
  1466. struct mlx4_vhcr *vhcr,
  1467. struct mlx4_cmd_mailbox *inbox,
  1468. struct mlx4_cmd_mailbox *outbox,
  1469. struct mlx4_cmd_info *cmd)
  1470. {
  1471. int err;
  1472. int qpn = vhcr->in_modifier & 0x7fffff;
  1473. struct res_mtt *mtt;
  1474. struct res_qp *qp;
  1475. struct mlx4_qp_context *qpc = inbox->buf + 8;
  1476. int mtt_base = qp_get_mtt_addr(qpc) / dev->caps.mtt_entry_sz;
  1477. int mtt_size = qp_get_mtt_size(qpc);
  1478. struct res_cq *rcq;
  1479. struct res_cq *scq;
  1480. int rcqn = qp_get_rcqn(qpc);
  1481. int scqn = qp_get_scqn(qpc);
  1482. u32 srqn = qp_get_srqn(qpc) & 0xffffff;
  1483. int use_srq = (qp_get_srqn(qpc) >> 24) & 1;
  1484. struct res_srq *srq;
  1485. int local_qpn = be32_to_cpu(qpc->local_qpn) & 0xffffff;
  1486. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_HW, &qp, 0);
  1487. if (err)
  1488. return err;
  1489. qp->local_qpn = local_qpn;
  1490. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1491. if (err)
  1492. goto ex_abort;
  1493. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1494. if (err)
  1495. goto ex_put_mtt;
  1496. if (pdn2slave(qp_get_pdn(qpc)) != slave) {
  1497. err = -EPERM;
  1498. goto ex_put_mtt;
  1499. }
  1500. err = get_res(dev, slave, rcqn, RES_CQ, &rcq);
  1501. if (err)
  1502. goto ex_put_mtt;
  1503. if (scqn != rcqn) {
  1504. err = get_res(dev, slave, scqn, RES_CQ, &scq);
  1505. if (err)
  1506. goto ex_put_rcq;
  1507. } else
  1508. scq = rcq;
  1509. if (use_srq) {
  1510. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1511. if (err)
  1512. goto ex_put_scq;
  1513. }
  1514. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1515. if (err)
  1516. goto ex_put_srq;
  1517. atomic_inc(&mtt->ref_count);
  1518. qp->mtt = mtt;
  1519. atomic_inc(&rcq->ref_count);
  1520. qp->rcq = rcq;
  1521. atomic_inc(&scq->ref_count);
  1522. qp->scq = scq;
  1523. if (scqn != rcqn)
  1524. put_res(dev, slave, scqn, RES_CQ);
  1525. if (use_srq) {
  1526. atomic_inc(&srq->ref_count);
  1527. put_res(dev, slave, srqn, RES_SRQ);
  1528. qp->srq = srq;
  1529. }
  1530. put_res(dev, slave, rcqn, RES_CQ);
  1531. put_res(dev, slave, mtt_base, RES_MTT);
  1532. res_end_move(dev, slave, RES_QP, qpn);
  1533. return 0;
  1534. ex_put_srq:
  1535. if (use_srq)
  1536. put_res(dev, slave, srqn, RES_SRQ);
  1537. ex_put_scq:
  1538. if (scqn != rcqn)
  1539. put_res(dev, slave, scqn, RES_CQ);
  1540. ex_put_rcq:
  1541. put_res(dev, slave, rcqn, RES_CQ);
  1542. ex_put_mtt:
  1543. put_res(dev, slave, mtt_base, RES_MTT);
  1544. ex_abort:
  1545. res_abort_move(dev, slave, RES_QP, qpn);
  1546. return err;
  1547. }
  1548. static int eq_get_mtt_addr(struct mlx4_eq_context *eqc)
  1549. {
  1550. return be32_to_cpu(eqc->mtt_base_addr_l) & 0xfffffff8;
  1551. }
  1552. static int eq_get_mtt_size(struct mlx4_eq_context *eqc)
  1553. {
  1554. int log_eq_size = eqc->log_eq_size & 0x1f;
  1555. int page_shift = (eqc->log_page_size & 0x3f) + 12;
  1556. if (log_eq_size + 5 < page_shift)
  1557. return 1;
  1558. return 1 << (log_eq_size + 5 - page_shift);
  1559. }
  1560. static int cq_get_mtt_addr(struct mlx4_cq_context *cqc)
  1561. {
  1562. return be32_to_cpu(cqc->mtt_base_addr_l) & 0xfffffff8;
  1563. }
  1564. static int cq_get_mtt_size(struct mlx4_cq_context *cqc)
  1565. {
  1566. int log_cq_size = (be32_to_cpu(cqc->logsize_usrpage) >> 24) & 0x1f;
  1567. int page_shift = (cqc->log_page_size & 0x3f) + 12;
  1568. if (log_cq_size + 5 < page_shift)
  1569. return 1;
  1570. return 1 << (log_cq_size + 5 - page_shift);
  1571. }
  1572. int mlx4_SW2HW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1573. struct mlx4_vhcr *vhcr,
  1574. struct mlx4_cmd_mailbox *inbox,
  1575. struct mlx4_cmd_mailbox *outbox,
  1576. struct mlx4_cmd_info *cmd)
  1577. {
  1578. int err;
  1579. int eqn = vhcr->in_modifier;
  1580. int res_id = (slave << 8) | eqn;
  1581. struct mlx4_eq_context *eqc = inbox->buf;
  1582. int mtt_base = eq_get_mtt_addr(eqc) / dev->caps.mtt_entry_sz;
  1583. int mtt_size = eq_get_mtt_size(eqc);
  1584. struct res_eq *eq;
  1585. struct res_mtt *mtt;
  1586. err = add_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1587. if (err)
  1588. return err;
  1589. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_HW, &eq);
  1590. if (err)
  1591. goto out_add;
  1592. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1593. if (err)
  1594. goto out_move;
  1595. err = check_mtt_range(dev, slave, mtt_base, mtt_size, mtt);
  1596. if (err)
  1597. goto out_put;
  1598. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1599. if (err)
  1600. goto out_put;
  1601. atomic_inc(&mtt->ref_count);
  1602. eq->mtt = mtt;
  1603. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1604. res_end_move(dev, slave, RES_EQ, res_id);
  1605. return 0;
  1606. out_put:
  1607. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1608. out_move:
  1609. res_abort_move(dev, slave, RES_EQ, res_id);
  1610. out_add:
  1611. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1612. return err;
  1613. }
  1614. static int get_containing_mtt(struct mlx4_dev *dev, int slave, int start,
  1615. int len, struct res_mtt **res)
  1616. {
  1617. struct mlx4_priv *priv = mlx4_priv(dev);
  1618. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  1619. struct res_mtt *mtt;
  1620. int err = -EINVAL;
  1621. spin_lock_irq(mlx4_tlock(dev));
  1622. list_for_each_entry(mtt, &tracker->slave_list[slave].res_list[RES_MTT],
  1623. com.list) {
  1624. if (!check_mtt_range(dev, slave, start, len, mtt)) {
  1625. *res = mtt;
  1626. mtt->com.from_state = mtt->com.state;
  1627. mtt->com.state = RES_MTT_BUSY;
  1628. err = 0;
  1629. break;
  1630. }
  1631. }
  1632. spin_unlock_irq(mlx4_tlock(dev));
  1633. return err;
  1634. }
  1635. int mlx4_WRITE_MTT_wrapper(struct mlx4_dev *dev, int slave,
  1636. struct mlx4_vhcr *vhcr,
  1637. struct mlx4_cmd_mailbox *inbox,
  1638. struct mlx4_cmd_mailbox *outbox,
  1639. struct mlx4_cmd_info *cmd)
  1640. {
  1641. struct mlx4_mtt mtt;
  1642. __be64 *page_list = inbox->buf;
  1643. u64 *pg_list = (u64 *)page_list;
  1644. int i;
  1645. struct res_mtt *rmtt = NULL;
  1646. int start = be64_to_cpu(page_list[0]);
  1647. int npages = vhcr->in_modifier;
  1648. int err;
  1649. err = get_containing_mtt(dev, slave, start, npages, &rmtt);
  1650. if (err)
  1651. return err;
  1652. /* Call the SW implementation of write_mtt:
  1653. * - Prepare a dummy mtt struct
  1654. * - Translate inbox contents to simple addresses in host endianess */
  1655. mtt.offset = 0; /* TBD this is broken but I don't handle it since
  1656. we don't really use it */
  1657. mtt.order = 0;
  1658. mtt.page_shift = 0;
  1659. for (i = 0; i < npages; ++i)
  1660. pg_list[i + 2] = (be64_to_cpu(page_list[i + 2]) & ~1ULL);
  1661. err = __mlx4_write_mtt(dev, &mtt, be64_to_cpu(page_list[0]), npages,
  1662. ((u64 *)page_list + 2));
  1663. if (rmtt)
  1664. put_res(dev, slave, rmtt->com.res_id, RES_MTT);
  1665. return err;
  1666. }
  1667. int mlx4_HW2SW_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1668. struct mlx4_vhcr *vhcr,
  1669. struct mlx4_cmd_mailbox *inbox,
  1670. struct mlx4_cmd_mailbox *outbox,
  1671. struct mlx4_cmd_info *cmd)
  1672. {
  1673. int eqn = vhcr->in_modifier;
  1674. int res_id = eqn | (slave << 8);
  1675. struct res_eq *eq;
  1676. int err;
  1677. err = eq_res_start_move_to(dev, slave, res_id, RES_EQ_RESERVED, &eq);
  1678. if (err)
  1679. return err;
  1680. err = get_res(dev, slave, eq->mtt->com.res_id, RES_MTT, NULL);
  1681. if (err)
  1682. goto ex_abort;
  1683. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1684. if (err)
  1685. goto ex_put;
  1686. atomic_dec(&eq->mtt->ref_count);
  1687. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1688. res_end_move(dev, slave, RES_EQ, res_id);
  1689. rem_res_range(dev, slave, res_id, 1, RES_EQ, 0);
  1690. return 0;
  1691. ex_put:
  1692. put_res(dev, slave, eq->mtt->com.res_id, RES_MTT);
  1693. ex_abort:
  1694. res_abort_move(dev, slave, RES_EQ, res_id);
  1695. return err;
  1696. }
  1697. int mlx4_GEN_EQE(struct mlx4_dev *dev, int slave, struct mlx4_eqe *eqe)
  1698. {
  1699. struct mlx4_priv *priv = mlx4_priv(dev);
  1700. struct mlx4_slave_event_eq_info *event_eq;
  1701. struct mlx4_cmd_mailbox *mailbox;
  1702. u32 in_modifier = 0;
  1703. int err;
  1704. int res_id;
  1705. struct res_eq *req;
  1706. if (!priv->mfunc.master.slave_state)
  1707. return -EINVAL;
  1708. event_eq = &priv->mfunc.master.slave_state[slave].event_eq;
  1709. /* Create the event only if the slave is registered */
  1710. if ((event_eq->event_type & (1 << eqe->type)) == 0)
  1711. return 0;
  1712. mutex_lock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1713. res_id = (slave << 8) | event_eq->eqn;
  1714. err = get_res(dev, slave, res_id, RES_EQ, &req);
  1715. if (err)
  1716. goto unlock;
  1717. if (req->com.from_state != RES_EQ_HW) {
  1718. err = -EINVAL;
  1719. goto put;
  1720. }
  1721. mailbox = mlx4_alloc_cmd_mailbox(dev);
  1722. if (IS_ERR(mailbox)) {
  1723. err = PTR_ERR(mailbox);
  1724. goto put;
  1725. }
  1726. if (eqe->type == MLX4_EVENT_TYPE_CMD) {
  1727. ++event_eq->token;
  1728. eqe->event.cmd.token = cpu_to_be16(event_eq->token);
  1729. }
  1730. memcpy(mailbox->buf, (u8 *) eqe, 28);
  1731. in_modifier = (slave & 0xff) | ((event_eq->eqn & 0xff) << 16);
  1732. err = mlx4_cmd(dev, mailbox->dma, in_modifier, 0,
  1733. MLX4_CMD_GEN_EQE, MLX4_CMD_TIME_CLASS_B,
  1734. MLX4_CMD_NATIVE);
  1735. put_res(dev, slave, res_id, RES_EQ);
  1736. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1737. mlx4_free_cmd_mailbox(dev, mailbox);
  1738. return err;
  1739. put:
  1740. put_res(dev, slave, res_id, RES_EQ);
  1741. unlock:
  1742. mutex_unlock(&priv->mfunc.master.gen_eqe_mutex[slave]);
  1743. return err;
  1744. }
  1745. int mlx4_QUERY_EQ_wrapper(struct mlx4_dev *dev, int slave,
  1746. struct mlx4_vhcr *vhcr,
  1747. struct mlx4_cmd_mailbox *inbox,
  1748. struct mlx4_cmd_mailbox *outbox,
  1749. struct mlx4_cmd_info *cmd)
  1750. {
  1751. int eqn = vhcr->in_modifier;
  1752. int res_id = eqn | (slave << 8);
  1753. struct res_eq *eq;
  1754. int err;
  1755. err = get_res(dev, slave, res_id, RES_EQ, &eq);
  1756. if (err)
  1757. return err;
  1758. if (eq->com.from_state != RES_EQ_HW) {
  1759. err = -EINVAL;
  1760. goto ex_put;
  1761. }
  1762. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1763. ex_put:
  1764. put_res(dev, slave, res_id, RES_EQ);
  1765. return err;
  1766. }
  1767. int mlx4_SW2HW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1768. struct mlx4_vhcr *vhcr,
  1769. struct mlx4_cmd_mailbox *inbox,
  1770. struct mlx4_cmd_mailbox *outbox,
  1771. struct mlx4_cmd_info *cmd)
  1772. {
  1773. int err;
  1774. int cqn = vhcr->in_modifier;
  1775. struct mlx4_cq_context *cqc = inbox->buf;
  1776. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1777. struct res_cq *cq;
  1778. struct res_mtt *mtt;
  1779. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_HW, &cq);
  1780. if (err)
  1781. return err;
  1782. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1783. if (err)
  1784. goto out_move;
  1785. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1786. if (err)
  1787. goto out_put;
  1788. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1789. if (err)
  1790. goto out_put;
  1791. atomic_inc(&mtt->ref_count);
  1792. cq->mtt = mtt;
  1793. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1794. res_end_move(dev, slave, RES_CQ, cqn);
  1795. return 0;
  1796. out_put:
  1797. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1798. out_move:
  1799. res_abort_move(dev, slave, RES_CQ, cqn);
  1800. return err;
  1801. }
  1802. int mlx4_HW2SW_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1803. struct mlx4_vhcr *vhcr,
  1804. struct mlx4_cmd_mailbox *inbox,
  1805. struct mlx4_cmd_mailbox *outbox,
  1806. struct mlx4_cmd_info *cmd)
  1807. {
  1808. int err;
  1809. int cqn = vhcr->in_modifier;
  1810. struct res_cq *cq;
  1811. err = cq_res_start_move_to(dev, slave, cqn, RES_CQ_ALLOCATED, &cq);
  1812. if (err)
  1813. return err;
  1814. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1815. if (err)
  1816. goto out_move;
  1817. atomic_dec(&cq->mtt->ref_count);
  1818. res_end_move(dev, slave, RES_CQ, cqn);
  1819. return 0;
  1820. out_move:
  1821. res_abort_move(dev, slave, RES_CQ, cqn);
  1822. return err;
  1823. }
  1824. int mlx4_QUERY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1825. struct mlx4_vhcr *vhcr,
  1826. struct mlx4_cmd_mailbox *inbox,
  1827. struct mlx4_cmd_mailbox *outbox,
  1828. struct mlx4_cmd_info *cmd)
  1829. {
  1830. int cqn = vhcr->in_modifier;
  1831. struct res_cq *cq;
  1832. int err;
  1833. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1834. if (err)
  1835. return err;
  1836. if (cq->com.from_state != RES_CQ_HW)
  1837. goto ex_put;
  1838. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1839. ex_put:
  1840. put_res(dev, slave, cqn, RES_CQ);
  1841. return err;
  1842. }
  1843. static int handle_resize(struct mlx4_dev *dev, int slave,
  1844. struct mlx4_vhcr *vhcr,
  1845. struct mlx4_cmd_mailbox *inbox,
  1846. struct mlx4_cmd_mailbox *outbox,
  1847. struct mlx4_cmd_info *cmd,
  1848. struct res_cq *cq)
  1849. {
  1850. int err;
  1851. struct res_mtt *orig_mtt;
  1852. struct res_mtt *mtt;
  1853. struct mlx4_cq_context *cqc = inbox->buf;
  1854. int mtt_base = cq_get_mtt_addr(cqc) / dev->caps.mtt_entry_sz;
  1855. err = get_res(dev, slave, cq->mtt->com.res_id, RES_MTT, &orig_mtt);
  1856. if (err)
  1857. return err;
  1858. if (orig_mtt != cq->mtt) {
  1859. err = -EINVAL;
  1860. goto ex_put;
  1861. }
  1862. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1863. if (err)
  1864. goto ex_put;
  1865. err = check_mtt_range(dev, slave, mtt_base, cq_get_mtt_size(cqc), mtt);
  1866. if (err)
  1867. goto ex_put1;
  1868. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1869. if (err)
  1870. goto ex_put1;
  1871. atomic_dec(&orig_mtt->ref_count);
  1872. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1873. atomic_inc(&mtt->ref_count);
  1874. cq->mtt = mtt;
  1875. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1876. return 0;
  1877. ex_put1:
  1878. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1879. ex_put:
  1880. put_res(dev, slave, orig_mtt->com.res_id, RES_MTT);
  1881. return err;
  1882. }
  1883. int mlx4_MODIFY_CQ_wrapper(struct mlx4_dev *dev, int slave,
  1884. struct mlx4_vhcr *vhcr,
  1885. struct mlx4_cmd_mailbox *inbox,
  1886. struct mlx4_cmd_mailbox *outbox,
  1887. struct mlx4_cmd_info *cmd)
  1888. {
  1889. int cqn = vhcr->in_modifier;
  1890. struct res_cq *cq;
  1891. int err;
  1892. err = get_res(dev, slave, cqn, RES_CQ, &cq);
  1893. if (err)
  1894. return err;
  1895. if (cq->com.from_state != RES_CQ_HW)
  1896. goto ex_put;
  1897. if (vhcr->op_modifier == 0) {
  1898. err = handle_resize(dev, slave, vhcr, inbox, outbox, cmd, cq);
  1899. if (err)
  1900. goto ex_put;
  1901. }
  1902. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1903. ex_put:
  1904. put_res(dev, slave, cqn, RES_CQ);
  1905. return err;
  1906. }
  1907. static int srq_get_pdn(struct mlx4_srq_context *srqc)
  1908. {
  1909. return be32_to_cpu(srqc->pd) & 0xffffff;
  1910. }
  1911. static int srq_get_mtt_size(struct mlx4_srq_context *srqc)
  1912. {
  1913. int log_srq_size = (be32_to_cpu(srqc->state_logsize_srqn) >> 24) & 0xf;
  1914. int log_rq_stride = srqc->logstride & 7;
  1915. int page_shift = (srqc->log_page_size & 0x3f) + 12;
  1916. if (log_srq_size + log_rq_stride + 4 < page_shift)
  1917. return 1;
  1918. return 1 << (log_srq_size + log_rq_stride + 4 - page_shift);
  1919. }
  1920. int mlx4_SW2HW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1921. struct mlx4_vhcr *vhcr,
  1922. struct mlx4_cmd_mailbox *inbox,
  1923. struct mlx4_cmd_mailbox *outbox,
  1924. struct mlx4_cmd_info *cmd)
  1925. {
  1926. int err;
  1927. int srqn = vhcr->in_modifier;
  1928. struct res_mtt *mtt;
  1929. struct res_srq *srq;
  1930. struct mlx4_srq_context *srqc = inbox->buf;
  1931. int mtt_base = srq_get_mtt_addr(srqc) / dev->caps.mtt_entry_sz;
  1932. if (srqn != (be32_to_cpu(srqc->state_logsize_srqn) & 0xffffff))
  1933. return -EINVAL;
  1934. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_HW, &srq);
  1935. if (err)
  1936. return err;
  1937. err = get_res(dev, slave, mtt_base, RES_MTT, &mtt);
  1938. if (err)
  1939. goto ex_abort;
  1940. err = check_mtt_range(dev, slave, mtt_base, srq_get_mtt_size(srqc),
  1941. mtt);
  1942. if (err)
  1943. goto ex_put_mtt;
  1944. if (pdn2slave(srq_get_pdn(srqc)) != slave) {
  1945. err = -EPERM;
  1946. goto ex_put_mtt;
  1947. }
  1948. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1949. if (err)
  1950. goto ex_put_mtt;
  1951. atomic_inc(&mtt->ref_count);
  1952. srq->mtt = mtt;
  1953. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1954. res_end_move(dev, slave, RES_SRQ, srqn);
  1955. return 0;
  1956. ex_put_mtt:
  1957. put_res(dev, slave, mtt->com.res_id, RES_MTT);
  1958. ex_abort:
  1959. res_abort_move(dev, slave, RES_SRQ, srqn);
  1960. return err;
  1961. }
  1962. int mlx4_HW2SW_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1963. struct mlx4_vhcr *vhcr,
  1964. struct mlx4_cmd_mailbox *inbox,
  1965. struct mlx4_cmd_mailbox *outbox,
  1966. struct mlx4_cmd_info *cmd)
  1967. {
  1968. int err;
  1969. int srqn = vhcr->in_modifier;
  1970. struct res_srq *srq;
  1971. err = srq_res_start_move_to(dev, slave, srqn, RES_SRQ_ALLOCATED, &srq);
  1972. if (err)
  1973. return err;
  1974. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  1975. if (err)
  1976. goto ex_abort;
  1977. atomic_dec(&srq->mtt->ref_count);
  1978. if (srq->cq)
  1979. atomic_dec(&srq->cq->ref_count);
  1980. res_end_move(dev, slave, RES_SRQ, srqn);
  1981. return 0;
  1982. ex_abort:
  1983. res_abort_move(dev, slave, RES_SRQ, srqn);
  1984. return err;
  1985. }
  1986. int mlx4_QUERY_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  1987. struct mlx4_vhcr *vhcr,
  1988. struct mlx4_cmd_mailbox *inbox,
  1989. struct mlx4_cmd_mailbox *outbox,
  1990. struct mlx4_cmd_info *cmd)
  1991. {
  1992. int err;
  1993. int srqn = vhcr->in_modifier;
  1994. struct res_srq *srq;
  1995. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  1996. if (err)
  1997. return err;
  1998. if (srq->com.from_state != RES_SRQ_HW) {
  1999. err = -EBUSY;
  2000. goto out;
  2001. }
  2002. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2003. out:
  2004. put_res(dev, slave, srqn, RES_SRQ);
  2005. return err;
  2006. }
  2007. int mlx4_ARM_SRQ_wrapper(struct mlx4_dev *dev, int slave,
  2008. struct mlx4_vhcr *vhcr,
  2009. struct mlx4_cmd_mailbox *inbox,
  2010. struct mlx4_cmd_mailbox *outbox,
  2011. struct mlx4_cmd_info *cmd)
  2012. {
  2013. int err;
  2014. int srqn = vhcr->in_modifier;
  2015. struct res_srq *srq;
  2016. err = get_res(dev, slave, srqn, RES_SRQ, &srq);
  2017. if (err)
  2018. return err;
  2019. if (srq->com.from_state != RES_SRQ_HW) {
  2020. err = -EBUSY;
  2021. goto out;
  2022. }
  2023. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2024. out:
  2025. put_res(dev, slave, srqn, RES_SRQ);
  2026. return err;
  2027. }
  2028. int mlx4_GEN_QP_wrapper(struct mlx4_dev *dev, int slave,
  2029. struct mlx4_vhcr *vhcr,
  2030. struct mlx4_cmd_mailbox *inbox,
  2031. struct mlx4_cmd_mailbox *outbox,
  2032. struct mlx4_cmd_info *cmd)
  2033. {
  2034. int err;
  2035. int qpn = vhcr->in_modifier & 0x7fffff;
  2036. struct res_qp *qp;
  2037. err = get_res(dev, slave, qpn, RES_QP, &qp);
  2038. if (err)
  2039. return err;
  2040. if (qp->com.from_state != RES_QP_HW) {
  2041. err = -EBUSY;
  2042. goto out;
  2043. }
  2044. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2045. out:
  2046. put_res(dev, slave, qpn, RES_QP);
  2047. return err;
  2048. }
  2049. int mlx4_INIT2RTR_QP_wrapper(struct mlx4_dev *dev, int slave,
  2050. struct mlx4_vhcr *vhcr,
  2051. struct mlx4_cmd_mailbox *inbox,
  2052. struct mlx4_cmd_mailbox *outbox,
  2053. struct mlx4_cmd_info *cmd)
  2054. {
  2055. struct mlx4_qp_context *qpc = inbox->buf + 8;
  2056. update_ud_gid(dev, qpc, (u8)slave);
  2057. return mlx4_GEN_QP_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2058. }
  2059. int mlx4_2RST_QP_wrapper(struct mlx4_dev *dev, int slave,
  2060. struct mlx4_vhcr *vhcr,
  2061. struct mlx4_cmd_mailbox *inbox,
  2062. struct mlx4_cmd_mailbox *outbox,
  2063. struct mlx4_cmd_info *cmd)
  2064. {
  2065. int err;
  2066. int qpn = vhcr->in_modifier & 0x7fffff;
  2067. struct res_qp *qp;
  2068. err = qp_res_start_move_to(dev, slave, qpn, RES_QP_MAPPED, &qp, 0);
  2069. if (err)
  2070. return err;
  2071. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2072. if (err)
  2073. goto ex_abort;
  2074. atomic_dec(&qp->mtt->ref_count);
  2075. atomic_dec(&qp->rcq->ref_count);
  2076. atomic_dec(&qp->scq->ref_count);
  2077. if (qp->srq)
  2078. atomic_dec(&qp->srq->ref_count);
  2079. res_end_move(dev, slave, RES_QP, qpn);
  2080. return 0;
  2081. ex_abort:
  2082. res_abort_move(dev, slave, RES_QP, qpn);
  2083. return err;
  2084. }
  2085. static struct res_gid *find_gid(struct mlx4_dev *dev, int slave,
  2086. struct res_qp *rqp, u8 *gid)
  2087. {
  2088. struct res_gid *res;
  2089. list_for_each_entry(res, &rqp->mcg_list, list) {
  2090. if (!memcmp(res->gid, gid, 16))
  2091. return res;
  2092. }
  2093. return NULL;
  2094. }
  2095. static int add_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2096. u8 *gid, enum mlx4_protocol prot)
  2097. {
  2098. struct res_gid *res;
  2099. int err;
  2100. res = kzalloc(sizeof *res, GFP_KERNEL);
  2101. if (!res)
  2102. return -ENOMEM;
  2103. spin_lock_irq(&rqp->mcg_spl);
  2104. if (find_gid(dev, slave, rqp, gid)) {
  2105. kfree(res);
  2106. err = -EEXIST;
  2107. } else {
  2108. memcpy(res->gid, gid, 16);
  2109. res->prot = prot;
  2110. list_add_tail(&res->list, &rqp->mcg_list);
  2111. err = 0;
  2112. }
  2113. spin_unlock_irq(&rqp->mcg_spl);
  2114. return err;
  2115. }
  2116. static int rem_mcg_res(struct mlx4_dev *dev, int slave, struct res_qp *rqp,
  2117. u8 *gid, enum mlx4_protocol prot)
  2118. {
  2119. struct res_gid *res;
  2120. int err;
  2121. spin_lock_irq(&rqp->mcg_spl);
  2122. res = find_gid(dev, slave, rqp, gid);
  2123. if (!res || res->prot != prot)
  2124. err = -EINVAL;
  2125. else {
  2126. list_del(&res->list);
  2127. kfree(res);
  2128. err = 0;
  2129. }
  2130. spin_unlock_irq(&rqp->mcg_spl);
  2131. return err;
  2132. }
  2133. int mlx4_QP_ATTACH_wrapper(struct mlx4_dev *dev, int slave,
  2134. struct mlx4_vhcr *vhcr,
  2135. struct mlx4_cmd_mailbox *inbox,
  2136. struct mlx4_cmd_mailbox *outbox,
  2137. struct mlx4_cmd_info *cmd)
  2138. {
  2139. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2140. u8 *gid = inbox->buf;
  2141. enum mlx4_protocol prot = (vhcr->in_modifier >> 28) & 0x7;
  2142. int err, err1;
  2143. int qpn;
  2144. struct res_qp *rqp;
  2145. int attach = vhcr->op_modifier;
  2146. int block_loopback = vhcr->in_modifier >> 31;
  2147. u8 steer_type_mask = 2;
  2148. enum mlx4_steer_type type = gid[7] & steer_type_mask;
  2149. qpn = vhcr->in_modifier & 0xffffff;
  2150. err = get_res(dev, slave, qpn, RES_QP, &rqp);
  2151. if (err)
  2152. return err;
  2153. qp.qpn = qpn;
  2154. if (attach) {
  2155. err = add_mcg_res(dev, slave, rqp, gid, prot);
  2156. if (err)
  2157. goto ex_put;
  2158. err = mlx4_qp_attach_common(dev, &qp, gid,
  2159. block_loopback, prot, type);
  2160. if (err)
  2161. goto ex_rem;
  2162. } else {
  2163. err = rem_mcg_res(dev, slave, rqp, gid, prot);
  2164. if (err)
  2165. goto ex_put;
  2166. err = mlx4_qp_detach_common(dev, &qp, gid, prot, type);
  2167. }
  2168. put_res(dev, slave, qpn, RES_QP);
  2169. return 0;
  2170. ex_rem:
  2171. /* ignore error return below, already in error */
  2172. err1 = rem_mcg_res(dev, slave, rqp, gid, prot);
  2173. ex_put:
  2174. put_res(dev, slave, qpn, RES_QP);
  2175. return err;
  2176. }
  2177. enum {
  2178. BUSY_MAX_RETRIES = 10
  2179. };
  2180. int mlx4_QUERY_IF_STAT_wrapper(struct mlx4_dev *dev, int slave,
  2181. struct mlx4_vhcr *vhcr,
  2182. struct mlx4_cmd_mailbox *inbox,
  2183. struct mlx4_cmd_mailbox *outbox,
  2184. struct mlx4_cmd_info *cmd)
  2185. {
  2186. int err;
  2187. int index = vhcr->in_modifier & 0xffff;
  2188. err = get_res(dev, slave, index, RES_COUNTER, NULL);
  2189. if (err)
  2190. return err;
  2191. err = mlx4_DMA_wrapper(dev, slave, vhcr, inbox, outbox, cmd);
  2192. put_res(dev, slave, index, RES_COUNTER);
  2193. return err;
  2194. }
  2195. static void detach_qp(struct mlx4_dev *dev, int slave, struct res_qp *rqp)
  2196. {
  2197. struct res_gid *rgid;
  2198. struct res_gid *tmp;
  2199. int err;
  2200. struct mlx4_qp qp; /* dummy for calling attach/detach */
  2201. list_for_each_entry_safe(rgid, tmp, &rqp->mcg_list, list) {
  2202. qp.qpn = rqp->local_qpn;
  2203. err = mlx4_qp_detach_common(dev, &qp, rgid->gid, rgid->prot,
  2204. MLX4_MC_STEER);
  2205. list_del(&rgid->list);
  2206. kfree(rgid);
  2207. }
  2208. }
  2209. static int _move_all_busy(struct mlx4_dev *dev, int slave,
  2210. enum mlx4_resource type, int print)
  2211. {
  2212. struct mlx4_priv *priv = mlx4_priv(dev);
  2213. struct mlx4_resource_tracker *tracker =
  2214. &priv->mfunc.master.res_tracker;
  2215. struct list_head *rlist = &tracker->slave_list[slave].res_list[type];
  2216. struct res_common *r;
  2217. struct res_common *tmp;
  2218. int busy;
  2219. busy = 0;
  2220. spin_lock_irq(mlx4_tlock(dev));
  2221. list_for_each_entry_safe(r, tmp, rlist, list) {
  2222. if (r->owner == slave) {
  2223. if (!r->removing) {
  2224. if (r->state == RES_ANY_BUSY) {
  2225. if (print)
  2226. mlx4_dbg(dev,
  2227. "%s id 0x%x is busy\n",
  2228. ResourceType(type),
  2229. r->res_id);
  2230. ++busy;
  2231. } else {
  2232. r->from_state = r->state;
  2233. r->state = RES_ANY_BUSY;
  2234. r->removing = 1;
  2235. }
  2236. }
  2237. }
  2238. }
  2239. spin_unlock_irq(mlx4_tlock(dev));
  2240. return busy;
  2241. }
  2242. static int move_all_busy(struct mlx4_dev *dev, int slave,
  2243. enum mlx4_resource type)
  2244. {
  2245. unsigned long begin;
  2246. int busy;
  2247. begin = jiffies;
  2248. do {
  2249. busy = _move_all_busy(dev, slave, type, 0);
  2250. if (time_after(jiffies, begin + 5 * HZ))
  2251. break;
  2252. if (busy)
  2253. cond_resched();
  2254. } while (busy);
  2255. if (busy)
  2256. busy = _move_all_busy(dev, slave, type, 1);
  2257. return busy;
  2258. }
  2259. static void rem_slave_qps(struct mlx4_dev *dev, int slave)
  2260. {
  2261. struct mlx4_priv *priv = mlx4_priv(dev);
  2262. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2263. struct list_head *qp_list =
  2264. &tracker->slave_list[slave].res_list[RES_QP];
  2265. struct res_qp *qp;
  2266. struct res_qp *tmp;
  2267. int state;
  2268. u64 in_param;
  2269. int qpn;
  2270. int err;
  2271. err = move_all_busy(dev, slave, RES_QP);
  2272. if (err)
  2273. mlx4_warn(dev, "rem_slave_qps: Could not move all qps to busy"
  2274. "for slave %d\n", slave);
  2275. spin_lock_irq(mlx4_tlock(dev));
  2276. list_for_each_entry_safe(qp, tmp, qp_list, com.list) {
  2277. spin_unlock_irq(mlx4_tlock(dev));
  2278. if (qp->com.owner == slave) {
  2279. qpn = qp->com.res_id;
  2280. detach_qp(dev, slave, qp);
  2281. state = qp->com.from_state;
  2282. while (state != 0) {
  2283. switch (state) {
  2284. case RES_QP_RESERVED:
  2285. spin_lock_irq(mlx4_tlock(dev));
  2286. radix_tree_delete(&tracker->res_tree[RES_QP],
  2287. qp->com.res_id);
  2288. list_del(&qp->com.list);
  2289. spin_unlock_irq(mlx4_tlock(dev));
  2290. kfree(qp);
  2291. state = 0;
  2292. break;
  2293. case RES_QP_MAPPED:
  2294. if (!valid_reserved(dev, slave, qpn))
  2295. __mlx4_qp_free_icm(dev, qpn);
  2296. state = RES_QP_RESERVED;
  2297. break;
  2298. case RES_QP_HW:
  2299. in_param = slave;
  2300. err = mlx4_cmd(dev, in_param,
  2301. qp->local_qpn, 2,
  2302. MLX4_CMD_2RST_QP,
  2303. MLX4_CMD_TIME_CLASS_A,
  2304. MLX4_CMD_NATIVE);
  2305. if (err)
  2306. mlx4_dbg(dev, "rem_slave_qps: failed"
  2307. " to move slave %d qpn %d to"
  2308. " reset\n", slave,
  2309. qp->local_qpn);
  2310. atomic_dec(&qp->rcq->ref_count);
  2311. atomic_dec(&qp->scq->ref_count);
  2312. atomic_dec(&qp->mtt->ref_count);
  2313. if (qp->srq)
  2314. atomic_dec(&qp->srq->ref_count);
  2315. state = RES_QP_MAPPED;
  2316. break;
  2317. default:
  2318. state = 0;
  2319. }
  2320. }
  2321. }
  2322. spin_lock_irq(mlx4_tlock(dev));
  2323. }
  2324. spin_unlock_irq(mlx4_tlock(dev));
  2325. }
  2326. static void rem_slave_srqs(struct mlx4_dev *dev, int slave)
  2327. {
  2328. struct mlx4_priv *priv = mlx4_priv(dev);
  2329. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2330. struct list_head *srq_list =
  2331. &tracker->slave_list[slave].res_list[RES_SRQ];
  2332. struct res_srq *srq;
  2333. struct res_srq *tmp;
  2334. int state;
  2335. u64 in_param;
  2336. LIST_HEAD(tlist);
  2337. int srqn;
  2338. int err;
  2339. err = move_all_busy(dev, slave, RES_SRQ);
  2340. if (err)
  2341. mlx4_warn(dev, "rem_slave_srqs: Could not move all srqs to "
  2342. "busy for slave %d\n", slave);
  2343. spin_lock_irq(mlx4_tlock(dev));
  2344. list_for_each_entry_safe(srq, tmp, srq_list, com.list) {
  2345. spin_unlock_irq(mlx4_tlock(dev));
  2346. if (srq->com.owner == slave) {
  2347. srqn = srq->com.res_id;
  2348. state = srq->com.from_state;
  2349. while (state != 0) {
  2350. switch (state) {
  2351. case RES_SRQ_ALLOCATED:
  2352. __mlx4_srq_free_icm(dev, srqn);
  2353. spin_lock_irq(mlx4_tlock(dev));
  2354. radix_tree_delete(&tracker->res_tree[RES_SRQ],
  2355. srqn);
  2356. list_del(&srq->com.list);
  2357. spin_unlock_irq(mlx4_tlock(dev));
  2358. kfree(srq);
  2359. state = 0;
  2360. break;
  2361. case RES_SRQ_HW:
  2362. in_param = slave;
  2363. err = mlx4_cmd(dev, in_param, srqn, 1,
  2364. MLX4_CMD_HW2SW_SRQ,
  2365. MLX4_CMD_TIME_CLASS_A,
  2366. MLX4_CMD_NATIVE);
  2367. if (err)
  2368. mlx4_dbg(dev, "rem_slave_srqs: failed"
  2369. " to move slave %d srq %d to"
  2370. " SW ownership\n",
  2371. slave, srqn);
  2372. atomic_dec(&srq->mtt->ref_count);
  2373. if (srq->cq)
  2374. atomic_dec(&srq->cq->ref_count);
  2375. state = RES_SRQ_ALLOCATED;
  2376. break;
  2377. default:
  2378. state = 0;
  2379. }
  2380. }
  2381. }
  2382. spin_lock_irq(mlx4_tlock(dev));
  2383. }
  2384. spin_unlock_irq(mlx4_tlock(dev));
  2385. }
  2386. static void rem_slave_cqs(struct mlx4_dev *dev, int slave)
  2387. {
  2388. struct mlx4_priv *priv = mlx4_priv(dev);
  2389. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2390. struct list_head *cq_list =
  2391. &tracker->slave_list[slave].res_list[RES_CQ];
  2392. struct res_cq *cq;
  2393. struct res_cq *tmp;
  2394. int state;
  2395. u64 in_param;
  2396. LIST_HEAD(tlist);
  2397. int cqn;
  2398. int err;
  2399. err = move_all_busy(dev, slave, RES_CQ);
  2400. if (err)
  2401. mlx4_warn(dev, "rem_slave_cqs: Could not move all cqs to "
  2402. "busy for slave %d\n", slave);
  2403. spin_lock_irq(mlx4_tlock(dev));
  2404. list_for_each_entry_safe(cq, tmp, cq_list, com.list) {
  2405. spin_unlock_irq(mlx4_tlock(dev));
  2406. if (cq->com.owner == slave && !atomic_read(&cq->ref_count)) {
  2407. cqn = cq->com.res_id;
  2408. state = cq->com.from_state;
  2409. while (state != 0) {
  2410. switch (state) {
  2411. case RES_CQ_ALLOCATED:
  2412. __mlx4_cq_free_icm(dev, cqn);
  2413. spin_lock_irq(mlx4_tlock(dev));
  2414. radix_tree_delete(&tracker->res_tree[RES_CQ],
  2415. cqn);
  2416. list_del(&cq->com.list);
  2417. spin_unlock_irq(mlx4_tlock(dev));
  2418. kfree(cq);
  2419. state = 0;
  2420. break;
  2421. case RES_CQ_HW:
  2422. in_param = slave;
  2423. err = mlx4_cmd(dev, in_param, cqn, 1,
  2424. MLX4_CMD_HW2SW_CQ,
  2425. MLX4_CMD_TIME_CLASS_A,
  2426. MLX4_CMD_NATIVE);
  2427. if (err)
  2428. mlx4_dbg(dev, "rem_slave_cqs: failed"
  2429. " to move slave %d cq %d to"
  2430. " SW ownership\n",
  2431. slave, cqn);
  2432. atomic_dec(&cq->mtt->ref_count);
  2433. state = RES_CQ_ALLOCATED;
  2434. break;
  2435. default:
  2436. state = 0;
  2437. }
  2438. }
  2439. }
  2440. spin_lock_irq(mlx4_tlock(dev));
  2441. }
  2442. spin_unlock_irq(mlx4_tlock(dev));
  2443. }
  2444. static void rem_slave_mrs(struct mlx4_dev *dev, int slave)
  2445. {
  2446. struct mlx4_priv *priv = mlx4_priv(dev);
  2447. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2448. struct list_head *mpt_list =
  2449. &tracker->slave_list[slave].res_list[RES_MPT];
  2450. struct res_mpt *mpt;
  2451. struct res_mpt *tmp;
  2452. int state;
  2453. u64 in_param;
  2454. LIST_HEAD(tlist);
  2455. int mptn;
  2456. int err;
  2457. err = move_all_busy(dev, slave, RES_MPT);
  2458. if (err)
  2459. mlx4_warn(dev, "rem_slave_mrs: Could not move all mpts to "
  2460. "busy for slave %d\n", slave);
  2461. spin_lock_irq(mlx4_tlock(dev));
  2462. list_for_each_entry_safe(mpt, tmp, mpt_list, com.list) {
  2463. spin_unlock_irq(mlx4_tlock(dev));
  2464. if (mpt->com.owner == slave) {
  2465. mptn = mpt->com.res_id;
  2466. state = mpt->com.from_state;
  2467. while (state != 0) {
  2468. switch (state) {
  2469. case RES_MPT_RESERVED:
  2470. __mlx4_mr_release(dev, mpt->key);
  2471. spin_lock_irq(mlx4_tlock(dev));
  2472. radix_tree_delete(&tracker->res_tree[RES_MPT],
  2473. mptn);
  2474. list_del(&mpt->com.list);
  2475. spin_unlock_irq(mlx4_tlock(dev));
  2476. kfree(mpt);
  2477. state = 0;
  2478. break;
  2479. case RES_MPT_MAPPED:
  2480. __mlx4_mr_free_icm(dev, mpt->key);
  2481. state = RES_MPT_RESERVED;
  2482. break;
  2483. case RES_MPT_HW:
  2484. in_param = slave;
  2485. err = mlx4_cmd(dev, in_param, mptn, 0,
  2486. MLX4_CMD_HW2SW_MPT,
  2487. MLX4_CMD_TIME_CLASS_A,
  2488. MLX4_CMD_NATIVE);
  2489. if (err)
  2490. mlx4_dbg(dev, "rem_slave_mrs: failed"
  2491. " to move slave %d mpt %d to"
  2492. " SW ownership\n",
  2493. slave, mptn);
  2494. if (mpt->mtt)
  2495. atomic_dec(&mpt->mtt->ref_count);
  2496. state = RES_MPT_MAPPED;
  2497. break;
  2498. default:
  2499. state = 0;
  2500. }
  2501. }
  2502. }
  2503. spin_lock_irq(mlx4_tlock(dev));
  2504. }
  2505. spin_unlock_irq(mlx4_tlock(dev));
  2506. }
  2507. static void rem_slave_mtts(struct mlx4_dev *dev, int slave)
  2508. {
  2509. struct mlx4_priv *priv = mlx4_priv(dev);
  2510. struct mlx4_resource_tracker *tracker =
  2511. &priv->mfunc.master.res_tracker;
  2512. struct list_head *mtt_list =
  2513. &tracker->slave_list[slave].res_list[RES_MTT];
  2514. struct res_mtt *mtt;
  2515. struct res_mtt *tmp;
  2516. int state;
  2517. LIST_HEAD(tlist);
  2518. int base;
  2519. int err;
  2520. err = move_all_busy(dev, slave, RES_MTT);
  2521. if (err)
  2522. mlx4_warn(dev, "rem_slave_mtts: Could not move all mtts to "
  2523. "busy for slave %d\n", slave);
  2524. spin_lock_irq(mlx4_tlock(dev));
  2525. list_for_each_entry_safe(mtt, tmp, mtt_list, com.list) {
  2526. spin_unlock_irq(mlx4_tlock(dev));
  2527. if (mtt->com.owner == slave) {
  2528. base = mtt->com.res_id;
  2529. state = mtt->com.from_state;
  2530. while (state != 0) {
  2531. switch (state) {
  2532. case RES_MTT_ALLOCATED:
  2533. __mlx4_free_mtt_range(dev, base,
  2534. mtt->order);
  2535. spin_lock_irq(mlx4_tlock(dev));
  2536. radix_tree_delete(&tracker->res_tree[RES_MTT],
  2537. base);
  2538. list_del(&mtt->com.list);
  2539. spin_unlock_irq(mlx4_tlock(dev));
  2540. kfree(mtt);
  2541. state = 0;
  2542. break;
  2543. default:
  2544. state = 0;
  2545. }
  2546. }
  2547. }
  2548. spin_lock_irq(mlx4_tlock(dev));
  2549. }
  2550. spin_unlock_irq(mlx4_tlock(dev));
  2551. }
  2552. static void rem_slave_eqs(struct mlx4_dev *dev, int slave)
  2553. {
  2554. struct mlx4_priv *priv = mlx4_priv(dev);
  2555. struct mlx4_resource_tracker *tracker = &priv->mfunc.master.res_tracker;
  2556. struct list_head *eq_list =
  2557. &tracker->slave_list[slave].res_list[RES_EQ];
  2558. struct res_eq *eq;
  2559. struct res_eq *tmp;
  2560. int err;
  2561. int state;
  2562. LIST_HEAD(tlist);
  2563. int eqn;
  2564. struct mlx4_cmd_mailbox *mailbox;
  2565. err = move_all_busy(dev, slave, RES_EQ);
  2566. if (err)
  2567. mlx4_warn(dev, "rem_slave_eqs: Could not move all eqs to "
  2568. "busy for slave %d\n", slave);
  2569. spin_lock_irq(mlx4_tlock(dev));
  2570. list_for_each_entry_safe(eq, tmp, eq_list, com.list) {
  2571. spin_unlock_irq(mlx4_tlock(dev));
  2572. if (eq->com.owner == slave) {
  2573. eqn = eq->com.res_id;
  2574. state = eq->com.from_state;
  2575. while (state != 0) {
  2576. switch (state) {
  2577. case RES_EQ_RESERVED:
  2578. spin_lock_irq(mlx4_tlock(dev));
  2579. radix_tree_delete(&tracker->res_tree[RES_EQ],
  2580. eqn);
  2581. list_del(&eq->com.list);
  2582. spin_unlock_irq(mlx4_tlock(dev));
  2583. kfree(eq);
  2584. state = 0;
  2585. break;
  2586. case RES_EQ_HW:
  2587. mailbox = mlx4_alloc_cmd_mailbox(dev);
  2588. if (IS_ERR(mailbox)) {
  2589. cond_resched();
  2590. continue;
  2591. }
  2592. err = mlx4_cmd_box(dev, slave, 0,
  2593. eqn & 0xff, 0,
  2594. MLX4_CMD_HW2SW_EQ,
  2595. MLX4_CMD_TIME_CLASS_A,
  2596. MLX4_CMD_NATIVE);
  2597. mlx4_dbg(dev, "rem_slave_eqs: failed"
  2598. " to move slave %d eqs %d to"
  2599. " SW ownership\n", slave, eqn);
  2600. mlx4_free_cmd_mailbox(dev, mailbox);
  2601. if (!err) {
  2602. atomic_dec(&eq->mtt->ref_count);
  2603. state = RES_EQ_RESERVED;
  2604. }
  2605. break;
  2606. default:
  2607. state = 0;
  2608. }
  2609. }
  2610. }
  2611. spin_lock_irq(mlx4_tlock(dev));
  2612. }
  2613. spin_unlock_irq(mlx4_tlock(dev));
  2614. }
  2615. void mlx4_delete_all_resources_for_slave(struct mlx4_dev *dev, int slave)
  2616. {
  2617. struct mlx4_priv *priv = mlx4_priv(dev);
  2618. mutex_lock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2619. /*VLAN*/
  2620. rem_slave_macs(dev, slave);
  2621. rem_slave_qps(dev, slave);
  2622. rem_slave_srqs(dev, slave);
  2623. rem_slave_cqs(dev, slave);
  2624. rem_slave_mrs(dev, slave);
  2625. rem_slave_eqs(dev, slave);
  2626. rem_slave_mtts(dev, slave);
  2627. mutex_unlock(&priv->mfunc.master.res_tracker.slave_list[slave].mutex);
  2628. }