dm_common.c 52 KB

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  1. /******************************************************************************
  2. *
  3. * Copyright(c) 2009-2012 Realtek Corporation.
  4. *
  5. * This program is free software; you can redistribute it and/or modify it
  6. * under the terms of version 2 of the GNU General Public License as
  7. * published by the Free Software Foundation.
  8. *
  9. * This program is distributed in the hope that it will be useful, but WITHOUT
  10. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  12. * more details.
  13. *
  14. * You should have received a copy of the GNU General Public License along with
  15. * this program; if not, write to the Free Software Foundation, Inc.,
  16. * 51 Franklin Street, Fifth Floor, Boston, MA 02110, USA
  17. *
  18. * The full GNU General Public License is included in this distribution in the
  19. * file called LICENSE.
  20. *
  21. * Contact Information:
  22. * wlanfae <wlanfae@realtek.com>
  23. * Realtek Corporation, No. 2, Innovation Road II, Hsinchu Science Park,
  24. * Hsinchu 300, Taiwan.
  25. *
  26. * Larry Finger <Larry.Finger@lwfinger.net>
  27. *
  28. *****************************************************************************/
  29. #include <linux/export.h>
  30. #include "dm_common.h"
  31. #include "phy_common.h"
  32. #include "../pci.h"
  33. #include "../base.h"
  34. struct dig_t dm_digtable;
  35. static struct ps_t dm_pstable;
  36. #define BT_RSSI_STATE_NORMAL_POWER BIT_OFFSET_LEN_MASK_32(0, 1)
  37. #define BT_RSSI_STATE_AMDPU_OFF BIT_OFFSET_LEN_MASK_32(1, 1)
  38. #define BT_RSSI_STATE_SPECIAL_LOW BIT_OFFSET_LEN_MASK_32(2, 1)
  39. #define BT_RSSI_STATE_BG_EDCA_LOW BIT_OFFSET_LEN_MASK_32(3, 1)
  40. #define BT_RSSI_STATE_TXPOWER_LOW BIT_OFFSET_LEN_MASK_32(4, 1)
  41. #define RTLPRIV (struct rtl_priv *)
  42. #define GET_UNDECORATED_AVERAGE_RSSI(_priv) \
  43. ((RTLPRIV(_priv))->mac80211.opmode == \
  44. NL80211_IFTYPE_ADHOC) ? \
  45. ((RTLPRIV(_priv))->dm.entry_min_undecoratedsmoothed_pwdb) : \
  46. ((RTLPRIV(_priv))->dm.undecorated_smoothed_pwdb)
  47. static const u32 ofdmswing_table[OFDM_TABLE_SIZE] = {
  48. 0x7f8001fe,
  49. 0x788001e2,
  50. 0x71c001c7,
  51. 0x6b8001ae,
  52. 0x65400195,
  53. 0x5fc0017f,
  54. 0x5a400169,
  55. 0x55400155,
  56. 0x50800142,
  57. 0x4c000130,
  58. 0x47c0011f,
  59. 0x43c0010f,
  60. 0x40000100,
  61. 0x3c8000f2,
  62. 0x390000e4,
  63. 0x35c000d7,
  64. 0x32c000cb,
  65. 0x300000c0,
  66. 0x2d4000b5,
  67. 0x2ac000ab,
  68. 0x288000a2,
  69. 0x26000098,
  70. 0x24000090,
  71. 0x22000088,
  72. 0x20000080,
  73. 0x1e400079,
  74. 0x1c800072,
  75. 0x1b00006c,
  76. 0x19800066,
  77. 0x18000060,
  78. 0x16c0005b,
  79. 0x15800056,
  80. 0x14400051,
  81. 0x1300004c,
  82. 0x12000048,
  83. 0x11000044,
  84. 0x10000040,
  85. };
  86. static const u8 cckswing_table_ch1ch13[CCK_TABLE_SIZE][8] = {
  87. {0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04},
  88. {0x33, 0x32, 0x2b, 0x23, 0x1a, 0x11, 0x08, 0x04},
  89. {0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03},
  90. {0x2d, 0x2d, 0x27, 0x1f, 0x18, 0x0f, 0x08, 0x03},
  91. {0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03},
  92. {0x28, 0x28, 0x22, 0x1c, 0x15, 0x0d, 0x07, 0x03},
  93. {0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03},
  94. {0x24, 0x23, 0x1f, 0x19, 0x13, 0x0c, 0x06, 0x03},
  95. {0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02},
  96. {0x20, 0x20, 0x1b, 0x16, 0x11, 0x08, 0x05, 0x02},
  97. {0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02},
  98. {0x1d, 0x1c, 0x18, 0x14, 0x0f, 0x0a, 0x05, 0x02},
  99. {0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02},
  100. {0x1a, 0x19, 0x16, 0x12, 0x0d, 0x09, 0x04, 0x02},
  101. {0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02},
  102. {0x17, 0x16, 0x13, 0x10, 0x0c, 0x08, 0x04, 0x02},
  103. {0x16, 0x15, 0x12, 0x0f, 0x0b, 0x07, 0x04, 0x01},
  104. {0x14, 0x14, 0x11, 0x0e, 0x0b, 0x07, 0x03, 0x02},
  105. {0x13, 0x13, 0x10, 0x0d, 0x0a, 0x06, 0x03, 0x01},
  106. {0x12, 0x12, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  107. {0x11, 0x11, 0x0f, 0x0c, 0x09, 0x06, 0x03, 0x01},
  108. {0x10, 0x10, 0x0e, 0x0b, 0x08, 0x05, 0x03, 0x01},
  109. {0x0f, 0x0f, 0x0d, 0x0b, 0x08, 0x05, 0x03, 0x01},
  110. {0x0e, 0x0e, 0x0c, 0x0a, 0x08, 0x05, 0x02, 0x01},
  111. {0x0d, 0x0d, 0x0c, 0x0a, 0x07, 0x05, 0x02, 0x01},
  112. {0x0d, 0x0c, 0x0b, 0x09, 0x07, 0x04, 0x02, 0x01},
  113. {0x0c, 0x0c, 0x0a, 0x09, 0x06, 0x04, 0x02, 0x01},
  114. {0x0b, 0x0b, 0x0a, 0x08, 0x06, 0x04, 0x02, 0x01},
  115. {0x0b, 0x0a, 0x09, 0x08, 0x06, 0x04, 0x02, 0x01},
  116. {0x0a, 0x0a, 0x09, 0x07, 0x05, 0x03, 0x02, 0x01},
  117. {0x0a, 0x09, 0x08, 0x07, 0x05, 0x03, 0x02, 0x01},
  118. {0x09, 0x09, 0x08, 0x06, 0x05, 0x03, 0x01, 0x01},
  119. {0x09, 0x08, 0x07, 0x06, 0x04, 0x03, 0x01, 0x01}
  120. };
  121. static const u8 cckswing_table_ch14[CCK_TABLE_SIZE][8] = {
  122. {0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00},
  123. {0x33, 0x32, 0x2b, 0x19, 0x00, 0x00, 0x00, 0x00},
  124. {0x30, 0x2f, 0x29, 0x18, 0x00, 0x00, 0x00, 0x00},
  125. {0x2d, 0x2d, 0x17, 0x17, 0x00, 0x00, 0x00, 0x00},
  126. {0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00},
  127. {0x28, 0x28, 0x24, 0x14, 0x00, 0x00, 0x00, 0x00},
  128. {0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00},
  129. {0x24, 0x23, 0x1f, 0x12, 0x00, 0x00, 0x00, 0x00},
  130. {0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00},
  131. {0x20, 0x20, 0x1b, 0x10, 0x00, 0x00, 0x00, 0x00},
  132. {0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00},
  133. {0x1d, 0x1c, 0x18, 0x0e, 0x00, 0x00, 0x00, 0x00},
  134. {0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00},
  135. {0x1a, 0x19, 0x16, 0x0d, 0x00, 0x00, 0x00, 0x00},
  136. {0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00},
  137. {0x17, 0x16, 0x13, 0x0b, 0x00, 0x00, 0x00, 0x00},
  138. {0x16, 0x15, 0x12, 0x0b, 0x00, 0x00, 0x00, 0x00},
  139. {0x14, 0x14, 0x11, 0x0a, 0x00, 0x00, 0x00, 0x00},
  140. {0x13, 0x13, 0x10, 0x0a, 0x00, 0x00, 0x00, 0x00},
  141. {0x12, 0x12, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  142. {0x11, 0x11, 0x0f, 0x09, 0x00, 0x00, 0x00, 0x00},
  143. {0x10, 0x10, 0x0e, 0x08, 0x00, 0x00, 0x00, 0x00},
  144. {0x0f, 0x0f, 0x0d, 0x08, 0x00, 0x00, 0x00, 0x00},
  145. {0x0e, 0x0e, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  146. {0x0d, 0x0d, 0x0c, 0x07, 0x00, 0x00, 0x00, 0x00},
  147. {0x0d, 0x0c, 0x0b, 0x06, 0x00, 0x00, 0x00, 0x00},
  148. {0x0c, 0x0c, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  149. {0x0b, 0x0b, 0x0a, 0x06, 0x00, 0x00, 0x00, 0x00},
  150. {0x0b, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  151. {0x0a, 0x0a, 0x09, 0x05, 0x00, 0x00, 0x00, 0x00},
  152. {0x0a, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  153. {0x09, 0x09, 0x08, 0x05, 0x00, 0x00, 0x00, 0x00},
  154. {0x09, 0x08, 0x07, 0x04, 0x00, 0x00, 0x00, 0x00}
  155. };
  156. static void rtl92c_dm_diginit(struct ieee80211_hw *hw)
  157. {
  158. dm_digtable.dig_enable_flag = true;
  159. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  160. dm_digtable.cur_igvalue = 0x20;
  161. dm_digtable.pre_igvalue = 0x0;
  162. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  163. dm_digtable.presta_connectstate = DIG_STA_DISCONNECT;
  164. dm_digtable.curmultista_connectstate = DIG_MULTISTA_DISCONNECT;
  165. dm_digtable.rssi_lowthresh = DM_DIG_THRESH_LOW;
  166. dm_digtable.rssi_highthresh = DM_DIG_THRESH_HIGH;
  167. dm_digtable.fa_lowthresh = DM_FALSEALARM_THRESH_LOW;
  168. dm_digtable.fa_highthresh = DM_FALSEALARM_THRESH_HIGH;
  169. dm_digtable.rx_gain_range_max = DM_DIG_MAX;
  170. dm_digtable.rx_gain_range_min = DM_DIG_MIN;
  171. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  172. dm_digtable.backoff_val_range_max = DM_DIG_BACKOFF_MAX;
  173. dm_digtable.backoff_val_range_min = DM_DIG_BACKOFF_MIN;
  174. dm_digtable.pre_cck_pd_state = CCK_PD_STAGE_MAX;
  175. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  176. }
  177. static u8 rtl92c_dm_initial_gain_min_pwdb(struct ieee80211_hw *hw)
  178. {
  179. struct rtl_priv *rtlpriv = rtl_priv(hw);
  180. long rssi_val_min = 0;
  181. if ((dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) &&
  182. (dm_digtable.cursta_connectctate == DIG_STA_CONNECT)) {
  183. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb != 0)
  184. rssi_val_min =
  185. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb >
  186. rtlpriv->dm.undecorated_smoothed_pwdb) ?
  187. rtlpriv->dm.undecorated_smoothed_pwdb :
  188. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  189. else
  190. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  191. } else if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT ||
  192. dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT) {
  193. rssi_val_min = rtlpriv->dm.undecorated_smoothed_pwdb;
  194. } else if (dm_digtable.curmultista_connectstate ==
  195. DIG_MULTISTA_CONNECT) {
  196. rssi_val_min = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  197. }
  198. return (u8) rssi_val_min;
  199. }
  200. static void rtl92c_dm_false_alarm_counter_statistics(struct ieee80211_hw *hw)
  201. {
  202. u32 ret_value;
  203. struct rtl_priv *rtlpriv = rtl_priv(hw);
  204. struct false_alarm_statistics *falsealm_cnt = &(rtlpriv->falsealm_cnt);
  205. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER1, MASKDWORD);
  206. falsealm_cnt->cnt_parity_fail = ((ret_value & 0xffff0000) >> 16);
  207. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER2, MASKDWORD);
  208. falsealm_cnt->cnt_rate_illegal = (ret_value & 0xffff);
  209. falsealm_cnt->cnt_crc8_fail = ((ret_value & 0xffff0000) >> 16);
  210. ret_value = rtl_get_bbreg(hw, ROFDM_PHYCOUNTER3, MASKDWORD);
  211. falsealm_cnt->cnt_mcs_fail = (ret_value & 0xffff);
  212. falsealm_cnt->cnt_ofdm_fail = falsealm_cnt->cnt_parity_fail +
  213. falsealm_cnt->cnt_rate_illegal +
  214. falsealm_cnt->cnt_crc8_fail + falsealm_cnt->cnt_mcs_fail;
  215. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, BIT(14), 1);
  216. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERLOWER, MASKBYTE0);
  217. falsealm_cnt->cnt_cck_fail = ret_value;
  218. ret_value = rtl_get_bbreg(hw, RCCK0_FACOUNTERUPPER, MASKBYTE3);
  219. falsealm_cnt->cnt_cck_fail += (ret_value & 0xff) << 8;
  220. falsealm_cnt->cnt_all = (falsealm_cnt->cnt_parity_fail +
  221. falsealm_cnt->cnt_rate_illegal +
  222. falsealm_cnt->cnt_crc8_fail +
  223. falsealm_cnt->cnt_mcs_fail +
  224. falsealm_cnt->cnt_cck_fail);
  225. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 1);
  226. rtl_set_bbreg(hw, ROFDM1_LSTF, 0x08000000, 0);
  227. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 0);
  228. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT, 0x0000c000, 2);
  229. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  230. "cnt_parity_fail = %d, cnt_rate_illegal = %d, cnt_crc8_fail = %d, cnt_mcs_fail = %d\n",
  231. falsealm_cnt->cnt_parity_fail,
  232. falsealm_cnt->cnt_rate_illegal,
  233. falsealm_cnt->cnt_crc8_fail, falsealm_cnt->cnt_mcs_fail);
  234. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  235. "cnt_ofdm_fail = %x, cnt_cck_fail = %x, cnt_all = %x\n",
  236. falsealm_cnt->cnt_ofdm_fail,
  237. falsealm_cnt->cnt_cck_fail, falsealm_cnt->cnt_all);
  238. }
  239. static void rtl92c_dm_ctrl_initgain_by_fa(struct ieee80211_hw *hw)
  240. {
  241. struct rtl_priv *rtlpriv = rtl_priv(hw);
  242. u8 value_igi = dm_digtable.cur_igvalue;
  243. if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH0)
  244. value_igi--;
  245. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH1)
  246. value_igi += 0;
  247. else if (rtlpriv->falsealm_cnt.cnt_all < DM_DIG_FA_TH2)
  248. value_igi++;
  249. else if (rtlpriv->falsealm_cnt.cnt_all >= DM_DIG_FA_TH2)
  250. value_igi += 2;
  251. if (value_igi > DM_DIG_FA_UPPER)
  252. value_igi = DM_DIG_FA_UPPER;
  253. else if (value_igi < DM_DIG_FA_LOWER)
  254. value_igi = DM_DIG_FA_LOWER;
  255. if (rtlpriv->falsealm_cnt.cnt_all > 10000)
  256. value_igi = 0x32;
  257. dm_digtable.cur_igvalue = value_igi;
  258. rtl92c_dm_write_dig(hw);
  259. }
  260. static void rtl92c_dm_ctrl_initgain_by_rssi(struct ieee80211_hw *hw)
  261. {
  262. struct rtl_priv *rtlpriv = rtl_priv(hw);
  263. if (rtlpriv->falsealm_cnt.cnt_all > dm_digtable.fa_highthresh) {
  264. if ((dm_digtable.backoff_val - 2) <
  265. dm_digtable.backoff_val_range_min)
  266. dm_digtable.backoff_val =
  267. dm_digtable.backoff_val_range_min;
  268. else
  269. dm_digtable.backoff_val -= 2;
  270. } else if (rtlpriv->falsealm_cnt.cnt_all < dm_digtable.fa_lowthresh) {
  271. if ((dm_digtable.backoff_val + 2) >
  272. dm_digtable.backoff_val_range_max)
  273. dm_digtable.backoff_val =
  274. dm_digtable.backoff_val_range_max;
  275. else
  276. dm_digtable.backoff_val += 2;
  277. }
  278. if ((dm_digtable.rssi_val_min + 10 - dm_digtable.backoff_val) >
  279. dm_digtable.rx_gain_range_max)
  280. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_max;
  281. else if ((dm_digtable.rssi_val_min + 10 -
  282. dm_digtable.backoff_val) < dm_digtable.rx_gain_range_min)
  283. dm_digtable.cur_igvalue = dm_digtable.rx_gain_range_min;
  284. else
  285. dm_digtable.cur_igvalue = dm_digtable.rssi_val_min + 10 -
  286. dm_digtable.backoff_val;
  287. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  288. "rssi_val_min = %x backoff_val %x\n",
  289. dm_digtable.rssi_val_min, dm_digtable.backoff_val);
  290. rtl92c_dm_write_dig(hw);
  291. }
  292. static void rtl92c_dm_initial_gain_multi_sta(struct ieee80211_hw *hw)
  293. {
  294. static u8 initialized; /* initialized to false */
  295. struct rtl_priv *rtlpriv = rtl_priv(hw);
  296. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  297. long rssi_strength = rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  298. bool multi_sta = false;
  299. if (mac->opmode == NL80211_IFTYPE_ADHOC)
  300. multi_sta = true;
  301. if (!multi_sta ||
  302. dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  303. initialized = false;
  304. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  305. return;
  306. } else if (initialized == false) {
  307. initialized = true;
  308. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  309. dm_digtable.cur_igvalue = 0x20;
  310. rtl92c_dm_write_dig(hw);
  311. }
  312. if (dm_digtable.curmultista_connectstate == DIG_MULTISTA_CONNECT) {
  313. if ((rssi_strength < dm_digtable.rssi_lowthresh) &&
  314. (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_1)) {
  315. if (dm_digtable.dig_ext_port_stage ==
  316. DIG_EXT_PORT_STAGE_2) {
  317. dm_digtable.cur_igvalue = 0x20;
  318. rtl92c_dm_write_dig(hw);
  319. }
  320. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_1;
  321. } else if (rssi_strength > dm_digtable.rssi_highthresh) {
  322. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_2;
  323. rtl92c_dm_ctrl_initgain_by_fa(hw);
  324. }
  325. } else if (dm_digtable.dig_ext_port_stage != DIG_EXT_PORT_STAGE_0) {
  326. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_0;
  327. dm_digtable.cur_igvalue = 0x20;
  328. rtl92c_dm_write_dig(hw);
  329. }
  330. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  331. "curmultista_connectstate = %x dig_ext_port_stage %x\n",
  332. dm_digtable.curmultista_connectstate,
  333. dm_digtable.dig_ext_port_stage);
  334. }
  335. static void rtl92c_dm_initial_gain_sta(struct ieee80211_hw *hw)
  336. {
  337. struct rtl_priv *rtlpriv = rtl_priv(hw);
  338. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE,
  339. "presta_connectstate = %x, cursta_connectctate = %x\n",
  340. dm_digtable.presta_connectstate,
  341. dm_digtable.cursta_connectctate);
  342. if (dm_digtable.presta_connectstate == dm_digtable.cursta_connectctate
  343. || dm_digtable.cursta_connectctate == DIG_STA_BEFORE_CONNECT
  344. || dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  345. if (dm_digtable.cursta_connectctate != DIG_STA_DISCONNECT) {
  346. dm_digtable.rssi_val_min =
  347. rtl92c_dm_initial_gain_min_pwdb(hw);
  348. rtl92c_dm_ctrl_initgain_by_rssi(hw);
  349. }
  350. } else {
  351. dm_digtable.rssi_val_min = 0;
  352. dm_digtable.dig_ext_port_stage = DIG_EXT_PORT_STAGE_MAX;
  353. dm_digtable.backoff_val = DM_DIG_BACKOFF_DEFAULT;
  354. dm_digtable.cur_igvalue = 0x20;
  355. dm_digtable.pre_igvalue = 0;
  356. rtl92c_dm_write_dig(hw);
  357. }
  358. }
  359. static void rtl92c_dm_cck_packet_detection_thresh(struct ieee80211_hw *hw)
  360. {
  361. struct rtl_priv *rtlpriv = rtl_priv(hw);
  362. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  363. if (dm_digtable.cursta_connectctate == DIG_STA_CONNECT) {
  364. dm_digtable.rssi_val_min = rtl92c_dm_initial_gain_min_pwdb(hw);
  365. if (dm_digtable.pre_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  366. if (dm_digtable.rssi_val_min <= 25)
  367. dm_digtable.cur_cck_pd_state =
  368. CCK_PD_STAGE_LowRssi;
  369. else
  370. dm_digtable.cur_cck_pd_state =
  371. CCK_PD_STAGE_HighRssi;
  372. } else {
  373. if (dm_digtable.rssi_val_min <= 20)
  374. dm_digtable.cur_cck_pd_state =
  375. CCK_PD_STAGE_LowRssi;
  376. else
  377. dm_digtable.cur_cck_pd_state =
  378. CCK_PD_STAGE_HighRssi;
  379. }
  380. } else {
  381. dm_digtable.cur_cck_pd_state = CCK_PD_STAGE_MAX;
  382. }
  383. if (dm_digtable.pre_cck_pd_state != dm_digtable.cur_cck_pd_state) {
  384. if (dm_digtable.cur_cck_pd_state == CCK_PD_STAGE_LowRssi) {
  385. if (rtlpriv->falsealm_cnt.cnt_cck_fail > 800)
  386. dm_digtable.cur_cck_fa_state =
  387. CCK_FA_STAGE_High;
  388. else
  389. dm_digtable.cur_cck_fa_state = CCK_FA_STAGE_Low;
  390. if (dm_digtable.pre_cck_fa_state !=
  391. dm_digtable.cur_cck_fa_state) {
  392. if (dm_digtable.cur_cck_fa_state ==
  393. CCK_FA_STAGE_Low)
  394. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  395. 0x83);
  396. else
  397. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2,
  398. 0xcd);
  399. dm_digtable.pre_cck_fa_state =
  400. dm_digtable.cur_cck_fa_state;
  401. }
  402. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x40);
  403. if (IS_92C_SERIAL(rtlhal->version))
  404. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  405. MASKBYTE2, 0xd7);
  406. } else {
  407. rtl_set_bbreg(hw, RCCK0_CCA, MASKBYTE2, 0xcd);
  408. rtl_set_bbreg(hw, RCCK0_SYSTEM, MASKBYTE1, 0x47);
  409. if (IS_92C_SERIAL(rtlhal->version))
  410. rtl_set_bbreg(hw, RCCK0_FALSEALARMREPORT,
  411. MASKBYTE2, 0xd3);
  412. }
  413. dm_digtable.pre_cck_pd_state = dm_digtable.cur_cck_pd_state;
  414. }
  415. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "CCKPDStage=%x\n",
  416. dm_digtable.cur_cck_pd_state);
  417. RT_TRACE(rtlpriv, COMP_DIG, DBG_TRACE, "is92C=%x\n",
  418. IS_92C_SERIAL(rtlhal->version));
  419. }
  420. static void rtl92c_dm_ctrl_initgain_by_twoport(struct ieee80211_hw *hw)
  421. {
  422. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  423. if (mac->act_scanning)
  424. return;
  425. if (mac->link_state >= MAC80211_LINKED)
  426. dm_digtable.cursta_connectctate = DIG_STA_CONNECT;
  427. else
  428. dm_digtable.cursta_connectctate = DIG_STA_DISCONNECT;
  429. rtl92c_dm_initial_gain_sta(hw);
  430. rtl92c_dm_initial_gain_multi_sta(hw);
  431. rtl92c_dm_cck_packet_detection_thresh(hw);
  432. dm_digtable.presta_connectstate = dm_digtable.cursta_connectctate;
  433. }
  434. static void rtl92c_dm_dig(struct ieee80211_hw *hw)
  435. {
  436. struct rtl_priv *rtlpriv = rtl_priv(hw);
  437. if (rtlpriv->dm.dm_initialgain_enable == false)
  438. return;
  439. if (dm_digtable.dig_enable_flag == false)
  440. return;
  441. rtl92c_dm_ctrl_initgain_by_twoport(hw);
  442. }
  443. static void rtl92c_dm_init_dynamic_txpower(struct ieee80211_hw *hw)
  444. {
  445. struct rtl_priv *rtlpriv = rtl_priv(hw);
  446. rtlpriv->dm.dynamic_txpower_enable = false;
  447. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  448. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  449. }
  450. void rtl92c_dm_write_dig(struct ieee80211_hw *hw)
  451. {
  452. struct rtl_priv *rtlpriv = rtl_priv(hw);
  453. RT_TRACE(rtlpriv, COMP_DIG, DBG_LOUD,
  454. "cur_igvalue = 0x%x, pre_igvalue = 0x%x, backoff_val = %d\n",
  455. dm_digtable.cur_igvalue, dm_digtable.pre_igvalue,
  456. dm_digtable.backoff_val);
  457. if (dm_digtable.pre_igvalue != dm_digtable.cur_igvalue) {
  458. rtl_set_bbreg(hw, ROFDM0_XAAGCCORE1, 0x7f,
  459. dm_digtable.cur_igvalue);
  460. rtl_set_bbreg(hw, ROFDM0_XBAGCCORE1, 0x7f,
  461. dm_digtable.cur_igvalue);
  462. dm_digtable.pre_igvalue = dm_digtable.cur_igvalue;
  463. }
  464. }
  465. EXPORT_SYMBOL(rtl92c_dm_write_dig);
  466. static void rtl92c_dm_pwdb_monitor(struct ieee80211_hw *hw)
  467. {
  468. struct rtl_priv *rtlpriv = rtl_priv(hw);
  469. long tmpentry_max_pwdb = 0, tmpentry_min_pwdb = 0xff;
  470. u8 h2c_parameter[3] = { 0 };
  471. return;
  472. if (tmpentry_max_pwdb != 0) {
  473. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb =
  474. tmpentry_max_pwdb;
  475. } else {
  476. rtlpriv->dm.entry_max_undecoratedsmoothed_pwdb = 0;
  477. }
  478. if (tmpentry_min_pwdb != 0xff) {
  479. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb =
  480. tmpentry_min_pwdb;
  481. } else {
  482. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb = 0;
  483. }
  484. h2c_parameter[2] = (u8) (rtlpriv->dm.undecorated_smoothed_pwdb & 0xFF);
  485. h2c_parameter[0] = 0;
  486. rtl92c_fill_h2c_cmd(hw, H2C_RSSI_REPORT, 3, h2c_parameter);
  487. }
  488. void rtl92c_dm_init_edca_turbo(struct ieee80211_hw *hw)
  489. {
  490. struct rtl_priv *rtlpriv = rtl_priv(hw);
  491. rtlpriv->dm.current_turbo_edca = false;
  492. rtlpriv->dm.is_any_nonbepkts = false;
  493. rtlpriv->dm.is_cur_rdlstate = false;
  494. }
  495. EXPORT_SYMBOL(rtl92c_dm_init_edca_turbo);
  496. static void rtl92c_dm_check_edca_turbo(struct ieee80211_hw *hw)
  497. {
  498. struct rtl_priv *rtlpriv = rtl_priv(hw);
  499. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  500. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  501. static u64 last_txok_cnt;
  502. static u64 last_rxok_cnt;
  503. static u32 last_bt_edca_ul;
  504. static u32 last_bt_edca_dl;
  505. u64 cur_txok_cnt = 0;
  506. u64 cur_rxok_cnt = 0;
  507. u32 edca_be_ul = 0x5ea42b;
  508. u32 edca_be_dl = 0x5ea42b;
  509. bool bt_change_edca = false;
  510. if ((last_bt_edca_ul != rtlpcipriv->bt_coexist.bt_edca_ul) ||
  511. (last_bt_edca_dl != rtlpcipriv->bt_coexist.bt_edca_dl)) {
  512. rtlpriv->dm.current_turbo_edca = false;
  513. last_bt_edca_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  514. last_bt_edca_dl = rtlpcipriv->bt_coexist.bt_edca_dl;
  515. }
  516. if (rtlpcipriv->bt_coexist.bt_edca_ul != 0) {
  517. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_ul;
  518. bt_change_edca = true;
  519. }
  520. if (rtlpcipriv->bt_coexist.bt_edca_dl != 0) {
  521. edca_be_ul = rtlpcipriv->bt_coexist.bt_edca_dl;
  522. bt_change_edca = true;
  523. }
  524. if (mac->link_state != MAC80211_LINKED) {
  525. rtlpriv->dm.current_turbo_edca = false;
  526. return;
  527. }
  528. if ((!mac->ht_enable) && (!rtlpcipriv->bt_coexist.bt_coexistence)) {
  529. if (!(edca_be_ul & 0xffff0000))
  530. edca_be_ul |= 0x005e0000;
  531. if (!(edca_be_dl & 0xffff0000))
  532. edca_be_dl |= 0x005e0000;
  533. }
  534. if ((bt_change_edca) || ((!rtlpriv->dm.is_any_nonbepkts) &&
  535. (!rtlpriv->dm.disable_framebursting))) {
  536. cur_txok_cnt = rtlpriv->stats.txbytesunicast - last_txok_cnt;
  537. cur_rxok_cnt = rtlpriv->stats.rxbytesunicast - last_rxok_cnt;
  538. if (cur_rxok_cnt > 4 * cur_txok_cnt) {
  539. if (!rtlpriv->dm.is_cur_rdlstate ||
  540. !rtlpriv->dm.current_turbo_edca) {
  541. rtl_write_dword(rtlpriv,
  542. REG_EDCA_BE_PARAM,
  543. edca_be_dl);
  544. rtlpriv->dm.is_cur_rdlstate = true;
  545. }
  546. } else {
  547. if (rtlpriv->dm.is_cur_rdlstate ||
  548. !rtlpriv->dm.current_turbo_edca) {
  549. rtl_write_dword(rtlpriv,
  550. REG_EDCA_BE_PARAM,
  551. edca_be_ul);
  552. rtlpriv->dm.is_cur_rdlstate = false;
  553. }
  554. }
  555. rtlpriv->dm.current_turbo_edca = true;
  556. } else {
  557. if (rtlpriv->dm.current_turbo_edca) {
  558. u8 tmp = AC0_BE;
  559. rtlpriv->cfg->ops->set_hw_reg(hw,
  560. HW_VAR_AC_PARAM,
  561. (u8 *) (&tmp));
  562. rtlpriv->dm.current_turbo_edca = false;
  563. }
  564. }
  565. rtlpriv->dm.is_any_nonbepkts = false;
  566. last_txok_cnt = rtlpriv->stats.txbytesunicast;
  567. last_rxok_cnt = rtlpriv->stats.rxbytesunicast;
  568. }
  569. static void rtl92c_dm_txpower_tracking_callback_thermalmeter(struct ieee80211_hw
  570. *hw)
  571. {
  572. struct rtl_priv *rtlpriv = rtl_priv(hw);
  573. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  574. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  575. struct rtl_efuse *rtlefuse = rtl_efuse(rtl_priv(hw));
  576. u8 thermalvalue, delta, delta_lck, delta_iqk;
  577. long ele_a, ele_d, temp_cck, val_x, value32;
  578. long val_y, ele_c = 0;
  579. u8 ofdm_index[2], cck_index = 0, ofdm_index_old[2], cck_index_old = 0;
  580. int i;
  581. bool is2t = IS_92C_SERIAL(rtlhal->version);
  582. s8 txpwr_level[2] = {0, 0};
  583. u8 ofdm_min_index = 6, rf;
  584. rtlpriv->dm.txpower_trackinginit = true;
  585. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  586. "rtl92c_dm_txpower_tracking_callback_thermalmeter\n");
  587. thermalvalue = (u8) rtl_get_rfreg(hw, RF90_PATH_A, RF_T_METER, 0x1f);
  588. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  589. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x\n",
  590. thermalvalue, rtlpriv->dm.thermalvalue,
  591. rtlefuse->eeprom_thermalmeter);
  592. rtl92c_phy_ap_calibrate(hw, (thermalvalue -
  593. rtlefuse->eeprom_thermalmeter));
  594. if (is2t)
  595. rf = 2;
  596. else
  597. rf = 1;
  598. if (thermalvalue) {
  599. ele_d = rtl_get_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  600. MASKDWORD) & MASKOFDM_D;
  601. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  602. if (ele_d == (ofdmswing_table[i] & MASKOFDM_D)) {
  603. ofdm_index_old[0] = (u8) i;
  604. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  605. "Initial pathA ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  606. ROFDM0_XATXIQIMBALANCE,
  607. ele_d, ofdm_index_old[0]);
  608. break;
  609. }
  610. }
  611. if (is2t) {
  612. ele_d = rtl_get_bbreg(hw, ROFDM0_XBTXIQIMBALANCE,
  613. MASKDWORD) & MASKOFDM_D;
  614. for (i = 0; i < OFDM_TABLE_LENGTH; i++) {
  615. if (ele_d == (ofdmswing_table[i] &
  616. MASKOFDM_D)) {
  617. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  618. DBG_LOUD,
  619. "Initial pathB ele_d reg0x%x = 0x%lx, ofdm_index=0x%x\n",
  620. ROFDM0_XBTXIQIMBALANCE, ele_d,
  621. ofdm_index_old[1]);
  622. break;
  623. }
  624. }
  625. }
  626. temp_cck =
  627. rtl_get_bbreg(hw, RCCK0_TXFILTER2, MASKDWORD) & MASKCCK;
  628. for (i = 0; i < CCK_TABLE_LENGTH; i++) {
  629. if (rtlpriv->dm.cck_inch14) {
  630. if (memcmp((void *)&temp_cck,
  631. (void *)&cckswing_table_ch14[i][2],
  632. 4) == 0) {
  633. cck_index_old = (u8) i;
  634. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  635. DBG_LOUD,
  636. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch 14 %d\n",
  637. RCCK0_TXFILTER2, temp_cck,
  638. cck_index_old,
  639. rtlpriv->dm.cck_inch14);
  640. break;
  641. }
  642. } else {
  643. if (memcmp((void *)&temp_cck,
  644. (void *)
  645. &cckswing_table_ch1ch13[i][2],
  646. 4) == 0) {
  647. cck_index_old = (u8) i;
  648. RT_TRACE(rtlpriv, COMP_POWER_TRACKING,
  649. DBG_LOUD,
  650. "Initial reg0x%x = 0x%lx, cck_index=0x%x, ch14 %d\n",
  651. RCCK0_TXFILTER2, temp_cck,
  652. cck_index_old,
  653. rtlpriv->dm.cck_inch14);
  654. break;
  655. }
  656. }
  657. }
  658. if (!rtlpriv->dm.thermalvalue) {
  659. rtlpriv->dm.thermalvalue =
  660. rtlefuse->eeprom_thermalmeter;
  661. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  662. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  663. for (i = 0; i < rf; i++)
  664. rtlpriv->dm.ofdm_index[i] = ofdm_index_old[i];
  665. rtlpriv->dm.cck_index = cck_index_old;
  666. }
  667. delta = (thermalvalue > rtlpriv->dm.thermalvalue) ?
  668. (thermalvalue - rtlpriv->dm.thermalvalue) :
  669. (rtlpriv->dm.thermalvalue - thermalvalue);
  670. delta_lck = (thermalvalue > rtlpriv->dm.thermalvalue_lck) ?
  671. (thermalvalue - rtlpriv->dm.thermalvalue_lck) :
  672. (rtlpriv->dm.thermalvalue_lck - thermalvalue);
  673. delta_iqk = (thermalvalue > rtlpriv->dm.thermalvalue_iqk) ?
  674. (thermalvalue - rtlpriv->dm.thermalvalue_iqk) :
  675. (rtlpriv->dm.thermalvalue_iqk - thermalvalue);
  676. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  677. "Readback Thermal Meter = 0x%x pre thermal meter 0x%x eeprom_thermalmeter 0x%x delta 0x%x delta_lck 0x%x delta_iqk 0x%x\n",
  678. thermalvalue, rtlpriv->dm.thermalvalue,
  679. rtlefuse->eeprom_thermalmeter, delta, delta_lck,
  680. delta_iqk);
  681. if (delta_lck > 1) {
  682. rtlpriv->dm.thermalvalue_lck = thermalvalue;
  683. rtl92c_phy_lc_calibrate(hw);
  684. }
  685. if (delta > 0 && rtlpriv->dm.txpower_track_control) {
  686. if (thermalvalue > rtlpriv->dm.thermalvalue) {
  687. for (i = 0; i < rf; i++)
  688. rtlpriv->dm.ofdm_index[i] -= delta;
  689. rtlpriv->dm.cck_index -= delta;
  690. } else {
  691. for (i = 0; i < rf; i++)
  692. rtlpriv->dm.ofdm_index[i] += delta;
  693. rtlpriv->dm.cck_index += delta;
  694. }
  695. if (is2t) {
  696. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  697. "temp OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  698. rtlpriv->dm.ofdm_index[0],
  699. rtlpriv->dm.ofdm_index[1],
  700. rtlpriv->dm.cck_index);
  701. } else {
  702. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  703. "temp OFDM_A_index=0x%x, cck_index=0x%x\n",
  704. rtlpriv->dm.ofdm_index[0],
  705. rtlpriv->dm.cck_index);
  706. }
  707. if (thermalvalue > rtlefuse->eeprom_thermalmeter) {
  708. for (i = 0; i < rf; i++)
  709. ofdm_index[i] =
  710. rtlpriv->dm.ofdm_index[i]
  711. + 1;
  712. cck_index = rtlpriv->dm.cck_index + 1;
  713. } else {
  714. for (i = 0; i < rf; i++)
  715. ofdm_index[i] =
  716. rtlpriv->dm.ofdm_index[i];
  717. cck_index = rtlpriv->dm.cck_index;
  718. }
  719. for (i = 0; i < rf; i++) {
  720. if (txpwr_level[i] >= 0 &&
  721. txpwr_level[i] <= 26) {
  722. if (thermalvalue >
  723. rtlefuse->eeprom_thermalmeter) {
  724. if (delta < 5)
  725. ofdm_index[i] -= 1;
  726. else
  727. ofdm_index[i] -= 2;
  728. } else if (delta > 5 && thermalvalue <
  729. rtlefuse->
  730. eeprom_thermalmeter) {
  731. ofdm_index[i] += 1;
  732. }
  733. } else if (txpwr_level[i] >= 27 &&
  734. txpwr_level[i] <= 32
  735. && thermalvalue >
  736. rtlefuse->eeprom_thermalmeter) {
  737. if (delta < 5)
  738. ofdm_index[i] -= 1;
  739. else
  740. ofdm_index[i] -= 2;
  741. } else if (txpwr_level[i] >= 32 &&
  742. txpwr_level[i] <= 38 &&
  743. thermalvalue >
  744. rtlefuse->eeprom_thermalmeter
  745. && delta > 5) {
  746. ofdm_index[i] -= 1;
  747. }
  748. }
  749. if (txpwr_level[i] >= 0 && txpwr_level[i] <= 26) {
  750. if (thermalvalue >
  751. rtlefuse->eeprom_thermalmeter) {
  752. if (delta < 5)
  753. cck_index -= 1;
  754. else
  755. cck_index -= 2;
  756. } else if (delta > 5 && thermalvalue <
  757. rtlefuse->eeprom_thermalmeter) {
  758. cck_index += 1;
  759. }
  760. } else if (txpwr_level[i] >= 27 &&
  761. txpwr_level[i] <= 32 &&
  762. thermalvalue >
  763. rtlefuse->eeprom_thermalmeter) {
  764. if (delta < 5)
  765. cck_index -= 1;
  766. else
  767. cck_index -= 2;
  768. } else if (txpwr_level[i] >= 32 &&
  769. txpwr_level[i] <= 38 &&
  770. thermalvalue > rtlefuse->eeprom_thermalmeter
  771. && delta > 5) {
  772. cck_index -= 1;
  773. }
  774. for (i = 0; i < rf; i++) {
  775. if (ofdm_index[i] > OFDM_TABLE_SIZE - 1)
  776. ofdm_index[i] = OFDM_TABLE_SIZE - 1;
  777. else if (ofdm_index[i] < ofdm_min_index)
  778. ofdm_index[i] = ofdm_min_index;
  779. }
  780. if (cck_index > CCK_TABLE_SIZE - 1)
  781. cck_index = CCK_TABLE_SIZE - 1;
  782. else if (cck_index < 0)
  783. cck_index = 0;
  784. if (is2t) {
  785. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  786. "new OFDM_A_index=0x%x, OFDM_B_index=0x%x, cck_index=0x%x\n",
  787. ofdm_index[0], ofdm_index[1],
  788. cck_index);
  789. } else {
  790. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  791. "new OFDM_A_index=0x%x, cck_index=0x%x\n",
  792. ofdm_index[0], cck_index);
  793. }
  794. }
  795. if (rtlpriv->dm.txpower_track_control && delta != 0) {
  796. ele_d =
  797. (ofdmswing_table[ofdm_index[0]] & 0xFFC00000) >> 22;
  798. val_x = rtlphy->reg_e94;
  799. val_y = rtlphy->reg_e9c;
  800. if (val_x != 0) {
  801. if ((val_x & 0x00000200) != 0)
  802. val_x = val_x | 0xFFFFFC00;
  803. ele_a = ((val_x * ele_d) >> 8) & 0x000003FF;
  804. if ((val_y & 0x00000200) != 0)
  805. val_y = val_y | 0xFFFFFC00;
  806. ele_c = ((val_y * ele_d) >> 8) & 0x000003FF;
  807. value32 = (ele_d << 22) |
  808. ((ele_c & 0x3F) << 16) | ele_a;
  809. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  810. MASKDWORD, value32);
  811. value32 = (ele_c & 0x000003C0) >> 6;
  812. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  813. value32);
  814. value32 = ((val_x * ele_d) >> 7) & 0x01;
  815. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  816. BIT(31), value32);
  817. value32 = ((val_y * ele_d) >> 7) & 0x01;
  818. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  819. BIT(29), value32);
  820. } else {
  821. rtl_set_bbreg(hw, ROFDM0_XATXIQIMBALANCE,
  822. MASKDWORD,
  823. ofdmswing_table[ofdm_index[0]]);
  824. rtl_set_bbreg(hw, ROFDM0_XCTXAFE, MASKH4BITS,
  825. 0x00);
  826. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  827. BIT(31) | BIT(29), 0x00);
  828. }
  829. if (!rtlpriv->dm.cck_inch14) {
  830. rtl_write_byte(rtlpriv, 0xa22,
  831. cckswing_table_ch1ch13[cck_index]
  832. [0]);
  833. rtl_write_byte(rtlpriv, 0xa23,
  834. cckswing_table_ch1ch13[cck_index]
  835. [1]);
  836. rtl_write_byte(rtlpriv, 0xa24,
  837. cckswing_table_ch1ch13[cck_index]
  838. [2]);
  839. rtl_write_byte(rtlpriv, 0xa25,
  840. cckswing_table_ch1ch13[cck_index]
  841. [3]);
  842. rtl_write_byte(rtlpriv, 0xa26,
  843. cckswing_table_ch1ch13[cck_index]
  844. [4]);
  845. rtl_write_byte(rtlpriv, 0xa27,
  846. cckswing_table_ch1ch13[cck_index]
  847. [5]);
  848. rtl_write_byte(rtlpriv, 0xa28,
  849. cckswing_table_ch1ch13[cck_index]
  850. [6]);
  851. rtl_write_byte(rtlpriv, 0xa29,
  852. cckswing_table_ch1ch13[cck_index]
  853. [7]);
  854. } else {
  855. rtl_write_byte(rtlpriv, 0xa22,
  856. cckswing_table_ch14[cck_index]
  857. [0]);
  858. rtl_write_byte(rtlpriv, 0xa23,
  859. cckswing_table_ch14[cck_index]
  860. [1]);
  861. rtl_write_byte(rtlpriv, 0xa24,
  862. cckswing_table_ch14[cck_index]
  863. [2]);
  864. rtl_write_byte(rtlpriv, 0xa25,
  865. cckswing_table_ch14[cck_index]
  866. [3]);
  867. rtl_write_byte(rtlpriv, 0xa26,
  868. cckswing_table_ch14[cck_index]
  869. [4]);
  870. rtl_write_byte(rtlpriv, 0xa27,
  871. cckswing_table_ch14[cck_index]
  872. [5]);
  873. rtl_write_byte(rtlpriv, 0xa28,
  874. cckswing_table_ch14[cck_index]
  875. [6]);
  876. rtl_write_byte(rtlpriv, 0xa29,
  877. cckswing_table_ch14[cck_index]
  878. [7]);
  879. }
  880. if (is2t) {
  881. ele_d = (ofdmswing_table[ofdm_index[1]] &
  882. 0xFFC00000) >> 22;
  883. val_x = rtlphy->reg_eb4;
  884. val_y = rtlphy->reg_ebc;
  885. if (val_x != 0) {
  886. if ((val_x & 0x00000200) != 0)
  887. val_x = val_x | 0xFFFFFC00;
  888. ele_a = ((val_x * ele_d) >> 8) &
  889. 0x000003FF;
  890. if ((val_y & 0x00000200) != 0)
  891. val_y = val_y | 0xFFFFFC00;
  892. ele_c = ((val_y * ele_d) >> 8) &
  893. 0x00003FF;
  894. value32 = (ele_d << 22) |
  895. ((ele_c & 0x3F) << 16) | ele_a;
  896. rtl_set_bbreg(hw,
  897. ROFDM0_XBTXIQIMBALANCE,
  898. MASKDWORD, value32);
  899. value32 = (ele_c & 0x000003C0) >> 6;
  900. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  901. MASKH4BITS, value32);
  902. value32 = ((val_x * ele_d) >> 7) & 0x01;
  903. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  904. BIT(27), value32);
  905. value32 = ((val_y * ele_d) >> 7) & 0x01;
  906. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  907. BIT(25), value32);
  908. } else {
  909. rtl_set_bbreg(hw,
  910. ROFDM0_XBTXIQIMBALANCE,
  911. MASKDWORD,
  912. ofdmswing_table[ofdm_index
  913. [1]]);
  914. rtl_set_bbreg(hw, ROFDM0_XDTXAFE,
  915. MASKH4BITS, 0x00);
  916. rtl_set_bbreg(hw, ROFDM0_ECCATHRESHOLD,
  917. BIT(27) | BIT(25), 0x00);
  918. }
  919. }
  920. }
  921. if (delta_iqk > 3) {
  922. rtlpriv->dm.thermalvalue_iqk = thermalvalue;
  923. rtl92c_phy_iq_calibrate(hw, false);
  924. }
  925. if (rtlpriv->dm.txpower_track_control)
  926. rtlpriv->dm.thermalvalue = thermalvalue;
  927. }
  928. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD, "<===\n");
  929. }
  930. static void rtl92c_dm_initialize_txpower_tracking_thermalmeter(
  931. struct ieee80211_hw *hw)
  932. {
  933. struct rtl_priv *rtlpriv = rtl_priv(hw);
  934. rtlpriv->dm.txpower_tracking = true;
  935. rtlpriv->dm.txpower_trackinginit = false;
  936. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  937. "pMgntInfo->txpower_tracking = %d\n",
  938. rtlpriv->dm.txpower_tracking);
  939. }
  940. static void rtl92c_dm_initialize_txpower_tracking(struct ieee80211_hw *hw)
  941. {
  942. rtl92c_dm_initialize_txpower_tracking_thermalmeter(hw);
  943. }
  944. static void rtl92c_dm_txpower_tracking_directcall(struct ieee80211_hw *hw)
  945. {
  946. rtl92c_dm_txpower_tracking_callback_thermalmeter(hw);
  947. }
  948. static void rtl92c_dm_check_txpower_tracking_thermal_meter(
  949. struct ieee80211_hw *hw)
  950. {
  951. struct rtl_priv *rtlpriv = rtl_priv(hw);
  952. static u8 tm_trigger;
  953. if (!rtlpriv->dm.txpower_tracking)
  954. return;
  955. if (!tm_trigger) {
  956. rtl_set_rfreg(hw, RF90_PATH_A, RF_T_METER, RFREG_OFFSET_MASK,
  957. 0x60);
  958. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  959. "Trigger 92S Thermal Meter!!\n");
  960. tm_trigger = 1;
  961. return;
  962. } else {
  963. RT_TRACE(rtlpriv, COMP_POWER_TRACKING, DBG_LOUD,
  964. "Schedule TxPowerTracking direct call!!\n");
  965. rtl92c_dm_txpower_tracking_directcall(hw);
  966. tm_trigger = 0;
  967. }
  968. }
  969. void rtl92c_dm_check_txpower_tracking(struct ieee80211_hw *hw)
  970. {
  971. rtl92c_dm_check_txpower_tracking_thermal_meter(hw);
  972. }
  973. EXPORT_SYMBOL(rtl92c_dm_check_txpower_tracking);
  974. void rtl92c_dm_init_rate_adaptive_mask(struct ieee80211_hw *hw)
  975. {
  976. struct rtl_priv *rtlpriv = rtl_priv(hw);
  977. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  978. p_ra->ratr_state = DM_RATR_STA_INIT;
  979. p_ra->pre_ratr_state = DM_RATR_STA_INIT;
  980. if (rtlpriv->dm.dm_type == DM_TYPE_BYDRIVER)
  981. rtlpriv->dm.useramask = true;
  982. else
  983. rtlpriv->dm.useramask = false;
  984. }
  985. EXPORT_SYMBOL(rtl92c_dm_init_rate_adaptive_mask);
  986. static void rtl92c_dm_refresh_rate_adaptive_mask(struct ieee80211_hw *hw)
  987. {
  988. struct rtl_priv *rtlpriv = rtl_priv(hw);
  989. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  990. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  991. struct rate_adaptive *p_ra = &(rtlpriv->ra);
  992. u32 low_rssithresh_for_ra, high_rssithresh_for_ra;
  993. struct ieee80211_sta *sta = NULL;
  994. if (is_hal_stop(rtlhal)) {
  995. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  996. "<---- driver is going to unload\n");
  997. return;
  998. }
  999. if (!rtlpriv->dm.useramask) {
  1000. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1001. "<---- driver does not control rate adaptive mask\n");
  1002. return;
  1003. }
  1004. if (mac->link_state == MAC80211_LINKED &&
  1005. mac->opmode == NL80211_IFTYPE_STATION) {
  1006. switch (p_ra->pre_ratr_state) {
  1007. case DM_RATR_STA_HIGH:
  1008. high_rssithresh_for_ra = 50;
  1009. low_rssithresh_for_ra = 20;
  1010. break;
  1011. case DM_RATR_STA_MIDDLE:
  1012. high_rssithresh_for_ra = 55;
  1013. low_rssithresh_for_ra = 20;
  1014. break;
  1015. case DM_RATR_STA_LOW:
  1016. high_rssithresh_for_ra = 50;
  1017. low_rssithresh_for_ra = 25;
  1018. break;
  1019. default:
  1020. high_rssithresh_for_ra = 50;
  1021. low_rssithresh_for_ra = 20;
  1022. break;
  1023. }
  1024. if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1025. (long)high_rssithresh_for_ra)
  1026. p_ra->ratr_state = DM_RATR_STA_HIGH;
  1027. else if (rtlpriv->dm.undecorated_smoothed_pwdb >
  1028. (long)low_rssithresh_for_ra)
  1029. p_ra->ratr_state = DM_RATR_STA_MIDDLE;
  1030. else
  1031. p_ra->ratr_state = DM_RATR_STA_LOW;
  1032. if (p_ra->pre_ratr_state != p_ra->ratr_state) {
  1033. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD, "RSSI = %ld\n",
  1034. rtlpriv->dm.undecorated_smoothed_pwdb);
  1035. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1036. "RSSI_LEVEL = %d\n", p_ra->ratr_state);
  1037. RT_TRACE(rtlpriv, COMP_RATE, DBG_LOUD,
  1038. "PreState = %d, CurState = %d\n",
  1039. p_ra->pre_ratr_state, p_ra->ratr_state);
  1040. rcu_read_lock();
  1041. sta = ieee80211_find_sta(mac->vif, mac->bssid);
  1042. rtlpriv->cfg->ops->update_rate_tbl(hw, sta,
  1043. p_ra->ratr_state);
  1044. p_ra->pre_ratr_state = p_ra->ratr_state;
  1045. rcu_read_unlock();
  1046. }
  1047. }
  1048. }
  1049. static void rtl92c_dm_init_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1050. {
  1051. dm_pstable.pre_ccastate = CCA_MAX;
  1052. dm_pstable.cur_ccasate = CCA_MAX;
  1053. dm_pstable.pre_rfstate = RF_MAX;
  1054. dm_pstable.cur_rfstate = RF_MAX;
  1055. dm_pstable.rssi_val_min = 0;
  1056. }
  1057. void rtl92c_dm_rf_saving(struct ieee80211_hw *hw, u8 bforce_in_normal)
  1058. {
  1059. static u8 initialize;
  1060. static u32 reg_874, reg_c70, reg_85c, reg_a74;
  1061. if (initialize == 0) {
  1062. reg_874 = (rtl_get_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1063. MASKDWORD) & 0x1CC000) >> 14;
  1064. reg_c70 = (rtl_get_bbreg(hw, ROFDM0_AGCPARAMETER1,
  1065. MASKDWORD) & BIT(3)) >> 3;
  1066. reg_85c = (rtl_get_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1067. MASKDWORD) & 0xFF000000) >> 24;
  1068. reg_a74 = (rtl_get_bbreg(hw, 0xa74, MASKDWORD) & 0xF000) >> 12;
  1069. initialize = 1;
  1070. }
  1071. if (!bforce_in_normal) {
  1072. if (dm_pstable.rssi_val_min != 0) {
  1073. if (dm_pstable.pre_rfstate == RF_NORMAL) {
  1074. if (dm_pstable.rssi_val_min >= 30)
  1075. dm_pstable.cur_rfstate = RF_SAVE;
  1076. else
  1077. dm_pstable.cur_rfstate = RF_NORMAL;
  1078. } else {
  1079. if (dm_pstable.rssi_val_min <= 25)
  1080. dm_pstable.cur_rfstate = RF_NORMAL;
  1081. else
  1082. dm_pstable.cur_rfstate = RF_SAVE;
  1083. }
  1084. } else {
  1085. dm_pstable.cur_rfstate = RF_MAX;
  1086. }
  1087. } else {
  1088. dm_pstable.cur_rfstate = RF_NORMAL;
  1089. }
  1090. if (dm_pstable.pre_rfstate != dm_pstable.cur_rfstate) {
  1091. if (dm_pstable.cur_rfstate == RF_SAVE) {
  1092. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1093. 0x1C0000, 0x2);
  1094. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3), 0);
  1095. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL,
  1096. 0xFF000000, 0x63);
  1097. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1098. 0xC000, 0x2);
  1099. rtl_set_bbreg(hw, 0xa74, 0xF000, 0x3);
  1100. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1101. rtl_set_bbreg(hw, 0x818, BIT(28), 0x1);
  1102. } else {
  1103. rtl_set_bbreg(hw, RFPGA0_XCD_RFINTERFACESW,
  1104. 0x1CC000, reg_874);
  1105. rtl_set_bbreg(hw, ROFDM0_AGCPARAMETER1, BIT(3),
  1106. reg_c70);
  1107. rtl_set_bbreg(hw, RFPGA0_XCD_SWITCHCONTROL, 0xFF000000,
  1108. reg_85c);
  1109. rtl_set_bbreg(hw, 0xa74, 0xF000, reg_a74);
  1110. rtl_set_bbreg(hw, 0x818, BIT(28), 0x0);
  1111. }
  1112. dm_pstable.pre_rfstate = dm_pstable.cur_rfstate;
  1113. }
  1114. }
  1115. EXPORT_SYMBOL(rtl92c_dm_rf_saving);
  1116. static void rtl92c_dm_dynamic_bb_powersaving(struct ieee80211_hw *hw)
  1117. {
  1118. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1119. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1120. struct rtl_hal *rtlhal = rtl_hal(rtl_priv(hw));
  1121. if (((mac->link_state == MAC80211_NOLINK)) &&
  1122. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1123. dm_pstable.rssi_val_min = 0;
  1124. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD, "Not connected to any\n");
  1125. }
  1126. if (mac->link_state == MAC80211_LINKED) {
  1127. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1128. dm_pstable.rssi_val_min =
  1129. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1130. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1131. "AP Client PWDB = 0x%lx\n",
  1132. dm_pstable.rssi_val_min);
  1133. } else {
  1134. dm_pstable.rssi_val_min =
  1135. rtlpriv->dm.undecorated_smoothed_pwdb;
  1136. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1137. "STA Default Port PWDB = 0x%lx\n",
  1138. dm_pstable.rssi_val_min);
  1139. }
  1140. } else {
  1141. dm_pstable.rssi_val_min =
  1142. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1143. RT_TRACE(rtlpriv, DBG_LOUD, DBG_LOUD,
  1144. "AP Ext Port PWDB = 0x%lx\n",
  1145. dm_pstable.rssi_val_min);
  1146. }
  1147. if (IS_92C_SERIAL(rtlhal->version))
  1148. ;/* rtl92c_dm_1r_cca(hw); */
  1149. else
  1150. rtl92c_dm_rf_saving(hw, false);
  1151. }
  1152. void rtl92c_dm_init(struct ieee80211_hw *hw)
  1153. {
  1154. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1155. rtlpriv->dm.dm_type = DM_TYPE_BYDRIVER;
  1156. rtl92c_dm_diginit(hw);
  1157. rtl92c_dm_init_dynamic_txpower(hw);
  1158. rtl92c_dm_init_edca_turbo(hw);
  1159. rtl92c_dm_init_rate_adaptive_mask(hw);
  1160. rtl92c_dm_initialize_txpower_tracking(hw);
  1161. rtl92c_dm_init_dynamic_bb_powersaving(hw);
  1162. }
  1163. EXPORT_SYMBOL(rtl92c_dm_init);
  1164. void rtl92c_dm_dynamic_txpower(struct ieee80211_hw *hw)
  1165. {
  1166. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1167. struct rtl_phy *rtlphy = &(rtlpriv->phy);
  1168. struct rtl_mac *mac = rtl_mac(rtl_priv(hw));
  1169. long undecorated_smoothed_pwdb;
  1170. if (!rtlpriv->dm.dynamic_txpower_enable)
  1171. return;
  1172. if (rtlpriv->dm.dm_flag & HAL_DM_HIPWR_DISABLE) {
  1173. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1174. return;
  1175. }
  1176. if ((mac->link_state < MAC80211_LINKED) &&
  1177. (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)) {
  1178. RT_TRACE(rtlpriv, COMP_POWER, DBG_TRACE,
  1179. "Not connected to any\n");
  1180. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1181. rtlpriv->dm.last_dtp_lvl = TXHIGHPWRLEVEL_NORMAL;
  1182. return;
  1183. }
  1184. if (mac->link_state >= MAC80211_LINKED) {
  1185. if (mac->opmode == NL80211_IFTYPE_ADHOC) {
  1186. undecorated_smoothed_pwdb =
  1187. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1188. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1189. "AP Client PWDB = 0x%lx\n",
  1190. undecorated_smoothed_pwdb);
  1191. } else {
  1192. undecorated_smoothed_pwdb =
  1193. rtlpriv->dm.undecorated_smoothed_pwdb;
  1194. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1195. "STA Default Port PWDB = 0x%lx\n",
  1196. undecorated_smoothed_pwdb);
  1197. }
  1198. } else {
  1199. undecorated_smoothed_pwdb =
  1200. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1201. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1202. "AP Ext Port PWDB = 0x%lx\n",
  1203. undecorated_smoothed_pwdb);
  1204. }
  1205. if (undecorated_smoothed_pwdb >= TX_POWER_NEAR_FIELD_THRESH_LVL2) {
  1206. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1207. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1208. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x0)\n");
  1209. } else if ((undecorated_smoothed_pwdb <
  1210. (TX_POWER_NEAR_FIELD_THRESH_LVL2 - 3)) &&
  1211. (undecorated_smoothed_pwdb >=
  1212. TX_POWER_NEAR_FIELD_THRESH_LVL1)) {
  1213. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_LEVEL1;
  1214. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1215. "TXHIGHPWRLEVEL_LEVEL1 (TxPwr=0x10)\n");
  1216. } else if (undecorated_smoothed_pwdb <
  1217. (TX_POWER_NEAR_FIELD_THRESH_LVL1 - 5)) {
  1218. rtlpriv->dm.dynamic_txhighpower_lvl = TXHIGHPWRLEVEL_NORMAL;
  1219. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1220. "TXHIGHPWRLEVEL_NORMAL\n");
  1221. }
  1222. if ((rtlpriv->dm.dynamic_txhighpower_lvl != rtlpriv->dm.last_dtp_lvl)) {
  1223. RT_TRACE(rtlpriv, COMP_POWER, DBG_LOUD,
  1224. "PHY_SetTxPowerLevel8192S() Channel = %d\n",
  1225. rtlphy->current_channel);
  1226. rtl92c_phy_set_txpower_level(hw, rtlphy->current_channel);
  1227. }
  1228. rtlpriv->dm.last_dtp_lvl = rtlpriv->dm.dynamic_txhighpower_lvl;
  1229. }
  1230. void rtl92c_dm_watchdog(struct ieee80211_hw *hw)
  1231. {
  1232. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1233. struct rtl_ps_ctl *ppsc = rtl_psc(rtl_priv(hw));
  1234. bool fw_current_inpsmode = false;
  1235. bool fw_ps_awake = true;
  1236. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FW_PSMODE_STATUS,
  1237. (u8 *) (&fw_current_inpsmode));
  1238. rtlpriv->cfg->ops->get_hw_reg(hw, HW_VAR_FWLPS_RF_ON,
  1239. (u8 *) (&fw_ps_awake));
  1240. if ((ppsc->rfpwr_state == ERFON) && ((!fw_current_inpsmode) &&
  1241. fw_ps_awake)
  1242. && (!ppsc->rfchange_inprogress)) {
  1243. rtl92c_dm_pwdb_monitor(hw);
  1244. rtl92c_dm_dig(hw);
  1245. rtl92c_dm_false_alarm_counter_statistics(hw);
  1246. rtl92c_dm_dynamic_bb_powersaving(hw);
  1247. rtl92c_dm_dynamic_txpower(hw);
  1248. rtl92c_dm_check_txpower_tracking(hw);
  1249. rtl92c_dm_refresh_rate_adaptive_mask(hw);
  1250. rtl92c_dm_bt_coexist(hw);
  1251. rtl92c_dm_check_edca_turbo(hw);
  1252. }
  1253. }
  1254. EXPORT_SYMBOL(rtl92c_dm_watchdog);
  1255. u8 rtl92c_bt_rssi_state_change(struct ieee80211_hw *hw)
  1256. {
  1257. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1258. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1259. long undecorated_smoothed_pwdb;
  1260. u8 curr_bt_rssi_state = 0x00;
  1261. if (rtlpriv->mac80211.link_state == MAC80211_LINKED) {
  1262. undecorated_smoothed_pwdb =
  1263. GET_UNDECORATED_AVERAGE_RSSI(rtlpriv);
  1264. } else {
  1265. if (rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb == 0)
  1266. undecorated_smoothed_pwdb = 100;
  1267. else
  1268. undecorated_smoothed_pwdb =
  1269. rtlpriv->dm.entry_min_undecoratedsmoothed_pwdb;
  1270. }
  1271. /* Check RSSI to determine HighPower/NormalPower state for
  1272. * BT coexistence. */
  1273. if (undecorated_smoothed_pwdb >= 67)
  1274. curr_bt_rssi_state &= (~BT_RSSI_STATE_NORMAL_POWER);
  1275. else if (undecorated_smoothed_pwdb < 62)
  1276. curr_bt_rssi_state |= BT_RSSI_STATE_NORMAL_POWER;
  1277. /* Check RSSI to determine AMPDU setting for BT coexistence. */
  1278. if (undecorated_smoothed_pwdb >= 40)
  1279. curr_bt_rssi_state &= (~BT_RSSI_STATE_AMDPU_OFF);
  1280. else if (undecorated_smoothed_pwdb <= 32)
  1281. curr_bt_rssi_state |= BT_RSSI_STATE_AMDPU_OFF;
  1282. /* Marked RSSI state. It will be used to determine BT coexistence
  1283. * setting later. */
  1284. if (undecorated_smoothed_pwdb < 35)
  1285. curr_bt_rssi_state |= BT_RSSI_STATE_SPECIAL_LOW;
  1286. else
  1287. curr_bt_rssi_state &= (~BT_RSSI_STATE_SPECIAL_LOW);
  1288. /* Set Tx Power according to BT status. */
  1289. if (undecorated_smoothed_pwdb >= 30)
  1290. curr_bt_rssi_state |= BT_RSSI_STATE_TXPOWER_LOW;
  1291. else if (undecorated_smoothed_pwdb < 25)
  1292. curr_bt_rssi_state &= (~BT_RSSI_STATE_TXPOWER_LOW);
  1293. /* Check BT state related to BT_Idle in B/G mode. */
  1294. if (undecorated_smoothed_pwdb < 15)
  1295. curr_bt_rssi_state |= BT_RSSI_STATE_BG_EDCA_LOW;
  1296. else
  1297. curr_bt_rssi_state &= (~BT_RSSI_STATE_BG_EDCA_LOW);
  1298. if (curr_bt_rssi_state != rtlpcipriv->bt_coexist.bt_rssi_state) {
  1299. rtlpcipriv->bt_coexist.bt_rssi_state = curr_bt_rssi_state;
  1300. return true;
  1301. } else {
  1302. return false;
  1303. }
  1304. }
  1305. EXPORT_SYMBOL(rtl92c_bt_rssi_state_change);
  1306. static bool rtl92c_bt_state_change(struct ieee80211_hw *hw)
  1307. {
  1308. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1309. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1310. u32 polling, ratio_tx, ratio_pri;
  1311. u32 bt_tx, bt_pri;
  1312. u8 bt_state;
  1313. u8 cur_service_type;
  1314. if (rtlpriv->mac80211.link_state < MAC80211_LINKED)
  1315. return false;
  1316. bt_state = rtl_read_byte(rtlpriv, 0x4fd);
  1317. bt_tx = rtl_read_dword(rtlpriv, 0x488);
  1318. bt_tx = bt_tx & 0x00ffffff;
  1319. bt_pri = rtl_read_dword(rtlpriv, 0x48c);
  1320. bt_pri = bt_pri & 0x00ffffff;
  1321. polling = rtl_read_dword(rtlpriv, 0x490);
  1322. if (bt_tx == 0xffffffff && bt_pri == 0xffffffff &&
  1323. polling == 0xffffffff && bt_state == 0xff)
  1324. return false;
  1325. bt_state &= BIT_OFFSET_LEN_MASK_32(0, 1);
  1326. if (bt_state != rtlpcipriv->bt_coexist.bt_cur_state) {
  1327. rtlpcipriv->bt_coexist.bt_cur_state = bt_state;
  1328. if (rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1329. rtlpcipriv->bt_coexist.bt_service = BT_IDLE;
  1330. bt_state = bt_state |
  1331. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1332. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1333. BIT_OFFSET_LEN_MASK_32(2, 1);
  1334. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1335. }
  1336. return true;
  1337. }
  1338. ratio_tx = bt_tx * 1000 / polling;
  1339. ratio_pri = bt_pri * 1000 / polling;
  1340. rtlpcipriv->bt_coexist.ratio_tx = ratio_tx;
  1341. rtlpcipriv->bt_coexist.ratio_pri = ratio_pri;
  1342. if (bt_state && rtlpcipriv->bt_coexist.reg_bt_sco == 3) {
  1343. if ((ratio_tx < 30) && (ratio_pri < 30))
  1344. cur_service_type = BT_IDLE;
  1345. else if ((ratio_pri > 110) && (ratio_pri < 250))
  1346. cur_service_type = BT_SCO;
  1347. else if ((ratio_tx >= 200) && (ratio_pri >= 200))
  1348. cur_service_type = BT_BUSY;
  1349. else if ((ratio_tx >= 350) && (ratio_tx < 500))
  1350. cur_service_type = BT_OTHERBUSY;
  1351. else if (ratio_tx >= 500)
  1352. cur_service_type = BT_PAN;
  1353. else
  1354. cur_service_type = BT_OTHER_ACTION;
  1355. if (cur_service_type != rtlpcipriv->bt_coexist.bt_service) {
  1356. rtlpcipriv->bt_coexist.bt_service = cur_service_type;
  1357. bt_state = bt_state |
  1358. ((rtlpcipriv->bt_coexist.bt_ant_isolation == 1) ?
  1359. 0 : BIT_OFFSET_LEN_MASK_32(1, 1)) |
  1360. ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) ?
  1361. 0 : BIT_OFFSET_LEN_MASK_32(2, 1));
  1362. /* Add interrupt migration when bt is not ini
  1363. * idle state (no traffic). */
  1364. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1365. rtl_write_word(rtlpriv, 0x504, 0x0ccc);
  1366. rtl_write_byte(rtlpriv, 0x506, 0x54);
  1367. rtl_write_byte(rtlpriv, 0x507, 0x54);
  1368. } else {
  1369. rtl_write_byte(rtlpriv, 0x506, 0x00);
  1370. rtl_write_byte(rtlpriv, 0x507, 0x00);
  1371. }
  1372. rtl_write_byte(rtlpriv, 0x4fd, bt_state);
  1373. return true;
  1374. }
  1375. }
  1376. return false;
  1377. }
  1378. static bool rtl92c_bt_wifi_connect_change(struct ieee80211_hw *hw)
  1379. {
  1380. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1381. static bool media_connect;
  1382. if (rtlpriv->mac80211.link_state < MAC80211_LINKED) {
  1383. media_connect = false;
  1384. } else {
  1385. if (!media_connect) {
  1386. media_connect = true;
  1387. return true;
  1388. }
  1389. media_connect = true;
  1390. }
  1391. return false;
  1392. }
  1393. static void rtl92c_bt_set_normal(struct ieee80211_hw *hw)
  1394. {
  1395. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1396. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1397. if (rtlpcipriv->bt_coexist.bt_service == BT_OTHERBUSY) {
  1398. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72b;
  1399. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72b;
  1400. } else if (rtlpcipriv->bt_coexist.bt_service == BT_BUSY) {
  1401. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82f;
  1402. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82f;
  1403. } else if (rtlpcipriv->bt_coexist.bt_service == BT_SCO) {
  1404. if (rtlpcipriv->bt_coexist.ratio_tx > 160) {
  1405. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea72f;
  1406. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea72f;
  1407. } else {
  1408. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5ea32b;
  1409. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5ea42b;
  1410. }
  1411. } else {
  1412. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1413. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1414. }
  1415. if ((rtlpcipriv->bt_coexist.bt_service != BT_IDLE) &&
  1416. (rtlpriv->mac80211.mode == WIRELESS_MODE_G ||
  1417. (rtlpriv->mac80211.mode == (WIRELESS_MODE_G | WIRELESS_MODE_B))) &&
  1418. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1419. BT_RSSI_STATE_BG_EDCA_LOW)) {
  1420. rtlpcipriv->bt_coexist.bt_edca_ul = 0x5eb82b;
  1421. rtlpcipriv->bt_coexist.bt_edca_dl = 0x5eb82b;
  1422. }
  1423. }
  1424. static void rtl92c_bt_ant_isolation(struct ieee80211_hw *hw)
  1425. {
  1426. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1427. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1428. /* Only enable HW BT coexist when BT in "Busy" state. */
  1429. if (rtlpriv->mac80211.vendor == PEER_CISCO &&
  1430. rtlpcipriv->bt_coexist.bt_service == BT_OTHER_ACTION) {
  1431. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1432. } else {
  1433. if ((rtlpcipriv->bt_coexist.bt_service == BT_BUSY) &&
  1434. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1435. BT_RSSI_STATE_NORMAL_POWER)) {
  1436. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1437. } else if ((rtlpcipriv->bt_coexist.bt_service ==
  1438. BT_OTHER_ACTION) && (rtlpriv->mac80211.mode <
  1439. WIRELESS_MODE_N_24G) &&
  1440. (rtlpcipriv->bt_coexist.bt_rssi_state &
  1441. BT_RSSI_STATE_SPECIAL_LOW)) {
  1442. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0xa0);
  1443. } else if (rtlpcipriv->bt_coexist.bt_service == BT_PAN) {
  1444. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1445. } else {
  1446. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1447. }
  1448. }
  1449. if (rtlpcipriv->bt_coexist.bt_service == BT_PAN)
  1450. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x10100);
  1451. else
  1452. rtl_write_dword(rtlpriv, REG_GPIO_PIN_CTRL, 0x0);
  1453. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1454. BT_RSSI_STATE_NORMAL_POWER) {
  1455. rtl92c_bt_set_normal(hw);
  1456. } else {
  1457. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1458. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1459. }
  1460. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1461. rtlpriv->cfg->ops->set_rfreg(hw,
  1462. RF90_PATH_A,
  1463. 0x1e,
  1464. 0xf0, 0xf);
  1465. } else {
  1466. rtlpriv->cfg->ops->set_rfreg(hw,
  1467. RF90_PATH_A, 0x1e, 0xf0,
  1468. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1469. }
  1470. if (!rtlpriv->dm.dynamic_txpower_enable) {
  1471. if (rtlpcipriv->bt_coexist.bt_service != BT_IDLE) {
  1472. if (rtlpcipriv->bt_coexist.bt_rssi_state &
  1473. BT_RSSI_STATE_TXPOWER_LOW) {
  1474. rtlpriv->dm.dynamic_txhighpower_lvl =
  1475. TXHIGHPWRLEVEL_BT2;
  1476. } else {
  1477. rtlpriv->dm.dynamic_txhighpower_lvl =
  1478. TXHIGHPWRLEVEL_BT1;
  1479. }
  1480. } else {
  1481. rtlpriv->dm.dynamic_txhighpower_lvl =
  1482. TXHIGHPWRLEVEL_NORMAL;
  1483. }
  1484. rtl92c_phy_set_txpower_level(hw,
  1485. rtlpriv->phy.current_channel);
  1486. }
  1487. }
  1488. static void rtl92c_check_bt_change(struct ieee80211_hw *hw)
  1489. {
  1490. struct rtl_priv *rtlpriv = rtl_priv(hw);
  1491. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1492. if (rtlpcipriv->bt_coexist.bt_cur_state) {
  1493. if (rtlpcipriv->bt_coexist.bt_ant_isolation)
  1494. rtl92c_bt_ant_isolation(hw);
  1495. } else {
  1496. rtl_write_byte(rtlpriv, REG_GPIO_MUXCFG, 0x00);
  1497. rtlpriv->cfg->ops->set_rfreg(hw, RF90_PATH_A, 0x1e, 0xf0,
  1498. rtlpcipriv->bt_coexist.bt_rfreg_origin_1e);
  1499. rtlpcipriv->bt_coexist.bt_edca_ul = 0;
  1500. rtlpcipriv->bt_coexist.bt_edca_dl = 0;
  1501. }
  1502. }
  1503. void rtl92c_dm_bt_coexist(struct ieee80211_hw *hw)
  1504. {
  1505. struct rtl_pci_priv *rtlpcipriv = rtl_pcipriv(hw);
  1506. bool wifi_connect_change;
  1507. bool bt_state_change;
  1508. bool rssi_state_change;
  1509. if ((rtlpcipriv->bt_coexist.bt_coexistence) &&
  1510. (rtlpcipriv->bt_coexist.bt_coexist_type == BT_CSR_BC4)) {
  1511. wifi_connect_change = rtl92c_bt_wifi_connect_change(hw);
  1512. bt_state_change = rtl92c_bt_state_change(hw);
  1513. rssi_state_change = rtl92c_bt_rssi_state_change(hw);
  1514. if (wifi_connect_change || bt_state_change || rssi_state_change)
  1515. rtl92c_check_bt_change(hw);
  1516. }
  1517. }
  1518. EXPORT_SYMBOL(rtl92c_dm_bt_coexist);