rx.c 22 KB

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  1. /****************************************************************************
  2. * Driver for Solarflare Solarstorm network controllers and boards
  3. * Copyright 2005-2006 Fen Systems Ltd.
  4. * Copyright 2005-2011 Solarflare Communications Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify it
  7. * under the terms of the GNU General Public License version 2 as published
  8. * by the Free Software Foundation, incorporated herein by reference.
  9. */
  10. #include <linux/socket.h>
  11. #include <linux/in.h>
  12. #include <linux/slab.h>
  13. #include <linux/ip.h>
  14. #include <linux/tcp.h>
  15. #include <linux/udp.h>
  16. #include <linux/prefetch.h>
  17. #include <linux/moduleparam.h>
  18. #include <net/ip.h>
  19. #include <net/checksum.h>
  20. #include "net_driver.h"
  21. #include "efx.h"
  22. #include "nic.h"
  23. #include "selftest.h"
  24. #include "workarounds.h"
  25. /* Number of RX descriptors pushed at once. */
  26. #define EFX_RX_BATCH 8
  27. /* Maximum size of a buffer sharing a page */
  28. #define EFX_RX_HALF_PAGE ((PAGE_SIZE >> 1) - sizeof(struct efx_rx_page_state))
  29. /* Size of buffer allocated for skb header area. */
  30. #define EFX_SKB_HEADERS 64u
  31. /*
  32. * rx_alloc_method - RX buffer allocation method
  33. *
  34. * This driver supports two methods for allocating and using RX buffers:
  35. * each RX buffer may be backed by an skb or by an order-n page.
  36. *
  37. * When GRO is in use then the second method has a lower overhead,
  38. * since we don't have to allocate then free skbs on reassembled frames.
  39. *
  40. * Values:
  41. * - RX_ALLOC_METHOD_AUTO = 0
  42. * - RX_ALLOC_METHOD_SKB = 1
  43. * - RX_ALLOC_METHOD_PAGE = 2
  44. *
  45. * The heuristic for %RX_ALLOC_METHOD_AUTO is a simple hysteresis count
  46. * controlled by the parameters below.
  47. *
  48. * - Since pushing and popping descriptors are separated by the rx_queue
  49. * size, so the watermarks should be ~rxd_size.
  50. * - The performance win by using page-based allocation for GRO is less
  51. * than the performance hit of using page-based allocation of non-GRO,
  52. * so the watermarks should reflect this.
  53. *
  54. * Per channel we maintain a single variable, updated by each channel:
  55. *
  56. * rx_alloc_level += (gro_performed ? RX_ALLOC_FACTOR_GRO :
  57. * RX_ALLOC_FACTOR_SKB)
  58. * Per NAPI poll interval, we constrain rx_alloc_level to 0..MAX (which
  59. * limits the hysteresis), and update the allocation strategy:
  60. *
  61. * rx_alloc_method = (rx_alloc_level > RX_ALLOC_LEVEL_GRO ?
  62. * RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB)
  63. */
  64. static int rx_alloc_method = RX_ALLOC_METHOD_AUTO;
  65. #define RX_ALLOC_LEVEL_GRO 0x2000
  66. #define RX_ALLOC_LEVEL_MAX 0x3000
  67. #define RX_ALLOC_FACTOR_GRO 1
  68. #define RX_ALLOC_FACTOR_SKB (-2)
  69. /* This is the percentage fill level below which new RX descriptors
  70. * will be added to the RX descriptor ring.
  71. */
  72. static unsigned int rx_refill_threshold = 90;
  73. /* This is the percentage fill level to which an RX queue will be refilled
  74. * when the "RX refill threshold" is reached.
  75. */
  76. static unsigned int rx_refill_limit = 95;
  77. /*
  78. * RX maximum head room required.
  79. *
  80. * This must be at least 1 to prevent overflow and at least 2 to allow
  81. * pipelined receives.
  82. */
  83. #define EFX_RXD_HEAD_ROOM 2
  84. /* Offset of ethernet header within page */
  85. static inline unsigned int efx_rx_buf_offset(struct efx_nic *efx,
  86. struct efx_rx_buffer *buf)
  87. {
  88. /* Offset is always within one page, so we don't need to consider
  89. * the page order.
  90. */
  91. return ((unsigned int) buf->dma_addr & (PAGE_SIZE - 1)) +
  92. efx->type->rx_buffer_hash_size;
  93. }
  94. static inline unsigned int efx_rx_buf_size(struct efx_nic *efx)
  95. {
  96. return PAGE_SIZE << efx->rx_buffer_order;
  97. }
  98. static u8 *efx_rx_buf_eh(struct efx_nic *efx, struct efx_rx_buffer *buf)
  99. {
  100. if (buf->flags & EFX_RX_BUF_PAGE)
  101. return page_address(buf->u.page) + efx_rx_buf_offset(efx, buf);
  102. else
  103. return (u8 *)buf->u.skb->data + efx->type->rx_buffer_hash_size;
  104. }
  105. static inline u32 efx_rx_buf_hash(const u8 *eh)
  106. {
  107. /* The ethernet header is always directly after any hash. */
  108. #if defined(CONFIG_HAVE_EFFICIENT_UNALIGNED_ACCESS) || NET_IP_ALIGN % 4 == 0
  109. return __le32_to_cpup((const __le32 *)(eh - 4));
  110. #else
  111. const u8 *data = eh - 4;
  112. return (u32)data[0] |
  113. (u32)data[1] << 8 |
  114. (u32)data[2] << 16 |
  115. (u32)data[3] << 24;
  116. #endif
  117. }
  118. /**
  119. * efx_init_rx_buffers_skb - create EFX_RX_BATCH skb-based RX buffers
  120. *
  121. * @rx_queue: Efx RX queue
  122. *
  123. * This allocates EFX_RX_BATCH skbs, maps them for DMA, and populates a
  124. * struct efx_rx_buffer for each one. Return a negative error code or 0
  125. * on success. May fail having only inserted fewer than EFX_RX_BATCH
  126. * buffers.
  127. */
  128. static int efx_init_rx_buffers_skb(struct efx_rx_queue *rx_queue)
  129. {
  130. struct efx_nic *efx = rx_queue->efx;
  131. struct net_device *net_dev = efx->net_dev;
  132. struct efx_rx_buffer *rx_buf;
  133. struct sk_buff *skb;
  134. int skb_len = efx->rx_buffer_len;
  135. unsigned index, count;
  136. for (count = 0; count < EFX_RX_BATCH; ++count) {
  137. index = rx_queue->added_count & rx_queue->ptr_mask;
  138. rx_buf = efx_rx_buffer(rx_queue, index);
  139. rx_buf->u.skb = skb = netdev_alloc_skb(net_dev, skb_len);
  140. if (unlikely(!skb))
  141. return -ENOMEM;
  142. /* Adjust the SKB for padding */
  143. skb_reserve(skb, NET_IP_ALIGN);
  144. rx_buf->len = skb_len - NET_IP_ALIGN;
  145. rx_buf->flags = 0;
  146. rx_buf->dma_addr = pci_map_single(efx->pci_dev,
  147. skb->data, rx_buf->len,
  148. PCI_DMA_FROMDEVICE);
  149. if (unlikely(pci_dma_mapping_error(efx->pci_dev,
  150. rx_buf->dma_addr))) {
  151. dev_kfree_skb_any(skb);
  152. rx_buf->u.skb = NULL;
  153. return -EIO;
  154. }
  155. ++rx_queue->added_count;
  156. ++rx_queue->alloc_skb_count;
  157. }
  158. return 0;
  159. }
  160. /**
  161. * efx_init_rx_buffers_page - create EFX_RX_BATCH page-based RX buffers
  162. *
  163. * @rx_queue: Efx RX queue
  164. *
  165. * This allocates memory for EFX_RX_BATCH receive buffers, maps them for DMA,
  166. * and populates struct efx_rx_buffers for each one. Return a negative error
  167. * code or 0 on success. If a single page can be split between two buffers,
  168. * then the page will either be inserted fully, or not at at all.
  169. */
  170. static int efx_init_rx_buffers_page(struct efx_rx_queue *rx_queue)
  171. {
  172. struct efx_nic *efx = rx_queue->efx;
  173. struct efx_rx_buffer *rx_buf;
  174. struct page *page;
  175. void *page_addr;
  176. struct efx_rx_page_state *state;
  177. dma_addr_t dma_addr;
  178. unsigned index, count;
  179. /* We can split a page between two buffers */
  180. BUILD_BUG_ON(EFX_RX_BATCH & 1);
  181. for (count = 0; count < EFX_RX_BATCH; ++count) {
  182. page = alloc_pages(__GFP_COLD | __GFP_COMP | GFP_ATOMIC,
  183. efx->rx_buffer_order);
  184. if (unlikely(page == NULL))
  185. return -ENOMEM;
  186. dma_addr = pci_map_page(efx->pci_dev, page, 0,
  187. efx_rx_buf_size(efx),
  188. PCI_DMA_FROMDEVICE);
  189. if (unlikely(pci_dma_mapping_error(efx->pci_dev, dma_addr))) {
  190. __free_pages(page, efx->rx_buffer_order);
  191. return -EIO;
  192. }
  193. page_addr = page_address(page);
  194. state = page_addr;
  195. state->refcnt = 0;
  196. state->dma_addr = dma_addr;
  197. page_addr += sizeof(struct efx_rx_page_state);
  198. dma_addr += sizeof(struct efx_rx_page_state);
  199. split:
  200. index = rx_queue->added_count & rx_queue->ptr_mask;
  201. rx_buf = efx_rx_buffer(rx_queue, index);
  202. rx_buf->dma_addr = dma_addr + EFX_PAGE_IP_ALIGN;
  203. rx_buf->u.page = page;
  204. rx_buf->len = efx->rx_buffer_len - EFX_PAGE_IP_ALIGN;
  205. rx_buf->flags = EFX_RX_BUF_PAGE;
  206. ++rx_queue->added_count;
  207. ++rx_queue->alloc_page_count;
  208. ++state->refcnt;
  209. if ((~count & 1) && (efx->rx_buffer_len <= EFX_RX_HALF_PAGE)) {
  210. /* Use the second half of the page */
  211. get_page(page);
  212. dma_addr += (PAGE_SIZE >> 1);
  213. page_addr += (PAGE_SIZE >> 1);
  214. ++count;
  215. goto split;
  216. }
  217. }
  218. return 0;
  219. }
  220. static void efx_unmap_rx_buffer(struct efx_nic *efx,
  221. struct efx_rx_buffer *rx_buf)
  222. {
  223. if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) {
  224. struct efx_rx_page_state *state;
  225. state = page_address(rx_buf->u.page);
  226. if (--state->refcnt == 0) {
  227. pci_unmap_page(efx->pci_dev,
  228. state->dma_addr,
  229. efx_rx_buf_size(efx),
  230. PCI_DMA_FROMDEVICE);
  231. }
  232. } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) {
  233. pci_unmap_single(efx->pci_dev, rx_buf->dma_addr,
  234. rx_buf->len, PCI_DMA_FROMDEVICE);
  235. }
  236. }
  237. static void efx_free_rx_buffer(struct efx_nic *efx,
  238. struct efx_rx_buffer *rx_buf)
  239. {
  240. if ((rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.page) {
  241. __free_pages(rx_buf->u.page, efx->rx_buffer_order);
  242. rx_buf->u.page = NULL;
  243. } else if (!(rx_buf->flags & EFX_RX_BUF_PAGE) && rx_buf->u.skb) {
  244. dev_kfree_skb_any(rx_buf->u.skb);
  245. rx_buf->u.skb = NULL;
  246. }
  247. }
  248. static void efx_fini_rx_buffer(struct efx_rx_queue *rx_queue,
  249. struct efx_rx_buffer *rx_buf)
  250. {
  251. efx_unmap_rx_buffer(rx_queue->efx, rx_buf);
  252. efx_free_rx_buffer(rx_queue->efx, rx_buf);
  253. }
  254. /* Attempt to resurrect the other receive buffer that used to share this page,
  255. * which had previously been passed up to the kernel and freed. */
  256. static void efx_resurrect_rx_buffer(struct efx_rx_queue *rx_queue,
  257. struct efx_rx_buffer *rx_buf)
  258. {
  259. struct efx_rx_page_state *state = page_address(rx_buf->u.page);
  260. struct efx_rx_buffer *new_buf;
  261. unsigned fill_level, index;
  262. /* +1 because efx_rx_packet() incremented removed_count. +1 because
  263. * we'd like to insert an additional descriptor whilst leaving
  264. * EFX_RXD_HEAD_ROOM for the non-recycle path */
  265. fill_level = (rx_queue->added_count - rx_queue->removed_count + 2);
  266. if (unlikely(fill_level > rx_queue->max_fill)) {
  267. /* We could place "state" on a list, and drain the list in
  268. * efx_fast_push_rx_descriptors(). For now, this will do. */
  269. return;
  270. }
  271. ++state->refcnt;
  272. get_page(rx_buf->u.page);
  273. index = rx_queue->added_count & rx_queue->ptr_mask;
  274. new_buf = efx_rx_buffer(rx_queue, index);
  275. new_buf->dma_addr = rx_buf->dma_addr ^ (PAGE_SIZE >> 1);
  276. new_buf->u.page = rx_buf->u.page;
  277. new_buf->len = rx_buf->len;
  278. new_buf->flags = EFX_RX_BUF_PAGE;
  279. ++rx_queue->added_count;
  280. }
  281. /* Recycle the given rx buffer directly back into the rx_queue. There is
  282. * always room to add this buffer, because we've just popped a buffer. */
  283. static void efx_recycle_rx_buffer(struct efx_channel *channel,
  284. struct efx_rx_buffer *rx_buf)
  285. {
  286. struct efx_nic *efx = channel->efx;
  287. struct efx_rx_queue *rx_queue = efx_channel_get_rx_queue(channel);
  288. struct efx_rx_buffer *new_buf;
  289. unsigned index;
  290. rx_buf->flags &= EFX_RX_BUF_PAGE;
  291. if ((rx_buf->flags & EFX_RX_BUF_PAGE) &&
  292. efx->rx_buffer_len <= EFX_RX_HALF_PAGE &&
  293. page_count(rx_buf->u.page) == 1)
  294. efx_resurrect_rx_buffer(rx_queue, rx_buf);
  295. index = rx_queue->added_count & rx_queue->ptr_mask;
  296. new_buf = efx_rx_buffer(rx_queue, index);
  297. memcpy(new_buf, rx_buf, sizeof(*new_buf));
  298. rx_buf->u.page = NULL;
  299. ++rx_queue->added_count;
  300. }
  301. /**
  302. * efx_fast_push_rx_descriptors - push new RX descriptors quickly
  303. * @rx_queue: RX descriptor queue
  304. * This will aim to fill the RX descriptor queue up to
  305. * @rx_queue->@fast_fill_limit. If there is insufficient atomic
  306. * memory to do so, a slow fill will be scheduled.
  307. *
  308. * The caller must provide serialisation (none is used here). In practise,
  309. * this means this function must run from the NAPI handler, or be called
  310. * when NAPI is disabled.
  311. */
  312. void efx_fast_push_rx_descriptors(struct efx_rx_queue *rx_queue)
  313. {
  314. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  315. unsigned fill_level;
  316. int space, rc = 0;
  317. /* Calculate current fill level, and exit if we don't need to fill */
  318. fill_level = (rx_queue->added_count - rx_queue->removed_count);
  319. EFX_BUG_ON_PARANOID(fill_level > rx_queue->efx->rxq_entries);
  320. if (fill_level >= rx_queue->fast_fill_trigger)
  321. goto out;
  322. /* Record minimum fill level */
  323. if (unlikely(fill_level < rx_queue->min_fill)) {
  324. if (fill_level)
  325. rx_queue->min_fill = fill_level;
  326. }
  327. space = rx_queue->fast_fill_limit - fill_level;
  328. if (space < EFX_RX_BATCH)
  329. goto out;
  330. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  331. "RX queue %d fast-filling descriptor ring from"
  332. " level %d to level %d using %s allocation\n",
  333. efx_rx_queue_index(rx_queue), fill_level,
  334. rx_queue->fast_fill_limit,
  335. channel->rx_alloc_push_pages ? "page" : "skb");
  336. do {
  337. if (channel->rx_alloc_push_pages)
  338. rc = efx_init_rx_buffers_page(rx_queue);
  339. else
  340. rc = efx_init_rx_buffers_skb(rx_queue);
  341. if (unlikely(rc)) {
  342. /* Ensure that we don't leave the rx queue empty */
  343. if (rx_queue->added_count == rx_queue->removed_count)
  344. efx_schedule_slow_fill(rx_queue);
  345. goto out;
  346. }
  347. } while ((space -= EFX_RX_BATCH) >= EFX_RX_BATCH);
  348. netif_vdbg(rx_queue->efx, rx_status, rx_queue->efx->net_dev,
  349. "RX queue %d fast-filled descriptor ring "
  350. "to level %d\n", efx_rx_queue_index(rx_queue),
  351. rx_queue->added_count - rx_queue->removed_count);
  352. out:
  353. if (rx_queue->notified_count != rx_queue->added_count)
  354. efx_nic_notify_rx_desc(rx_queue);
  355. }
  356. void efx_rx_slow_fill(unsigned long context)
  357. {
  358. struct efx_rx_queue *rx_queue = (struct efx_rx_queue *)context;
  359. /* Post an event to cause NAPI to run and refill the queue */
  360. efx_nic_generate_fill_event(rx_queue);
  361. ++rx_queue->slow_fill_count;
  362. }
  363. static void efx_rx_packet__check_len(struct efx_rx_queue *rx_queue,
  364. struct efx_rx_buffer *rx_buf,
  365. int len, bool *leak_packet)
  366. {
  367. struct efx_nic *efx = rx_queue->efx;
  368. unsigned max_len = rx_buf->len - efx->type->rx_buffer_padding;
  369. if (likely(len <= max_len))
  370. return;
  371. /* The packet must be discarded, but this is only a fatal error
  372. * if the caller indicated it was
  373. */
  374. rx_buf->flags |= EFX_RX_PKT_DISCARD;
  375. if ((len > rx_buf->len) && EFX_WORKAROUND_8071(efx)) {
  376. if (net_ratelimit())
  377. netif_err(efx, rx_err, efx->net_dev,
  378. " RX queue %d seriously overlength "
  379. "RX event (0x%x > 0x%x+0x%x). Leaking\n",
  380. efx_rx_queue_index(rx_queue), len, max_len,
  381. efx->type->rx_buffer_padding);
  382. /* If this buffer was skb-allocated, then the meta
  383. * data at the end of the skb will be trashed. So
  384. * we have no choice but to leak the fragment.
  385. */
  386. *leak_packet = !(rx_buf->flags & EFX_RX_BUF_PAGE);
  387. efx_schedule_reset(efx, RESET_TYPE_RX_RECOVERY);
  388. } else {
  389. if (net_ratelimit())
  390. netif_err(efx, rx_err, efx->net_dev,
  391. " RX queue %d overlength RX event "
  392. "(0x%x > 0x%x)\n",
  393. efx_rx_queue_index(rx_queue), len, max_len);
  394. }
  395. efx_rx_queue_channel(rx_queue)->n_rx_overlength++;
  396. }
  397. /* Pass a received packet up through the generic GRO stack
  398. *
  399. * Handles driverlink veto, and passes the fragment up via
  400. * the appropriate GRO method
  401. */
  402. static void efx_rx_packet_gro(struct efx_channel *channel,
  403. struct efx_rx_buffer *rx_buf,
  404. const u8 *eh)
  405. {
  406. struct napi_struct *napi = &channel->napi_str;
  407. gro_result_t gro_result;
  408. /* Pass the skb/page into the GRO engine */
  409. if (rx_buf->flags & EFX_RX_BUF_PAGE) {
  410. struct efx_nic *efx = channel->efx;
  411. struct page *page = rx_buf->u.page;
  412. struct sk_buff *skb;
  413. rx_buf->u.page = NULL;
  414. skb = napi_get_frags(napi);
  415. if (!skb) {
  416. put_page(page);
  417. return;
  418. }
  419. if (efx->net_dev->features & NETIF_F_RXHASH)
  420. skb->rxhash = efx_rx_buf_hash(eh);
  421. skb_fill_page_desc(skb, 0, page,
  422. efx_rx_buf_offset(efx, rx_buf), rx_buf->len);
  423. skb->len = rx_buf->len;
  424. skb->data_len = rx_buf->len;
  425. skb->truesize += rx_buf->len;
  426. skb->ip_summed = ((rx_buf->flags & EFX_RX_PKT_CSUMMED) ?
  427. CHECKSUM_UNNECESSARY : CHECKSUM_NONE);
  428. skb_record_rx_queue(skb, channel->channel);
  429. gro_result = napi_gro_frags(napi);
  430. } else {
  431. struct sk_buff *skb = rx_buf->u.skb;
  432. EFX_BUG_ON_PARANOID(!(rx_buf->flags & EFX_RX_PKT_CSUMMED));
  433. rx_buf->u.skb = NULL;
  434. skb->ip_summed = CHECKSUM_UNNECESSARY;
  435. gro_result = napi_gro_receive(napi, skb);
  436. }
  437. if (gro_result == GRO_NORMAL) {
  438. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  439. } else if (gro_result != GRO_DROP) {
  440. channel->rx_alloc_level += RX_ALLOC_FACTOR_GRO;
  441. channel->irq_mod_score += 2;
  442. }
  443. }
  444. void efx_rx_packet(struct efx_rx_queue *rx_queue, unsigned int index,
  445. unsigned int len, u16 flags)
  446. {
  447. struct efx_nic *efx = rx_queue->efx;
  448. struct efx_channel *channel = efx_rx_queue_channel(rx_queue);
  449. struct efx_rx_buffer *rx_buf;
  450. bool leak_packet = false;
  451. rx_buf = efx_rx_buffer(rx_queue, index);
  452. rx_buf->flags |= flags;
  453. /* This allows the refill path to post another buffer.
  454. * EFX_RXD_HEAD_ROOM ensures that the slot we are using
  455. * isn't overwritten yet.
  456. */
  457. rx_queue->removed_count++;
  458. /* Validate the length encoded in the event vs the descriptor pushed */
  459. efx_rx_packet__check_len(rx_queue, rx_buf, len, &leak_packet);
  460. netif_vdbg(efx, rx_status, efx->net_dev,
  461. "RX queue %d received id %x at %llx+%x %s%s\n",
  462. efx_rx_queue_index(rx_queue), index,
  463. (unsigned long long)rx_buf->dma_addr, len,
  464. (rx_buf->flags & EFX_RX_PKT_CSUMMED) ? " [SUMMED]" : "",
  465. (rx_buf->flags & EFX_RX_PKT_DISCARD) ? " [DISCARD]" : "");
  466. /* Discard packet, if instructed to do so */
  467. if (unlikely(rx_buf->flags & EFX_RX_PKT_DISCARD)) {
  468. if (unlikely(leak_packet))
  469. channel->n_skbuff_leaks++;
  470. else
  471. efx_recycle_rx_buffer(channel, rx_buf);
  472. /* Don't hold off the previous receive */
  473. rx_buf = NULL;
  474. goto out;
  475. }
  476. /* Release card resources - assumes all RX buffers consumed in-order
  477. * per RX queue
  478. */
  479. efx_unmap_rx_buffer(efx, rx_buf);
  480. /* Prefetch nice and early so data will (hopefully) be in cache by
  481. * the time we look at it.
  482. */
  483. prefetch(efx_rx_buf_eh(efx, rx_buf));
  484. /* Pipeline receives so that we give time for packet headers to be
  485. * prefetched into cache.
  486. */
  487. rx_buf->len = len - efx->type->rx_buffer_hash_size;
  488. out:
  489. if (channel->rx_pkt)
  490. __efx_rx_packet(channel, channel->rx_pkt);
  491. channel->rx_pkt = rx_buf;
  492. }
  493. static void efx_rx_deliver(struct efx_channel *channel,
  494. struct efx_rx_buffer *rx_buf)
  495. {
  496. struct sk_buff *skb;
  497. /* We now own the SKB */
  498. skb = rx_buf->u.skb;
  499. rx_buf->u.skb = NULL;
  500. /* Set the SKB flags */
  501. skb_checksum_none_assert(skb);
  502. /* Pass the packet up */
  503. netif_receive_skb(skb);
  504. /* Update allocation strategy method */
  505. channel->rx_alloc_level += RX_ALLOC_FACTOR_SKB;
  506. }
  507. /* Handle a received packet. Second half: Touches packet payload. */
  508. void __efx_rx_packet(struct efx_channel *channel, struct efx_rx_buffer *rx_buf)
  509. {
  510. struct efx_nic *efx = channel->efx;
  511. u8 *eh = efx_rx_buf_eh(efx, rx_buf);
  512. /* If we're in loopback test, then pass the packet directly to the
  513. * loopback layer, and free the rx_buf here
  514. */
  515. if (unlikely(efx->loopback_selftest)) {
  516. efx_loopback_rx_packet(efx, eh, rx_buf->len);
  517. efx_free_rx_buffer(efx, rx_buf);
  518. return;
  519. }
  520. if (!(rx_buf->flags & EFX_RX_BUF_PAGE)) {
  521. struct sk_buff *skb = rx_buf->u.skb;
  522. prefetch(skb_shinfo(skb));
  523. skb_reserve(skb, efx->type->rx_buffer_hash_size);
  524. skb_put(skb, rx_buf->len);
  525. if (efx->net_dev->features & NETIF_F_RXHASH)
  526. skb->rxhash = efx_rx_buf_hash(eh);
  527. /* Move past the ethernet header. rx_buf->data still points
  528. * at the ethernet header */
  529. skb->protocol = eth_type_trans(skb, efx->net_dev);
  530. skb_record_rx_queue(skb, channel->channel);
  531. }
  532. if (unlikely(!(efx->net_dev->features & NETIF_F_RXCSUM)))
  533. rx_buf->flags &= ~EFX_RX_PKT_CSUMMED;
  534. if (likely(rx_buf->flags & (EFX_RX_BUF_PAGE | EFX_RX_PKT_CSUMMED)))
  535. efx_rx_packet_gro(channel, rx_buf, eh);
  536. else
  537. efx_rx_deliver(channel, rx_buf);
  538. }
  539. void efx_rx_strategy(struct efx_channel *channel)
  540. {
  541. enum efx_rx_alloc_method method = rx_alloc_method;
  542. /* Only makes sense to use page based allocation if GRO is enabled */
  543. if (!(channel->efx->net_dev->features & NETIF_F_GRO)) {
  544. method = RX_ALLOC_METHOD_SKB;
  545. } else if (method == RX_ALLOC_METHOD_AUTO) {
  546. /* Constrain the rx_alloc_level */
  547. if (channel->rx_alloc_level < 0)
  548. channel->rx_alloc_level = 0;
  549. else if (channel->rx_alloc_level > RX_ALLOC_LEVEL_MAX)
  550. channel->rx_alloc_level = RX_ALLOC_LEVEL_MAX;
  551. /* Decide on the allocation method */
  552. method = ((channel->rx_alloc_level > RX_ALLOC_LEVEL_GRO) ?
  553. RX_ALLOC_METHOD_PAGE : RX_ALLOC_METHOD_SKB);
  554. }
  555. /* Push the option */
  556. channel->rx_alloc_push_pages = (method == RX_ALLOC_METHOD_PAGE);
  557. }
  558. int efx_probe_rx_queue(struct efx_rx_queue *rx_queue)
  559. {
  560. struct efx_nic *efx = rx_queue->efx;
  561. unsigned int entries;
  562. int rc;
  563. /* Create the smallest power-of-two aligned ring */
  564. entries = max(roundup_pow_of_two(efx->rxq_entries), EFX_MIN_DMAQ_SIZE);
  565. EFX_BUG_ON_PARANOID(entries > EFX_MAX_DMAQ_SIZE);
  566. rx_queue->ptr_mask = entries - 1;
  567. netif_dbg(efx, probe, efx->net_dev,
  568. "creating RX queue %d size %#x mask %#x\n",
  569. efx_rx_queue_index(rx_queue), efx->rxq_entries,
  570. rx_queue->ptr_mask);
  571. /* Allocate RX buffers */
  572. rx_queue->buffer = kcalloc(entries, sizeof(*rx_queue->buffer),
  573. GFP_KERNEL);
  574. if (!rx_queue->buffer)
  575. return -ENOMEM;
  576. rc = efx_nic_probe_rx(rx_queue);
  577. if (rc) {
  578. kfree(rx_queue->buffer);
  579. rx_queue->buffer = NULL;
  580. }
  581. return rc;
  582. }
  583. void efx_init_rx_queue(struct efx_rx_queue *rx_queue)
  584. {
  585. struct efx_nic *efx = rx_queue->efx;
  586. unsigned int max_fill, trigger, limit;
  587. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  588. "initialising RX queue %d\n", efx_rx_queue_index(rx_queue));
  589. /* Initialise ptr fields */
  590. rx_queue->added_count = 0;
  591. rx_queue->notified_count = 0;
  592. rx_queue->removed_count = 0;
  593. rx_queue->min_fill = -1U;
  594. /* Initialise limit fields */
  595. max_fill = efx->rxq_entries - EFX_RXD_HEAD_ROOM;
  596. trigger = max_fill * min(rx_refill_threshold, 100U) / 100U;
  597. limit = max_fill * min(rx_refill_limit, 100U) / 100U;
  598. rx_queue->max_fill = max_fill;
  599. rx_queue->fast_fill_trigger = trigger;
  600. rx_queue->fast_fill_limit = limit;
  601. /* Set up RX descriptor ring */
  602. rx_queue->enabled = true;
  603. efx_nic_init_rx(rx_queue);
  604. }
  605. void efx_fini_rx_queue(struct efx_rx_queue *rx_queue)
  606. {
  607. int i;
  608. struct efx_rx_buffer *rx_buf;
  609. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  610. "shutting down RX queue %d\n", efx_rx_queue_index(rx_queue));
  611. /* A flush failure might have left rx_queue->enabled */
  612. rx_queue->enabled = false;
  613. del_timer_sync(&rx_queue->slow_fill);
  614. efx_nic_fini_rx(rx_queue);
  615. /* Release RX buffers NB start at index 0 not current HW ptr */
  616. if (rx_queue->buffer) {
  617. for (i = 0; i <= rx_queue->ptr_mask; i++) {
  618. rx_buf = efx_rx_buffer(rx_queue, i);
  619. efx_fini_rx_buffer(rx_queue, rx_buf);
  620. }
  621. }
  622. }
  623. void efx_remove_rx_queue(struct efx_rx_queue *rx_queue)
  624. {
  625. netif_dbg(rx_queue->efx, drv, rx_queue->efx->net_dev,
  626. "destroying RX queue %d\n", efx_rx_queue_index(rx_queue));
  627. efx_nic_remove_rx(rx_queue);
  628. kfree(rx_queue->buffer);
  629. rx_queue->buffer = NULL;
  630. }
  631. module_param(rx_alloc_method, int, 0644);
  632. MODULE_PARM_DESC(rx_alloc_method, "Allocation method used for RX buffers");
  633. module_param(rx_refill_threshold, uint, 0444);
  634. MODULE_PARM_DESC(rx_refill_threshold,
  635. "RX descriptor ring fast/slow fill threshold (%)");