cnic.c 144 KB

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  1. /* cnic.c: Broadcom CNIC core network driver.
  2. *
  3. * Copyright (c) 2006-2012 Broadcom Corporation
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation.
  8. *
  9. * Original skeleton written by: John(Zongxi) Chen (zongxi@broadcom.com)
  10. * Modified and maintained by: Michael Chan <mchan@broadcom.com>
  11. */
  12. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/slab.h>
  18. #include <linux/pci.h>
  19. #include <linux/init.h>
  20. #include <linux/netdevice.h>
  21. #include <linux/uio_driver.h>
  22. #include <linux/in.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/delay.h>
  25. #include <linux/ethtool.h>
  26. #include <linux/if_vlan.h>
  27. #include <linux/prefetch.h>
  28. #include <linux/random.h>
  29. #if defined(CONFIG_VLAN_8021Q) || defined(CONFIG_VLAN_8021Q_MODULE)
  30. #define BCM_VLAN 1
  31. #endif
  32. #include <net/ip.h>
  33. #include <net/tcp.h>
  34. #include <net/route.h>
  35. #include <net/ipv6.h>
  36. #include <net/ip6_route.h>
  37. #include <net/ip6_checksum.h>
  38. #include <scsi/iscsi_if.h>
  39. #include "cnic_if.h"
  40. #include "bnx2.h"
  41. #include "bnx2x/bnx2x_reg.h"
  42. #include "bnx2x/bnx2x_fw_defs.h"
  43. #include "bnx2x/bnx2x_hsi.h"
  44. #include "../../../scsi/bnx2i/57xx_iscsi_constants.h"
  45. #include "../../../scsi/bnx2i/57xx_iscsi_hsi.h"
  46. #include "cnic.h"
  47. #include "cnic_defs.h"
  48. #define DRV_MODULE_NAME "cnic"
  49. static char version[] __devinitdata =
  50. "Broadcom NetXtreme II CNIC Driver " DRV_MODULE_NAME " v" CNIC_MODULE_VERSION " (" CNIC_MODULE_RELDATE ")\n";
  51. MODULE_AUTHOR("Michael Chan <mchan@broadcom.com> and John(Zongxi) "
  52. "Chen (zongxi@broadcom.com");
  53. MODULE_DESCRIPTION("Broadcom NetXtreme II CNIC Driver");
  54. MODULE_LICENSE("GPL");
  55. MODULE_VERSION(CNIC_MODULE_VERSION);
  56. /* cnic_dev_list modifications are protected by both rtnl and cnic_dev_lock */
  57. static LIST_HEAD(cnic_dev_list);
  58. static LIST_HEAD(cnic_udev_list);
  59. static DEFINE_RWLOCK(cnic_dev_lock);
  60. static DEFINE_MUTEX(cnic_lock);
  61. static struct cnic_ulp_ops __rcu *cnic_ulp_tbl[MAX_CNIC_ULP_TYPE];
  62. /* helper function, assuming cnic_lock is held */
  63. static inline struct cnic_ulp_ops *cnic_ulp_tbl_prot(int type)
  64. {
  65. return rcu_dereference_protected(cnic_ulp_tbl[type],
  66. lockdep_is_held(&cnic_lock));
  67. }
  68. static int cnic_service_bnx2(void *, void *);
  69. static int cnic_service_bnx2x(void *, void *);
  70. static int cnic_ctl(void *, struct cnic_ctl_info *);
  71. static struct cnic_ops cnic_bnx2_ops = {
  72. .cnic_owner = THIS_MODULE,
  73. .cnic_handler = cnic_service_bnx2,
  74. .cnic_ctl = cnic_ctl,
  75. };
  76. static struct cnic_ops cnic_bnx2x_ops = {
  77. .cnic_owner = THIS_MODULE,
  78. .cnic_handler = cnic_service_bnx2x,
  79. .cnic_ctl = cnic_ctl,
  80. };
  81. static struct workqueue_struct *cnic_wq;
  82. static void cnic_shutdown_rings(struct cnic_dev *);
  83. static void cnic_init_rings(struct cnic_dev *);
  84. static int cnic_cm_set_pg(struct cnic_sock *);
  85. static int cnic_uio_open(struct uio_info *uinfo, struct inode *inode)
  86. {
  87. struct cnic_uio_dev *udev = uinfo->priv;
  88. struct cnic_dev *dev;
  89. if (!capable(CAP_NET_ADMIN))
  90. return -EPERM;
  91. if (udev->uio_dev != -1)
  92. return -EBUSY;
  93. rtnl_lock();
  94. dev = udev->dev;
  95. if (!dev || !test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  96. rtnl_unlock();
  97. return -ENODEV;
  98. }
  99. udev->uio_dev = iminor(inode);
  100. cnic_shutdown_rings(dev);
  101. cnic_init_rings(dev);
  102. rtnl_unlock();
  103. return 0;
  104. }
  105. static int cnic_uio_close(struct uio_info *uinfo, struct inode *inode)
  106. {
  107. struct cnic_uio_dev *udev = uinfo->priv;
  108. udev->uio_dev = -1;
  109. return 0;
  110. }
  111. static inline void cnic_hold(struct cnic_dev *dev)
  112. {
  113. atomic_inc(&dev->ref_count);
  114. }
  115. static inline void cnic_put(struct cnic_dev *dev)
  116. {
  117. atomic_dec(&dev->ref_count);
  118. }
  119. static inline void csk_hold(struct cnic_sock *csk)
  120. {
  121. atomic_inc(&csk->ref_count);
  122. }
  123. static inline void csk_put(struct cnic_sock *csk)
  124. {
  125. atomic_dec(&csk->ref_count);
  126. }
  127. static struct cnic_dev *cnic_from_netdev(struct net_device *netdev)
  128. {
  129. struct cnic_dev *cdev;
  130. read_lock(&cnic_dev_lock);
  131. list_for_each_entry(cdev, &cnic_dev_list, list) {
  132. if (netdev == cdev->netdev) {
  133. cnic_hold(cdev);
  134. read_unlock(&cnic_dev_lock);
  135. return cdev;
  136. }
  137. }
  138. read_unlock(&cnic_dev_lock);
  139. return NULL;
  140. }
  141. static inline void ulp_get(struct cnic_ulp_ops *ulp_ops)
  142. {
  143. atomic_inc(&ulp_ops->ref_count);
  144. }
  145. static inline void ulp_put(struct cnic_ulp_ops *ulp_ops)
  146. {
  147. atomic_dec(&ulp_ops->ref_count);
  148. }
  149. static void cnic_ctx_wr(struct cnic_dev *dev, u32 cid_addr, u32 off, u32 val)
  150. {
  151. struct cnic_local *cp = dev->cnic_priv;
  152. struct cnic_eth_dev *ethdev = cp->ethdev;
  153. struct drv_ctl_info info;
  154. struct drv_ctl_io *io = &info.data.io;
  155. info.cmd = DRV_CTL_CTX_WR_CMD;
  156. io->cid_addr = cid_addr;
  157. io->offset = off;
  158. io->data = val;
  159. ethdev->drv_ctl(dev->netdev, &info);
  160. }
  161. static void cnic_ctx_tbl_wr(struct cnic_dev *dev, u32 off, dma_addr_t addr)
  162. {
  163. struct cnic_local *cp = dev->cnic_priv;
  164. struct cnic_eth_dev *ethdev = cp->ethdev;
  165. struct drv_ctl_info info;
  166. struct drv_ctl_io *io = &info.data.io;
  167. info.cmd = DRV_CTL_CTXTBL_WR_CMD;
  168. io->offset = off;
  169. io->dma_addr = addr;
  170. ethdev->drv_ctl(dev->netdev, &info);
  171. }
  172. static void cnic_ring_ctl(struct cnic_dev *dev, u32 cid, u32 cl_id, int start)
  173. {
  174. struct cnic_local *cp = dev->cnic_priv;
  175. struct cnic_eth_dev *ethdev = cp->ethdev;
  176. struct drv_ctl_info info;
  177. struct drv_ctl_l2_ring *ring = &info.data.ring;
  178. if (start)
  179. info.cmd = DRV_CTL_START_L2_CMD;
  180. else
  181. info.cmd = DRV_CTL_STOP_L2_CMD;
  182. ring->cid = cid;
  183. ring->client_id = cl_id;
  184. ethdev->drv_ctl(dev->netdev, &info);
  185. }
  186. static void cnic_reg_wr_ind(struct cnic_dev *dev, u32 off, u32 val)
  187. {
  188. struct cnic_local *cp = dev->cnic_priv;
  189. struct cnic_eth_dev *ethdev = cp->ethdev;
  190. struct drv_ctl_info info;
  191. struct drv_ctl_io *io = &info.data.io;
  192. info.cmd = DRV_CTL_IO_WR_CMD;
  193. io->offset = off;
  194. io->data = val;
  195. ethdev->drv_ctl(dev->netdev, &info);
  196. }
  197. static u32 cnic_reg_rd_ind(struct cnic_dev *dev, u32 off)
  198. {
  199. struct cnic_local *cp = dev->cnic_priv;
  200. struct cnic_eth_dev *ethdev = cp->ethdev;
  201. struct drv_ctl_info info;
  202. struct drv_ctl_io *io = &info.data.io;
  203. info.cmd = DRV_CTL_IO_RD_CMD;
  204. io->offset = off;
  205. ethdev->drv_ctl(dev->netdev, &info);
  206. return io->data;
  207. }
  208. static void cnic_ulp_ctl(struct cnic_dev *dev, int ulp_type, bool reg)
  209. {
  210. struct cnic_local *cp = dev->cnic_priv;
  211. struct cnic_eth_dev *ethdev = cp->ethdev;
  212. struct drv_ctl_info info;
  213. if (reg)
  214. info.cmd = DRV_CTL_ULP_REGISTER_CMD;
  215. else
  216. info.cmd = DRV_CTL_ULP_UNREGISTER_CMD;
  217. info.data.ulp_type = ulp_type;
  218. ethdev->drv_ctl(dev->netdev, &info);
  219. }
  220. static int cnic_in_use(struct cnic_sock *csk)
  221. {
  222. return test_bit(SK_F_INUSE, &csk->flags);
  223. }
  224. static void cnic_spq_completion(struct cnic_dev *dev, int cmd, u32 count)
  225. {
  226. struct cnic_local *cp = dev->cnic_priv;
  227. struct cnic_eth_dev *ethdev = cp->ethdev;
  228. struct drv_ctl_info info;
  229. info.cmd = cmd;
  230. info.data.credit.credit_count = count;
  231. ethdev->drv_ctl(dev->netdev, &info);
  232. }
  233. static int cnic_get_l5_cid(struct cnic_local *cp, u32 cid, u32 *l5_cid)
  234. {
  235. u32 i;
  236. for (i = 0; i < cp->max_cid_space; i++) {
  237. if (cp->ctx_tbl[i].cid == cid) {
  238. *l5_cid = i;
  239. return 0;
  240. }
  241. }
  242. return -EINVAL;
  243. }
  244. static int cnic_send_nlmsg(struct cnic_local *cp, u32 type,
  245. struct cnic_sock *csk)
  246. {
  247. struct iscsi_path path_req;
  248. char *buf = NULL;
  249. u16 len = 0;
  250. u32 msg_type = ISCSI_KEVENT_IF_DOWN;
  251. struct cnic_ulp_ops *ulp_ops;
  252. struct cnic_uio_dev *udev = cp->udev;
  253. int rc = 0, retry = 0;
  254. if (!udev || udev->uio_dev == -1)
  255. return -ENODEV;
  256. if (csk) {
  257. len = sizeof(path_req);
  258. buf = (char *) &path_req;
  259. memset(&path_req, 0, len);
  260. msg_type = ISCSI_KEVENT_PATH_REQ;
  261. path_req.handle = (u64) csk->l5_cid;
  262. if (test_bit(SK_F_IPV6, &csk->flags)) {
  263. memcpy(&path_req.dst.v6_addr, &csk->dst_ip[0],
  264. sizeof(struct in6_addr));
  265. path_req.ip_addr_len = 16;
  266. } else {
  267. memcpy(&path_req.dst.v4_addr, &csk->dst_ip[0],
  268. sizeof(struct in_addr));
  269. path_req.ip_addr_len = 4;
  270. }
  271. path_req.vlan_id = csk->vlan_id;
  272. path_req.pmtu = csk->mtu;
  273. }
  274. while (retry < 3) {
  275. rc = 0;
  276. rcu_read_lock();
  277. ulp_ops = rcu_dereference(cnic_ulp_tbl[CNIC_ULP_ISCSI]);
  278. if (ulp_ops)
  279. rc = ulp_ops->iscsi_nl_send_msg(
  280. cp->ulp_handle[CNIC_ULP_ISCSI],
  281. msg_type, buf, len);
  282. rcu_read_unlock();
  283. if (rc == 0 || msg_type != ISCSI_KEVENT_PATH_REQ)
  284. break;
  285. msleep(100);
  286. retry++;
  287. }
  288. return rc;
  289. }
  290. static void cnic_cm_upcall(struct cnic_local *, struct cnic_sock *, u8);
  291. static int cnic_iscsi_nl_msg_recv(struct cnic_dev *dev, u32 msg_type,
  292. char *buf, u16 len)
  293. {
  294. int rc = -EINVAL;
  295. switch (msg_type) {
  296. case ISCSI_UEVENT_PATH_UPDATE: {
  297. struct cnic_local *cp;
  298. u32 l5_cid;
  299. struct cnic_sock *csk;
  300. struct iscsi_path *path_resp;
  301. if (len < sizeof(*path_resp))
  302. break;
  303. path_resp = (struct iscsi_path *) buf;
  304. cp = dev->cnic_priv;
  305. l5_cid = (u32) path_resp->handle;
  306. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  307. break;
  308. rcu_read_lock();
  309. if (!rcu_dereference(cp->ulp_ops[CNIC_ULP_L4])) {
  310. rc = -ENODEV;
  311. rcu_read_unlock();
  312. break;
  313. }
  314. csk = &cp->csk_tbl[l5_cid];
  315. csk_hold(csk);
  316. if (cnic_in_use(csk) &&
  317. test_bit(SK_F_CONNECT_START, &csk->flags)) {
  318. csk->vlan_id = path_resp->vlan_id;
  319. memcpy(csk->ha, path_resp->mac_addr, 6);
  320. if (test_bit(SK_F_IPV6, &csk->flags))
  321. memcpy(&csk->src_ip[0], &path_resp->src.v6_addr,
  322. sizeof(struct in6_addr));
  323. else
  324. memcpy(&csk->src_ip[0], &path_resp->src.v4_addr,
  325. sizeof(struct in_addr));
  326. if (is_valid_ether_addr(csk->ha)) {
  327. cnic_cm_set_pg(csk);
  328. } else if (!test_bit(SK_F_OFFLD_SCHED, &csk->flags) &&
  329. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  330. cnic_cm_upcall(cp, csk,
  331. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  332. clear_bit(SK_F_CONNECT_START, &csk->flags);
  333. }
  334. }
  335. csk_put(csk);
  336. rcu_read_unlock();
  337. rc = 0;
  338. }
  339. }
  340. return rc;
  341. }
  342. static int cnic_offld_prep(struct cnic_sock *csk)
  343. {
  344. if (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  345. return 0;
  346. if (!test_bit(SK_F_CONNECT_START, &csk->flags)) {
  347. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  348. return 0;
  349. }
  350. return 1;
  351. }
  352. static int cnic_close_prep(struct cnic_sock *csk)
  353. {
  354. clear_bit(SK_F_CONNECT_START, &csk->flags);
  355. smp_mb__after_clear_bit();
  356. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  357. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  358. msleep(1);
  359. return 1;
  360. }
  361. return 0;
  362. }
  363. static int cnic_abort_prep(struct cnic_sock *csk)
  364. {
  365. clear_bit(SK_F_CONNECT_START, &csk->flags);
  366. smp_mb__after_clear_bit();
  367. while (test_and_set_bit(SK_F_OFFLD_SCHED, &csk->flags))
  368. msleep(1);
  369. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  370. csk->state = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  371. return 1;
  372. }
  373. return 0;
  374. }
  375. int cnic_register_driver(int ulp_type, struct cnic_ulp_ops *ulp_ops)
  376. {
  377. struct cnic_dev *dev;
  378. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  379. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  380. return -EINVAL;
  381. }
  382. mutex_lock(&cnic_lock);
  383. if (cnic_ulp_tbl_prot(ulp_type)) {
  384. pr_err("%s: Type %d has already been registered\n",
  385. __func__, ulp_type);
  386. mutex_unlock(&cnic_lock);
  387. return -EBUSY;
  388. }
  389. read_lock(&cnic_dev_lock);
  390. list_for_each_entry(dev, &cnic_dev_list, list) {
  391. struct cnic_local *cp = dev->cnic_priv;
  392. clear_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]);
  393. }
  394. read_unlock(&cnic_dev_lock);
  395. atomic_set(&ulp_ops->ref_count, 0);
  396. rcu_assign_pointer(cnic_ulp_tbl[ulp_type], ulp_ops);
  397. mutex_unlock(&cnic_lock);
  398. /* Prevent race conditions with netdev_event */
  399. rtnl_lock();
  400. list_for_each_entry(dev, &cnic_dev_list, list) {
  401. struct cnic_local *cp = dev->cnic_priv;
  402. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[ulp_type]))
  403. ulp_ops->cnic_init(dev);
  404. }
  405. rtnl_unlock();
  406. return 0;
  407. }
  408. int cnic_unregister_driver(int ulp_type)
  409. {
  410. struct cnic_dev *dev;
  411. struct cnic_ulp_ops *ulp_ops;
  412. int i = 0;
  413. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  414. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  415. return -EINVAL;
  416. }
  417. mutex_lock(&cnic_lock);
  418. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  419. if (!ulp_ops) {
  420. pr_err("%s: Type %d has not been registered\n",
  421. __func__, ulp_type);
  422. goto out_unlock;
  423. }
  424. read_lock(&cnic_dev_lock);
  425. list_for_each_entry(dev, &cnic_dev_list, list) {
  426. struct cnic_local *cp = dev->cnic_priv;
  427. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  428. pr_err("%s: Type %d still has devices registered\n",
  429. __func__, ulp_type);
  430. read_unlock(&cnic_dev_lock);
  431. goto out_unlock;
  432. }
  433. }
  434. read_unlock(&cnic_dev_lock);
  435. RCU_INIT_POINTER(cnic_ulp_tbl[ulp_type], NULL);
  436. mutex_unlock(&cnic_lock);
  437. synchronize_rcu();
  438. while ((atomic_read(&ulp_ops->ref_count) != 0) && (i < 20)) {
  439. msleep(100);
  440. i++;
  441. }
  442. if (atomic_read(&ulp_ops->ref_count) != 0)
  443. netdev_warn(dev->netdev, "Failed waiting for ref count to go to zero\n");
  444. return 0;
  445. out_unlock:
  446. mutex_unlock(&cnic_lock);
  447. return -EINVAL;
  448. }
  449. static int cnic_start_hw(struct cnic_dev *);
  450. static void cnic_stop_hw(struct cnic_dev *);
  451. static int cnic_register_device(struct cnic_dev *dev, int ulp_type,
  452. void *ulp_ctx)
  453. {
  454. struct cnic_local *cp = dev->cnic_priv;
  455. struct cnic_ulp_ops *ulp_ops;
  456. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  457. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  458. return -EINVAL;
  459. }
  460. mutex_lock(&cnic_lock);
  461. if (cnic_ulp_tbl_prot(ulp_type) == NULL) {
  462. pr_err("%s: Driver with type %d has not been registered\n",
  463. __func__, ulp_type);
  464. mutex_unlock(&cnic_lock);
  465. return -EAGAIN;
  466. }
  467. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  468. pr_err("%s: Type %d has already been registered to this device\n",
  469. __func__, ulp_type);
  470. mutex_unlock(&cnic_lock);
  471. return -EBUSY;
  472. }
  473. clear_bit(ULP_F_START, &cp->ulp_flags[ulp_type]);
  474. cp->ulp_handle[ulp_type] = ulp_ctx;
  475. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  476. rcu_assign_pointer(cp->ulp_ops[ulp_type], ulp_ops);
  477. cnic_hold(dev);
  478. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  479. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[ulp_type]))
  480. ulp_ops->cnic_start(cp->ulp_handle[ulp_type]);
  481. mutex_unlock(&cnic_lock);
  482. cnic_ulp_ctl(dev, ulp_type, true);
  483. return 0;
  484. }
  485. EXPORT_SYMBOL(cnic_register_driver);
  486. static int cnic_unregister_device(struct cnic_dev *dev, int ulp_type)
  487. {
  488. struct cnic_local *cp = dev->cnic_priv;
  489. int i = 0;
  490. if (ulp_type < 0 || ulp_type >= MAX_CNIC_ULP_TYPE) {
  491. pr_err("%s: Bad type %d\n", __func__, ulp_type);
  492. return -EINVAL;
  493. }
  494. mutex_lock(&cnic_lock);
  495. if (rcu_dereference(cp->ulp_ops[ulp_type])) {
  496. RCU_INIT_POINTER(cp->ulp_ops[ulp_type], NULL);
  497. cnic_put(dev);
  498. } else {
  499. pr_err("%s: device not registered to this ulp type %d\n",
  500. __func__, ulp_type);
  501. mutex_unlock(&cnic_lock);
  502. return -EINVAL;
  503. }
  504. mutex_unlock(&cnic_lock);
  505. if (ulp_type == CNIC_ULP_ISCSI)
  506. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  507. synchronize_rcu();
  508. while (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]) &&
  509. i < 20) {
  510. msleep(100);
  511. i++;
  512. }
  513. if (test_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[ulp_type]))
  514. netdev_warn(dev->netdev, "Failed waiting for ULP up call to complete\n");
  515. cnic_ulp_ctl(dev, ulp_type, false);
  516. return 0;
  517. }
  518. EXPORT_SYMBOL(cnic_unregister_driver);
  519. static int cnic_init_id_tbl(struct cnic_id_tbl *id_tbl, u32 size, u32 start_id,
  520. u32 next)
  521. {
  522. id_tbl->start = start_id;
  523. id_tbl->max = size;
  524. id_tbl->next = next;
  525. spin_lock_init(&id_tbl->lock);
  526. id_tbl->table = kzalloc(DIV_ROUND_UP(size, 32) * 4, GFP_KERNEL);
  527. if (!id_tbl->table)
  528. return -ENOMEM;
  529. return 0;
  530. }
  531. static void cnic_free_id_tbl(struct cnic_id_tbl *id_tbl)
  532. {
  533. kfree(id_tbl->table);
  534. id_tbl->table = NULL;
  535. }
  536. static int cnic_alloc_id(struct cnic_id_tbl *id_tbl, u32 id)
  537. {
  538. int ret = -1;
  539. id -= id_tbl->start;
  540. if (id >= id_tbl->max)
  541. return ret;
  542. spin_lock(&id_tbl->lock);
  543. if (!test_bit(id, id_tbl->table)) {
  544. set_bit(id, id_tbl->table);
  545. ret = 0;
  546. }
  547. spin_unlock(&id_tbl->lock);
  548. return ret;
  549. }
  550. /* Returns -1 if not successful */
  551. static u32 cnic_alloc_new_id(struct cnic_id_tbl *id_tbl)
  552. {
  553. u32 id;
  554. spin_lock(&id_tbl->lock);
  555. id = find_next_zero_bit(id_tbl->table, id_tbl->max, id_tbl->next);
  556. if (id >= id_tbl->max) {
  557. id = -1;
  558. if (id_tbl->next != 0) {
  559. id = find_first_zero_bit(id_tbl->table, id_tbl->next);
  560. if (id >= id_tbl->next)
  561. id = -1;
  562. }
  563. }
  564. if (id < id_tbl->max) {
  565. set_bit(id, id_tbl->table);
  566. id_tbl->next = (id + 1) & (id_tbl->max - 1);
  567. id += id_tbl->start;
  568. }
  569. spin_unlock(&id_tbl->lock);
  570. return id;
  571. }
  572. static void cnic_free_id(struct cnic_id_tbl *id_tbl, u32 id)
  573. {
  574. if (id == -1)
  575. return;
  576. id -= id_tbl->start;
  577. if (id >= id_tbl->max)
  578. return;
  579. clear_bit(id, id_tbl->table);
  580. }
  581. static void cnic_free_dma(struct cnic_dev *dev, struct cnic_dma *dma)
  582. {
  583. int i;
  584. if (!dma->pg_arr)
  585. return;
  586. for (i = 0; i < dma->num_pages; i++) {
  587. if (dma->pg_arr[i]) {
  588. dma_free_coherent(&dev->pcidev->dev, BCM_PAGE_SIZE,
  589. dma->pg_arr[i], dma->pg_map_arr[i]);
  590. dma->pg_arr[i] = NULL;
  591. }
  592. }
  593. if (dma->pgtbl) {
  594. dma_free_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  595. dma->pgtbl, dma->pgtbl_map);
  596. dma->pgtbl = NULL;
  597. }
  598. kfree(dma->pg_arr);
  599. dma->pg_arr = NULL;
  600. dma->num_pages = 0;
  601. }
  602. static void cnic_setup_page_tbl(struct cnic_dev *dev, struct cnic_dma *dma)
  603. {
  604. int i;
  605. __le32 *page_table = (__le32 *) dma->pgtbl;
  606. for (i = 0; i < dma->num_pages; i++) {
  607. /* Each entry needs to be in big endian format. */
  608. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  609. page_table++;
  610. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  611. page_table++;
  612. }
  613. }
  614. static void cnic_setup_page_tbl_le(struct cnic_dev *dev, struct cnic_dma *dma)
  615. {
  616. int i;
  617. __le32 *page_table = (__le32 *) dma->pgtbl;
  618. for (i = 0; i < dma->num_pages; i++) {
  619. /* Each entry needs to be in little endian format. */
  620. *page_table = cpu_to_le32(dma->pg_map_arr[i] & 0xffffffff);
  621. page_table++;
  622. *page_table = cpu_to_le32((u64) dma->pg_map_arr[i] >> 32);
  623. page_table++;
  624. }
  625. }
  626. static int cnic_alloc_dma(struct cnic_dev *dev, struct cnic_dma *dma,
  627. int pages, int use_pg_tbl)
  628. {
  629. int i, size;
  630. struct cnic_local *cp = dev->cnic_priv;
  631. size = pages * (sizeof(void *) + sizeof(dma_addr_t));
  632. dma->pg_arr = kzalloc(size, GFP_ATOMIC);
  633. if (dma->pg_arr == NULL)
  634. return -ENOMEM;
  635. dma->pg_map_arr = (dma_addr_t *) (dma->pg_arr + pages);
  636. dma->num_pages = pages;
  637. for (i = 0; i < pages; i++) {
  638. dma->pg_arr[i] = dma_alloc_coherent(&dev->pcidev->dev,
  639. BCM_PAGE_SIZE,
  640. &dma->pg_map_arr[i],
  641. GFP_ATOMIC);
  642. if (dma->pg_arr[i] == NULL)
  643. goto error;
  644. }
  645. if (!use_pg_tbl)
  646. return 0;
  647. dma->pgtbl_size = ((pages * 8) + BCM_PAGE_SIZE - 1) &
  648. ~(BCM_PAGE_SIZE - 1);
  649. dma->pgtbl = dma_alloc_coherent(&dev->pcidev->dev, dma->pgtbl_size,
  650. &dma->pgtbl_map, GFP_ATOMIC);
  651. if (dma->pgtbl == NULL)
  652. goto error;
  653. cp->setup_pgtbl(dev, dma);
  654. return 0;
  655. error:
  656. cnic_free_dma(dev, dma);
  657. return -ENOMEM;
  658. }
  659. static void cnic_free_context(struct cnic_dev *dev)
  660. {
  661. struct cnic_local *cp = dev->cnic_priv;
  662. int i;
  663. for (i = 0; i < cp->ctx_blks; i++) {
  664. if (cp->ctx_arr[i].ctx) {
  665. dma_free_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  666. cp->ctx_arr[i].ctx,
  667. cp->ctx_arr[i].mapping);
  668. cp->ctx_arr[i].ctx = NULL;
  669. }
  670. }
  671. }
  672. static void __cnic_free_uio(struct cnic_uio_dev *udev)
  673. {
  674. uio_unregister_device(&udev->cnic_uinfo);
  675. if (udev->l2_buf) {
  676. dma_free_coherent(&udev->pdev->dev, udev->l2_buf_size,
  677. udev->l2_buf, udev->l2_buf_map);
  678. udev->l2_buf = NULL;
  679. }
  680. if (udev->l2_ring) {
  681. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  682. udev->l2_ring, udev->l2_ring_map);
  683. udev->l2_ring = NULL;
  684. }
  685. pci_dev_put(udev->pdev);
  686. kfree(udev);
  687. }
  688. static void cnic_free_uio(struct cnic_uio_dev *udev)
  689. {
  690. if (!udev)
  691. return;
  692. write_lock(&cnic_dev_lock);
  693. list_del_init(&udev->list);
  694. write_unlock(&cnic_dev_lock);
  695. __cnic_free_uio(udev);
  696. }
  697. static void cnic_free_resc(struct cnic_dev *dev)
  698. {
  699. struct cnic_local *cp = dev->cnic_priv;
  700. struct cnic_uio_dev *udev = cp->udev;
  701. if (udev) {
  702. udev->dev = NULL;
  703. cp->udev = NULL;
  704. }
  705. cnic_free_context(dev);
  706. kfree(cp->ctx_arr);
  707. cp->ctx_arr = NULL;
  708. cp->ctx_blks = 0;
  709. cnic_free_dma(dev, &cp->gbl_buf_info);
  710. cnic_free_dma(dev, &cp->kwq_info);
  711. cnic_free_dma(dev, &cp->kwq_16_data_info);
  712. cnic_free_dma(dev, &cp->kcq2.dma);
  713. cnic_free_dma(dev, &cp->kcq1.dma);
  714. kfree(cp->iscsi_tbl);
  715. cp->iscsi_tbl = NULL;
  716. kfree(cp->ctx_tbl);
  717. cp->ctx_tbl = NULL;
  718. cnic_free_id_tbl(&cp->fcoe_cid_tbl);
  719. cnic_free_id_tbl(&cp->cid_tbl);
  720. }
  721. static int cnic_alloc_context(struct cnic_dev *dev)
  722. {
  723. struct cnic_local *cp = dev->cnic_priv;
  724. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  725. int i, k, arr_size;
  726. cp->ctx_blk_size = BCM_PAGE_SIZE;
  727. cp->cids_per_blk = BCM_PAGE_SIZE / 128;
  728. arr_size = BNX2_MAX_CID / cp->cids_per_blk *
  729. sizeof(struct cnic_ctx);
  730. cp->ctx_arr = kzalloc(arr_size, GFP_KERNEL);
  731. if (cp->ctx_arr == NULL)
  732. return -ENOMEM;
  733. k = 0;
  734. for (i = 0; i < 2; i++) {
  735. u32 j, reg, off, lo, hi;
  736. if (i == 0)
  737. off = BNX2_PG_CTX_MAP;
  738. else
  739. off = BNX2_ISCSI_CTX_MAP;
  740. reg = cnic_reg_rd_ind(dev, off);
  741. lo = reg >> 16;
  742. hi = reg & 0xffff;
  743. for (j = lo; j < hi; j += cp->cids_per_blk, k++)
  744. cp->ctx_arr[k].cid = j;
  745. }
  746. cp->ctx_blks = k;
  747. if (cp->ctx_blks >= (BNX2_MAX_CID / cp->cids_per_blk)) {
  748. cp->ctx_blks = 0;
  749. return -ENOMEM;
  750. }
  751. for (i = 0; i < cp->ctx_blks; i++) {
  752. cp->ctx_arr[i].ctx =
  753. dma_alloc_coherent(&dev->pcidev->dev,
  754. BCM_PAGE_SIZE,
  755. &cp->ctx_arr[i].mapping,
  756. GFP_KERNEL);
  757. if (cp->ctx_arr[i].ctx == NULL)
  758. return -ENOMEM;
  759. }
  760. }
  761. return 0;
  762. }
  763. static u16 cnic_bnx2_next_idx(u16 idx)
  764. {
  765. return idx + 1;
  766. }
  767. static u16 cnic_bnx2_hw_idx(u16 idx)
  768. {
  769. return idx;
  770. }
  771. static u16 cnic_bnx2x_next_idx(u16 idx)
  772. {
  773. idx++;
  774. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  775. idx++;
  776. return idx;
  777. }
  778. static u16 cnic_bnx2x_hw_idx(u16 idx)
  779. {
  780. if ((idx & MAX_KCQE_CNT) == MAX_KCQE_CNT)
  781. idx++;
  782. return idx;
  783. }
  784. static int cnic_alloc_kcq(struct cnic_dev *dev, struct kcq_info *info,
  785. bool use_pg_tbl)
  786. {
  787. int err, i, use_page_tbl = 0;
  788. struct kcqe **kcq;
  789. if (use_pg_tbl)
  790. use_page_tbl = 1;
  791. err = cnic_alloc_dma(dev, &info->dma, KCQ_PAGE_CNT, use_page_tbl);
  792. if (err)
  793. return err;
  794. kcq = (struct kcqe **) info->dma.pg_arr;
  795. info->kcq = kcq;
  796. info->next_idx = cnic_bnx2_next_idx;
  797. info->hw_idx = cnic_bnx2_hw_idx;
  798. if (use_pg_tbl)
  799. return 0;
  800. info->next_idx = cnic_bnx2x_next_idx;
  801. info->hw_idx = cnic_bnx2x_hw_idx;
  802. for (i = 0; i < KCQ_PAGE_CNT; i++) {
  803. struct bnx2x_bd_chain_next *next =
  804. (struct bnx2x_bd_chain_next *) &kcq[i][MAX_KCQE_CNT];
  805. int j = i + 1;
  806. if (j >= KCQ_PAGE_CNT)
  807. j = 0;
  808. next->addr_hi = (u64) info->dma.pg_map_arr[j] >> 32;
  809. next->addr_lo = info->dma.pg_map_arr[j] & 0xffffffff;
  810. }
  811. return 0;
  812. }
  813. static int cnic_alloc_uio_rings(struct cnic_dev *dev, int pages)
  814. {
  815. struct cnic_local *cp = dev->cnic_priv;
  816. struct cnic_uio_dev *udev;
  817. read_lock(&cnic_dev_lock);
  818. list_for_each_entry(udev, &cnic_udev_list, list) {
  819. if (udev->pdev == dev->pcidev) {
  820. udev->dev = dev;
  821. cp->udev = udev;
  822. read_unlock(&cnic_dev_lock);
  823. return 0;
  824. }
  825. }
  826. read_unlock(&cnic_dev_lock);
  827. udev = kzalloc(sizeof(struct cnic_uio_dev), GFP_ATOMIC);
  828. if (!udev)
  829. return -ENOMEM;
  830. udev->uio_dev = -1;
  831. udev->dev = dev;
  832. udev->pdev = dev->pcidev;
  833. udev->l2_ring_size = pages * BCM_PAGE_SIZE;
  834. udev->l2_ring = dma_alloc_coherent(&udev->pdev->dev, udev->l2_ring_size,
  835. &udev->l2_ring_map,
  836. GFP_KERNEL | __GFP_COMP);
  837. if (!udev->l2_ring)
  838. goto err_udev;
  839. udev->l2_buf_size = (cp->l2_rx_ring_size + 1) * cp->l2_single_buf_size;
  840. udev->l2_buf_size = PAGE_ALIGN(udev->l2_buf_size);
  841. udev->l2_buf = dma_alloc_coherent(&udev->pdev->dev, udev->l2_buf_size,
  842. &udev->l2_buf_map,
  843. GFP_KERNEL | __GFP_COMP);
  844. if (!udev->l2_buf)
  845. goto err_dma;
  846. write_lock(&cnic_dev_lock);
  847. list_add(&udev->list, &cnic_udev_list);
  848. write_unlock(&cnic_dev_lock);
  849. pci_dev_get(udev->pdev);
  850. cp->udev = udev;
  851. return 0;
  852. err_dma:
  853. dma_free_coherent(&udev->pdev->dev, udev->l2_ring_size,
  854. udev->l2_ring, udev->l2_ring_map);
  855. err_udev:
  856. kfree(udev);
  857. return -ENOMEM;
  858. }
  859. static int cnic_init_uio(struct cnic_dev *dev)
  860. {
  861. struct cnic_local *cp = dev->cnic_priv;
  862. struct cnic_uio_dev *udev = cp->udev;
  863. struct uio_info *uinfo;
  864. int ret = 0;
  865. if (!udev)
  866. return -ENOMEM;
  867. uinfo = &udev->cnic_uinfo;
  868. uinfo->mem[0].addr = dev->netdev->base_addr;
  869. uinfo->mem[0].internal_addr = dev->regview;
  870. uinfo->mem[0].size = dev->netdev->mem_end - dev->netdev->mem_start;
  871. uinfo->mem[0].memtype = UIO_MEM_PHYS;
  872. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  873. uinfo->mem[1].addr = (unsigned long) cp->status_blk.gen &
  874. PAGE_MASK;
  875. if (cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  876. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE * 9;
  877. else
  878. uinfo->mem[1].size = BNX2_SBLK_MSIX_ALIGN_SIZE;
  879. uinfo->name = "bnx2_cnic";
  880. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  881. uinfo->mem[1].addr = (unsigned long) cp->bnx2x_def_status_blk &
  882. PAGE_MASK;
  883. uinfo->mem[1].size = sizeof(*cp->bnx2x_def_status_blk);
  884. uinfo->name = "bnx2x_cnic";
  885. }
  886. uinfo->mem[1].memtype = UIO_MEM_LOGICAL;
  887. uinfo->mem[2].addr = (unsigned long) udev->l2_ring;
  888. uinfo->mem[2].size = udev->l2_ring_size;
  889. uinfo->mem[2].memtype = UIO_MEM_LOGICAL;
  890. uinfo->mem[3].addr = (unsigned long) udev->l2_buf;
  891. uinfo->mem[3].size = udev->l2_buf_size;
  892. uinfo->mem[3].memtype = UIO_MEM_LOGICAL;
  893. uinfo->version = CNIC_MODULE_VERSION;
  894. uinfo->irq = UIO_IRQ_CUSTOM;
  895. uinfo->open = cnic_uio_open;
  896. uinfo->release = cnic_uio_close;
  897. if (udev->uio_dev == -1) {
  898. if (!uinfo->priv) {
  899. uinfo->priv = udev;
  900. ret = uio_register_device(&udev->pdev->dev, uinfo);
  901. }
  902. } else {
  903. cnic_init_rings(dev);
  904. }
  905. return ret;
  906. }
  907. static int cnic_alloc_bnx2_resc(struct cnic_dev *dev)
  908. {
  909. struct cnic_local *cp = dev->cnic_priv;
  910. int ret;
  911. ret = cnic_alloc_dma(dev, &cp->kwq_info, KWQ_PAGE_CNT, 1);
  912. if (ret)
  913. goto error;
  914. cp->kwq = (struct kwqe **) cp->kwq_info.pg_arr;
  915. ret = cnic_alloc_kcq(dev, &cp->kcq1, true);
  916. if (ret)
  917. goto error;
  918. ret = cnic_alloc_context(dev);
  919. if (ret)
  920. goto error;
  921. ret = cnic_alloc_uio_rings(dev, 2);
  922. if (ret)
  923. goto error;
  924. ret = cnic_init_uio(dev);
  925. if (ret)
  926. goto error;
  927. return 0;
  928. error:
  929. cnic_free_resc(dev);
  930. return ret;
  931. }
  932. static int cnic_alloc_bnx2x_context(struct cnic_dev *dev)
  933. {
  934. struct cnic_local *cp = dev->cnic_priv;
  935. int ctx_blk_size = cp->ethdev->ctx_blk_size;
  936. int total_mem, blks, i;
  937. total_mem = BNX2X_CONTEXT_MEM_SIZE * cp->max_cid_space;
  938. blks = total_mem / ctx_blk_size;
  939. if (total_mem % ctx_blk_size)
  940. blks++;
  941. if (blks > cp->ethdev->ctx_tbl_len)
  942. return -ENOMEM;
  943. cp->ctx_arr = kcalloc(blks, sizeof(struct cnic_ctx), GFP_KERNEL);
  944. if (cp->ctx_arr == NULL)
  945. return -ENOMEM;
  946. cp->ctx_blks = blks;
  947. cp->ctx_blk_size = ctx_blk_size;
  948. if (!BNX2X_CHIP_IS_57710(cp->chip_id))
  949. cp->ctx_align = 0;
  950. else
  951. cp->ctx_align = ctx_blk_size;
  952. cp->cids_per_blk = ctx_blk_size / BNX2X_CONTEXT_MEM_SIZE;
  953. for (i = 0; i < blks; i++) {
  954. cp->ctx_arr[i].ctx =
  955. dma_alloc_coherent(&dev->pcidev->dev, cp->ctx_blk_size,
  956. &cp->ctx_arr[i].mapping,
  957. GFP_KERNEL);
  958. if (cp->ctx_arr[i].ctx == NULL)
  959. return -ENOMEM;
  960. if (cp->ctx_align && cp->ctx_blk_size == ctx_blk_size) {
  961. if (cp->ctx_arr[i].mapping & (cp->ctx_align - 1)) {
  962. cnic_free_context(dev);
  963. cp->ctx_blk_size += cp->ctx_align;
  964. i = -1;
  965. continue;
  966. }
  967. }
  968. }
  969. return 0;
  970. }
  971. static int cnic_alloc_bnx2x_resc(struct cnic_dev *dev)
  972. {
  973. struct cnic_local *cp = dev->cnic_priv;
  974. struct cnic_eth_dev *ethdev = cp->ethdev;
  975. u32 start_cid = ethdev->starting_cid;
  976. int i, j, n, ret, pages;
  977. struct cnic_dma *kwq_16_dma = &cp->kwq_16_data_info;
  978. cp->iro_arr = ethdev->iro_arr;
  979. cp->max_cid_space = MAX_ISCSI_TBL_SZ;
  980. cp->iscsi_start_cid = start_cid;
  981. cp->fcoe_start_cid = start_cid + MAX_ISCSI_TBL_SZ;
  982. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  983. cp->max_cid_space += dev->max_fcoe_conn;
  984. cp->fcoe_init_cid = ethdev->fcoe_init_cid;
  985. if (!cp->fcoe_init_cid)
  986. cp->fcoe_init_cid = 0x10;
  987. }
  988. cp->iscsi_tbl = kzalloc(sizeof(struct cnic_iscsi) * MAX_ISCSI_TBL_SZ,
  989. GFP_KERNEL);
  990. if (!cp->iscsi_tbl)
  991. goto error;
  992. cp->ctx_tbl = kzalloc(sizeof(struct cnic_context) *
  993. cp->max_cid_space, GFP_KERNEL);
  994. if (!cp->ctx_tbl)
  995. goto error;
  996. for (i = 0; i < MAX_ISCSI_TBL_SZ; i++) {
  997. cp->ctx_tbl[i].proto.iscsi = &cp->iscsi_tbl[i];
  998. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_ISCSI;
  999. }
  1000. for (i = MAX_ISCSI_TBL_SZ; i < cp->max_cid_space; i++)
  1001. cp->ctx_tbl[i].ulp_proto_id = CNIC_ULP_FCOE;
  1002. pages = PAGE_ALIGN(cp->max_cid_space * CNIC_KWQ16_DATA_SIZE) /
  1003. PAGE_SIZE;
  1004. ret = cnic_alloc_dma(dev, kwq_16_dma, pages, 0);
  1005. if (ret)
  1006. return -ENOMEM;
  1007. n = PAGE_SIZE / CNIC_KWQ16_DATA_SIZE;
  1008. for (i = 0, j = 0; i < cp->max_cid_space; i++) {
  1009. long off = CNIC_KWQ16_DATA_SIZE * (i % n);
  1010. cp->ctx_tbl[i].kwqe_data = kwq_16_dma->pg_arr[j] + off;
  1011. cp->ctx_tbl[i].kwqe_data_mapping = kwq_16_dma->pg_map_arr[j] +
  1012. off;
  1013. if ((i % n) == (n - 1))
  1014. j++;
  1015. }
  1016. ret = cnic_alloc_kcq(dev, &cp->kcq1, false);
  1017. if (ret)
  1018. goto error;
  1019. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  1020. ret = cnic_alloc_kcq(dev, &cp->kcq2, true);
  1021. if (ret)
  1022. goto error;
  1023. }
  1024. pages = PAGE_ALIGN(BNX2X_ISCSI_GLB_BUF_SIZE) / PAGE_SIZE;
  1025. ret = cnic_alloc_dma(dev, &cp->gbl_buf_info, pages, 0);
  1026. if (ret)
  1027. goto error;
  1028. ret = cnic_alloc_bnx2x_context(dev);
  1029. if (ret)
  1030. goto error;
  1031. cp->bnx2x_def_status_blk = cp->ethdev->irq_arr[1].status_blk;
  1032. cp->l2_rx_ring_size = 15;
  1033. ret = cnic_alloc_uio_rings(dev, 4);
  1034. if (ret)
  1035. goto error;
  1036. ret = cnic_init_uio(dev);
  1037. if (ret)
  1038. goto error;
  1039. return 0;
  1040. error:
  1041. cnic_free_resc(dev);
  1042. return -ENOMEM;
  1043. }
  1044. static inline u32 cnic_kwq_avail(struct cnic_local *cp)
  1045. {
  1046. return cp->max_kwq_idx -
  1047. ((cp->kwq_prod_idx - cp->kwq_con_idx) & cp->max_kwq_idx);
  1048. }
  1049. static int cnic_submit_bnx2_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  1050. u32 num_wqes)
  1051. {
  1052. struct cnic_local *cp = dev->cnic_priv;
  1053. struct kwqe *prod_qe;
  1054. u16 prod, sw_prod, i;
  1055. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  1056. return -EAGAIN; /* bnx2 is down */
  1057. spin_lock_bh(&cp->cnic_ulp_lock);
  1058. if (num_wqes > cnic_kwq_avail(cp) &&
  1059. !test_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags)) {
  1060. spin_unlock_bh(&cp->cnic_ulp_lock);
  1061. return -EAGAIN;
  1062. }
  1063. clear_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  1064. prod = cp->kwq_prod_idx;
  1065. sw_prod = prod & MAX_KWQ_IDX;
  1066. for (i = 0; i < num_wqes; i++) {
  1067. prod_qe = &cp->kwq[KWQ_PG(sw_prod)][KWQ_IDX(sw_prod)];
  1068. memcpy(prod_qe, wqes[i], sizeof(struct kwqe));
  1069. prod++;
  1070. sw_prod = prod & MAX_KWQ_IDX;
  1071. }
  1072. cp->kwq_prod_idx = prod;
  1073. CNIC_WR16(dev, cp->kwq_io_addr, cp->kwq_prod_idx);
  1074. spin_unlock_bh(&cp->cnic_ulp_lock);
  1075. return 0;
  1076. }
  1077. static void *cnic_get_kwqe_16_data(struct cnic_local *cp, u32 l5_cid,
  1078. union l5cm_specific_data *l5_data)
  1079. {
  1080. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1081. dma_addr_t map;
  1082. map = ctx->kwqe_data_mapping;
  1083. l5_data->phy_address.lo = (u64) map & 0xffffffff;
  1084. l5_data->phy_address.hi = (u64) map >> 32;
  1085. return ctx->kwqe_data;
  1086. }
  1087. static int cnic_submit_kwqe_16(struct cnic_dev *dev, u32 cmd, u32 cid,
  1088. u32 type, union l5cm_specific_data *l5_data)
  1089. {
  1090. struct cnic_local *cp = dev->cnic_priv;
  1091. struct l5cm_spe kwqe;
  1092. struct kwqe_16 *kwq[1];
  1093. u16 type_16;
  1094. int ret;
  1095. kwqe.hdr.conn_and_cmd_data =
  1096. cpu_to_le32(((cmd << SPE_HDR_CMD_ID_SHIFT) |
  1097. BNX2X_HW_CID(cp, cid)));
  1098. type_16 = (type << SPE_HDR_CONN_TYPE_SHIFT) & SPE_HDR_CONN_TYPE;
  1099. type_16 |= (cp->pfid << SPE_HDR_FUNCTION_ID_SHIFT) &
  1100. SPE_HDR_FUNCTION_ID;
  1101. kwqe.hdr.type = cpu_to_le16(type_16);
  1102. kwqe.hdr.reserved1 = 0;
  1103. kwqe.data.phy_address.lo = cpu_to_le32(l5_data->phy_address.lo);
  1104. kwqe.data.phy_address.hi = cpu_to_le32(l5_data->phy_address.hi);
  1105. kwq[0] = (struct kwqe_16 *) &kwqe;
  1106. spin_lock_bh(&cp->cnic_ulp_lock);
  1107. ret = cp->ethdev->drv_submit_kwqes_16(dev->netdev, kwq, 1);
  1108. spin_unlock_bh(&cp->cnic_ulp_lock);
  1109. if (ret == 1)
  1110. return 0;
  1111. return ret;
  1112. }
  1113. static void cnic_reply_bnx2x_kcqes(struct cnic_dev *dev, int ulp_type,
  1114. struct kcqe *cqes[], u32 num_cqes)
  1115. {
  1116. struct cnic_local *cp = dev->cnic_priv;
  1117. struct cnic_ulp_ops *ulp_ops;
  1118. rcu_read_lock();
  1119. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  1120. if (likely(ulp_ops)) {
  1121. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  1122. cqes, num_cqes);
  1123. }
  1124. rcu_read_unlock();
  1125. }
  1126. static int cnic_bnx2x_iscsi_init1(struct cnic_dev *dev, struct kwqe *kwqe)
  1127. {
  1128. struct cnic_local *cp = dev->cnic_priv;
  1129. struct iscsi_kwqe_init1 *req1 = (struct iscsi_kwqe_init1 *) kwqe;
  1130. int hq_bds, pages;
  1131. u32 pfid = cp->pfid;
  1132. cp->num_iscsi_tasks = req1->num_tasks_per_conn;
  1133. cp->num_ccells = req1->num_ccells_per_conn;
  1134. cp->task_array_size = BNX2X_ISCSI_TASK_CONTEXT_SIZE *
  1135. cp->num_iscsi_tasks;
  1136. cp->r2tq_size = cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS *
  1137. BNX2X_ISCSI_R2TQE_SIZE;
  1138. cp->hq_size = cp->num_ccells * BNX2X_ISCSI_HQ_BD_SIZE;
  1139. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1140. hq_bds = pages * (PAGE_SIZE / BNX2X_ISCSI_HQ_BD_SIZE);
  1141. cp->num_cqs = req1->num_cqs;
  1142. if (!dev->max_iscsi_conn)
  1143. return 0;
  1144. /* init Tstorm RAM */
  1145. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1146. req1->rq_num_wqes);
  1147. CNIC_WR16(dev, BAR_TSTRORM_INTMEM + TSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1148. PAGE_SIZE);
  1149. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1150. TSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1151. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1152. TSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1153. req1->num_tasks_per_conn);
  1154. /* init Ustorm RAM */
  1155. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1156. USTORM_ISCSI_RQ_BUFFER_SIZE_OFFSET(pfid),
  1157. req1->rq_buffer_size);
  1158. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1159. PAGE_SIZE);
  1160. CNIC_WR8(dev, BAR_USTRORM_INTMEM +
  1161. USTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1162. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1163. USTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1164. req1->num_tasks_per_conn);
  1165. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_RQ_SIZE_OFFSET(pfid),
  1166. req1->rq_num_wqes);
  1167. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1168. req1->cq_num_wqes);
  1169. CNIC_WR16(dev, BAR_USTRORM_INTMEM + USTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1170. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1171. /* init Xstorm RAM */
  1172. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1173. PAGE_SIZE);
  1174. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1175. XSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1176. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1177. XSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1178. req1->num_tasks_per_conn);
  1179. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1180. hq_bds);
  1181. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_SQ_SIZE_OFFSET(pfid),
  1182. req1->num_tasks_per_conn);
  1183. CNIC_WR16(dev, BAR_XSTRORM_INTMEM + XSTORM_ISCSI_R2TQ_SIZE_OFFSET(pfid),
  1184. cp->num_iscsi_tasks * BNX2X_ISCSI_MAX_PENDING_R2TS);
  1185. /* init Cstorm RAM */
  1186. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_PAGE_SIZE_OFFSET(pfid),
  1187. PAGE_SIZE);
  1188. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  1189. CSTORM_ISCSI_PAGE_SIZE_LOG_OFFSET(pfid), PAGE_SHIFT);
  1190. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1191. CSTORM_ISCSI_NUM_OF_TASKS_OFFSET(pfid),
  1192. req1->num_tasks_per_conn);
  1193. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_CQ_SIZE_OFFSET(pfid),
  1194. req1->cq_num_wqes);
  1195. CNIC_WR16(dev, BAR_CSTRORM_INTMEM + CSTORM_ISCSI_HQ_SIZE_OFFSET(pfid),
  1196. hq_bds);
  1197. return 0;
  1198. }
  1199. static int cnic_bnx2x_iscsi_init2(struct cnic_dev *dev, struct kwqe *kwqe)
  1200. {
  1201. struct iscsi_kwqe_init2 *req2 = (struct iscsi_kwqe_init2 *) kwqe;
  1202. struct cnic_local *cp = dev->cnic_priv;
  1203. u32 pfid = cp->pfid;
  1204. struct iscsi_kcqe kcqe;
  1205. struct kcqe *cqes[1];
  1206. memset(&kcqe, 0, sizeof(kcqe));
  1207. if (!dev->max_iscsi_conn) {
  1208. kcqe.completion_status =
  1209. ISCSI_KCQE_COMPLETION_STATUS_ISCSI_NOT_SUPPORTED;
  1210. goto done;
  1211. }
  1212. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1213. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1214. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  1215. TSTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1216. req2->error_bit_map[1]);
  1217. CNIC_WR16(dev, BAR_USTRORM_INTMEM +
  1218. USTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1219. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1220. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid), req2->error_bit_map[0]);
  1221. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  1222. USTORM_ISCSI_ERROR_BITMAP_OFFSET(pfid) + 4,
  1223. req2->error_bit_map[1]);
  1224. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  1225. CSTORM_ISCSI_CQ_SQN_SIZE_OFFSET(pfid), req2->max_cq_sqn);
  1226. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1227. done:
  1228. kcqe.op_code = ISCSI_KCQE_OPCODE_INIT;
  1229. cqes[0] = (struct kcqe *) &kcqe;
  1230. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1231. return 0;
  1232. }
  1233. static void cnic_free_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1234. {
  1235. struct cnic_local *cp = dev->cnic_priv;
  1236. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1237. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI) {
  1238. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1239. cnic_free_dma(dev, &iscsi->hq_info);
  1240. cnic_free_dma(dev, &iscsi->r2tq_info);
  1241. cnic_free_dma(dev, &iscsi->task_array_info);
  1242. cnic_free_id(&cp->cid_tbl, ctx->cid);
  1243. } else {
  1244. cnic_free_id(&cp->fcoe_cid_tbl, ctx->cid);
  1245. }
  1246. ctx->cid = 0;
  1247. }
  1248. static int cnic_alloc_bnx2x_conn_resc(struct cnic_dev *dev, u32 l5_cid)
  1249. {
  1250. u32 cid;
  1251. int ret, pages;
  1252. struct cnic_local *cp = dev->cnic_priv;
  1253. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1254. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1255. if (ctx->ulp_proto_id == CNIC_ULP_FCOE) {
  1256. cid = cnic_alloc_new_id(&cp->fcoe_cid_tbl);
  1257. if (cid == -1) {
  1258. ret = -ENOMEM;
  1259. goto error;
  1260. }
  1261. ctx->cid = cid;
  1262. return 0;
  1263. }
  1264. cid = cnic_alloc_new_id(&cp->cid_tbl);
  1265. if (cid == -1) {
  1266. ret = -ENOMEM;
  1267. goto error;
  1268. }
  1269. ctx->cid = cid;
  1270. pages = PAGE_ALIGN(cp->task_array_size) / PAGE_SIZE;
  1271. ret = cnic_alloc_dma(dev, &iscsi->task_array_info, pages, 1);
  1272. if (ret)
  1273. goto error;
  1274. pages = PAGE_ALIGN(cp->r2tq_size) / PAGE_SIZE;
  1275. ret = cnic_alloc_dma(dev, &iscsi->r2tq_info, pages, 1);
  1276. if (ret)
  1277. goto error;
  1278. pages = PAGE_ALIGN(cp->hq_size) / PAGE_SIZE;
  1279. ret = cnic_alloc_dma(dev, &iscsi->hq_info, pages, 1);
  1280. if (ret)
  1281. goto error;
  1282. return 0;
  1283. error:
  1284. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1285. return ret;
  1286. }
  1287. static void *cnic_get_bnx2x_ctx(struct cnic_dev *dev, u32 cid, int init,
  1288. struct regpair *ctx_addr)
  1289. {
  1290. struct cnic_local *cp = dev->cnic_priv;
  1291. struct cnic_eth_dev *ethdev = cp->ethdev;
  1292. int blk = (cid - ethdev->starting_cid) / cp->cids_per_blk;
  1293. int off = (cid - ethdev->starting_cid) % cp->cids_per_blk;
  1294. unsigned long align_off = 0;
  1295. dma_addr_t ctx_map;
  1296. void *ctx;
  1297. if (cp->ctx_align) {
  1298. unsigned long mask = cp->ctx_align - 1;
  1299. if (cp->ctx_arr[blk].mapping & mask)
  1300. align_off = cp->ctx_align -
  1301. (cp->ctx_arr[blk].mapping & mask);
  1302. }
  1303. ctx_map = cp->ctx_arr[blk].mapping + align_off +
  1304. (off * BNX2X_CONTEXT_MEM_SIZE);
  1305. ctx = cp->ctx_arr[blk].ctx + align_off +
  1306. (off * BNX2X_CONTEXT_MEM_SIZE);
  1307. if (init)
  1308. memset(ctx, 0, BNX2X_CONTEXT_MEM_SIZE);
  1309. ctx_addr->lo = ctx_map & 0xffffffff;
  1310. ctx_addr->hi = (u64) ctx_map >> 32;
  1311. return ctx;
  1312. }
  1313. static int cnic_setup_bnx2x_ctx(struct cnic_dev *dev, struct kwqe *wqes[],
  1314. u32 num)
  1315. {
  1316. struct cnic_local *cp = dev->cnic_priv;
  1317. struct iscsi_kwqe_conn_offload1 *req1 =
  1318. (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1319. struct iscsi_kwqe_conn_offload2 *req2 =
  1320. (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1321. struct iscsi_kwqe_conn_offload3 *req3;
  1322. struct cnic_context *ctx = &cp->ctx_tbl[req1->iscsi_conn_id];
  1323. struct cnic_iscsi *iscsi = ctx->proto.iscsi;
  1324. u32 cid = ctx->cid;
  1325. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1326. struct iscsi_context *ictx;
  1327. struct regpair context_addr;
  1328. int i, j, n = 2, n_max;
  1329. u8 port = CNIC_PORT(cp);
  1330. ctx->ctx_flags = 0;
  1331. if (!req2->num_additional_wqes)
  1332. return -EINVAL;
  1333. n_max = req2->num_additional_wqes + 2;
  1334. ictx = cnic_get_bnx2x_ctx(dev, cid, 1, &context_addr);
  1335. if (ictx == NULL)
  1336. return -ENOMEM;
  1337. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1338. ictx->xstorm_ag_context.hq_prod = 1;
  1339. ictx->xstorm_st_context.iscsi.first_burst_length =
  1340. ISCSI_DEF_FIRST_BURST_LEN;
  1341. ictx->xstorm_st_context.iscsi.max_send_pdu_length =
  1342. ISCSI_DEF_MAX_RECV_SEG_LEN;
  1343. ictx->xstorm_st_context.iscsi.sq_pbl_base.lo =
  1344. req1->sq_page_table_addr_lo;
  1345. ictx->xstorm_st_context.iscsi.sq_pbl_base.hi =
  1346. req1->sq_page_table_addr_hi;
  1347. ictx->xstorm_st_context.iscsi.sq_curr_pbe.lo = req2->sq_first_pte.hi;
  1348. ictx->xstorm_st_context.iscsi.sq_curr_pbe.hi = req2->sq_first_pte.lo;
  1349. ictx->xstorm_st_context.iscsi.hq_pbl_base.lo =
  1350. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1351. ictx->xstorm_st_context.iscsi.hq_pbl_base.hi =
  1352. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1353. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.lo =
  1354. iscsi->hq_info.pgtbl[0];
  1355. ictx->xstorm_st_context.iscsi.hq_curr_pbe_base.hi =
  1356. iscsi->hq_info.pgtbl[1];
  1357. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.lo =
  1358. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1359. ictx->xstorm_st_context.iscsi.r2tq_pbl_base.hi =
  1360. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1361. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.lo =
  1362. iscsi->r2tq_info.pgtbl[0];
  1363. ictx->xstorm_st_context.iscsi.r2tq_curr_pbe_base.hi =
  1364. iscsi->r2tq_info.pgtbl[1];
  1365. ictx->xstorm_st_context.iscsi.task_pbl_base.lo =
  1366. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1367. ictx->xstorm_st_context.iscsi.task_pbl_base.hi =
  1368. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1369. ictx->xstorm_st_context.iscsi.task_pbl_cache_idx =
  1370. BNX2X_ISCSI_PBL_NOT_CACHED;
  1371. ictx->xstorm_st_context.iscsi.flags.flags |=
  1372. XSTORM_ISCSI_CONTEXT_FLAGS_B_IMMEDIATE_DATA;
  1373. ictx->xstorm_st_context.iscsi.flags.flags |=
  1374. XSTORM_ISCSI_CONTEXT_FLAGS_B_INITIAL_R2T;
  1375. ictx->xstorm_st_context.common.ethernet.reserved_vlan_type =
  1376. ETH_P_8021Q;
  1377. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  1378. cp->port_mode == CHIP_2_PORT_MODE) {
  1379. port = 0;
  1380. }
  1381. ictx->xstorm_st_context.common.flags =
  1382. 1 << XSTORM_COMMON_CONTEXT_SECTION_PHYSQ_INITIALIZED_SHIFT;
  1383. ictx->xstorm_st_context.common.flags =
  1384. port << XSTORM_COMMON_CONTEXT_SECTION_PBF_PORT_SHIFT;
  1385. ictx->tstorm_st_context.iscsi.hdr_bytes_2_fetch = ISCSI_HEADER_SIZE;
  1386. /* TSTORM requires the base address of RQ DB & not PTE */
  1387. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.lo =
  1388. req2->rq_page_table_addr_lo & PAGE_MASK;
  1389. ictx->tstorm_st_context.iscsi.rq_db_phy_addr.hi =
  1390. req2->rq_page_table_addr_hi;
  1391. ictx->tstorm_st_context.iscsi.iscsi_conn_id = req1->iscsi_conn_id;
  1392. ictx->tstorm_st_context.tcp.cwnd = 0x5A8;
  1393. ictx->tstorm_st_context.tcp.flags2 |=
  1394. TSTORM_TCP_ST_CONTEXT_SECTION_DA_EN;
  1395. ictx->tstorm_st_context.tcp.ooo_support_mode =
  1396. TCP_TSTORM_OOO_DROP_AND_PROC_ACK;
  1397. ictx->timers_context.flags |= TIMERS_BLOCK_CONTEXT_CONN_VALID_FLG;
  1398. ictx->ustorm_st_context.ring.rq.pbl_base.lo =
  1399. req2->rq_page_table_addr_lo;
  1400. ictx->ustorm_st_context.ring.rq.pbl_base.hi =
  1401. req2->rq_page_table_addr_hi;
  1402. ictx->ustorm_st_context.ring.rq.curr_pbe.lo = req3->qp_first_pte[0].hi;
  1403. ictx->ustorm_st_context.ring.rq.curr_pbe.hi = req3->qp_first_pte[0].lo;
  1404. ictx->ustorm_st_context.ring.r2tq.pbl_base.lo =
  1405. iscsi->r2tq_info.pgtbl_map & 0xffffffff;
  1406. ictx->ustorm_st_context.ring.r2tq.pbl_base.hi =
  1407. (u64) iscsi->r2tq_info.pgtbl_map >> 32;
  1408. ictx->ustorm_st_context.ring.r2tq.curr_pbe.lo =
  1409. iscsi->r2tq_info.pgtbl[0];
  1410. ictx->ustorm_st_context.ring.r2tq.curr_pbe.hi =
  1411. iscsi->r2tq_info.pgtbl[1];
  1412. ictx->ustorm_st_context.ring.cq_pbl_base.lo =
  1413. req1->cq_page_table_addr_lo;
  1414. ictx->ustorm_st_context.ring.cq_pbl_base.hi =
  1415. req1->cq_page_table_addr_hi;
  1416. ictx->ustorm_st_context.ring.cq[0].cq_sn = ISCSI_INITIAL_SN;
  1417. ictx->ustorm_st_context.ring.cq[0].curr_pbe.lo = req2->cq_first_pte.hi;
  1418. ictx->ustorm_st_context.ring.cq[0].curr_pbe.hi = req2->cq_first_pte.lo;
  1419. ictx->ustorm_st_context.task_pbe_cache_index =
  1420. BNX2X_ISCSI_PBL_NOT_CACHED;
  1421. ictx->ustorm_st_context.task_pdu_cache_index =
  1422. BNX2X_ISCSI_PDU_HEADER_NOT_CACHED;
  1423. for (i = 1, j = 1; i < cp->num_cqs; i++, j++) {
  1424. if (j == 3) {
  1425. if (n >= n_max)
  1426. break;
  1427. req3 = (struct iscsi_kwqe_conn_offload3 *) wqes[n++];
  1428. j = 0;
  1429. }
  1430. ictx->ustorm_st_context.ring.cq[i].cq_sn = ISCSI_INITIAL_SN;
  1431. ictx->ustorm_st_context.ring.cq[i].curr_pbe.lo =
  1432. req3->qp_first_pte[j].hi;
  1433. ictx->ustorm_st_context.ring.cq[i].curr_pbe.hi =
  1434. req3->qp_first_pte[j].lo;
  1435. }
  1436. ictx->ustorm_st_context.task_pbl_base.lo =
  1437. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1438. ictx->ustorm_st_context.task_pbl_base.hi =
  1439. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1440. ictx->ustorm_st_context.tce_phy_addr.lo =
  1441. iscsi->task_array_info.pgtbl[0];
  1442. ictx->ustorm_st_context.tce_phy_addr.hi =
  1443. iscsi->task_array_info.pgtbl[1];
  1444. ictx->ustorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1445. ictx->ustorm_st_context.num_cqs = cp->num_cqs;
  1446. ictx->ustorm_st_context.negotiated_rx |= ISCSI_DEF_MAX_RECV_SEG_LEN;
  1447. ictx->ustorm_st_context.negotiated_rx_and_flags |=
  1448. ISCSI_DEF_MAX_BURST_LEN;
  1449. ictx->ustorm_st_context.negotiated_rx |=
  1450. ISCSI_DEFAULT_MAX_OUTSTANDING_R2T <<
  1451. USTORM_ISCSI_ST_CONTEXT_MAX_OUTSTANDING_R2TS_SHIFT;
  1452. ictx->cstorm_st_context.hq_pbl_base.lo =
  1453. iscsi->hq_info.pgtbl_map & 0xffffffff;
  1454. ictx->cstorm_st_context.hq_pbl_base.hi =
  1455. (u64) iscsi->hq_info.pgtbl_map >> 32;
  1456. ictx->cstorm_st_context.hq_curr_pbe.lo = iscsi->hq_info.pgtbl[0];
  1457. ictx->cstorm_st_context.hq_curr_pbe.hi = iscsi->hq_info.pgtbl[1];
  1458. ictx->cstorm_st_context.task_pbl_base.lo =
  1459. iscsi->task_array_info.pgtbl_map & 0xffffffff;
  1460. ictx->cstorm_st_context.task_pbl_base.hi =
  1461. (u64) iscsi->task_array_info.pgtbl_map >> 32;
  1462. /* CSTORM and USTORM initialization is different, CSTORM requires
  1463. * CQ DB base & not PTE addr */
  1464. ictx->cstorm_st_context.cq_db_base.lo =
  1465. req1->cq_page_table_addr_lo & PAGE_MASK;
  1466. ictx->cstorm_st_context.cq_db_base.hi = req1->cq_page_table_addr_hi;
  1467. ictx->cstorm_st_context.iscsi_conn_id = req1->iscsi_conn_id;
  1468. ictx->cstorm_st_context.cq_proc_en_bit_map = (1 << cp->num_cqs) - 1;
  1469. for (i = 0; i < cp->num_cqs; i++) {
  1470. ictx->cstorm_st_context.cq_c_prod_sqn_arr.sqn[i] =
  1471. ISCSI_INITIAL_SN;
  1472. ictx->cstorm_st_context.cq_c_sqn_2_notify_arr.sqn[i] =
  1473. ISCSI_INITIAL_SN;
  1474. }
  1475. ictx->xstorm_ag_context.cdu_reserved =
  1476. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1477. ISCSI_CONNECTION_TYPE);
  1478. ictx->ustorm_ag_context.cdu_usage =
  1479. CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1480. ISCSI_CONNECTION_TYPE);
  1481. return 0;
  1482. }
  1483. static int cnic_bnx2x_iscsi_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1484. u32 num, int *work)
  1485. {
  1486. struct iscsi_kwqe_conn_offload1 *req1;
  1487. struct iscsi_kwqe_conn_offload2 *req2;
  1488. struct cnic_local *cp = dev->cnic_priv;
  1489. struct cnic_context *ctx;
  1490. struct iscsi_kcqe kcqe;
  1491. struct kcqe *cqes[1];
  1492. u32 l5_cid;
  1493. int ret = 0;
  1494. if (num < 2) {
  1495. *work = num;
  1496. return -EINVAL;
  1497. }
  1498. req1 = (struct iscsi_kwqe_conn_offload1 *) wqes[0];
  1499. req2 = (struct iscsi_kwqe_conn_offload2 *) wqes[1];
  1500. if ((num - 2) < req2->num_additional_wqes) {
  1501. *work = num;
  1502. return -EINVAL;
  1503. }
  1504. *work = 2 + req2->num_additional_wqes;
  1505. l5_cid = req1->iscsi_conn_id;
  1506. if (l5_cid >= MAX_ISCSI_TBL_SZ)
  1507. return -EINVAL;
  1508. memset(&kcqe, 0, sizeof(kcqe));
  1509. kcqe.op_code = ISCSI_KCQE_OPCODE_OFFLOAD_CONN;
  1510. kcqe.iscsi_conn_id = l5_cid;
  1511. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1512. ctx = &cp->ctx_tbl[l5_cid];
  1513. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags)) {
  1514. kcqe.completion_status =
  1515. ISCSI_KCQE_COMPLETION_STATUS_CID_BUSY;
  1516. goto done;
  1517. }
  1518. if (atomic_inc_return(&cp->iscsi_conn) > dev->max_iscsi_conn) {
  1519. atomic_dec(&cp->iscsi_conn);
  1520. goto done;
  1521. }
  1522. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1523. if (ret) {
  1524. atomic_dec(&cp->iscsi_conn);
  1525. ret = 0;
  1526. goto done;
  1527. }
  1528. ret = cnic_setup_bnx2x_ctx(dev, wqes, num);
  1529. if (ret < 0) {
  1530. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1531. atomic_dec(&cp->iscsi_conn);
  1532. goto done;
  1533. }
  1534. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1535. kcqe.iscsi_conn_context_id = BNX2X_HW_CID(cp, cp->ctx_tbl[l5_cid].cid);
  1536. done:
  1537. cqes[0] = (struct kcqe *) &kcqe;
  1538. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1539. return 0;
  1540. }
  1541. static int cnic_bnx2x_iscsi_update(struct cnic_dev *dev, struct kwqe *kwqe)
  1542. {
  1543. struct cnic_local *cp = dev->cnic_priv;
  1544. struct iscsi_kwqe_conn_update *req =
  1545. (struct iscsi_kwqe_conn_update *) kwqe;
  1546. void *data;
  1547. union l5cm_specific_data l5_data;
  1548. u32 l5_cid, cid = BNX2X_SW_CID(req->context_id);
  1549. int ret;
  1550. if (cnic_get_l5_cid(cp, cid, &l5_cid) != 0)
  1551. return -EINVAL;
  1552. data = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1553. if (!data)
  1554. return -ENOMEM;
  1555. memcpy(data, kwqe, sizeof(struct kwqe));
  1556. ret = cnic_submit_kwqe_16(dev, ISCSI_RAMROD_CMD_ID_UPDATE_CONN,
  1557. req->context_id, ISCSI_CONNECTION_TYPE, &l5_data);
  1558. return ret;
  1559. }
  1560. static int cnic_bnx2x_destroy_ramrod(struct cnic_dev *dev, u32 l5_cid)
  1561. {
  1562. struct cnic_local *cp = dev->cnic_priv;
  1563. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1564. union l5cm_specific_data l5_data;
  1565. int ret;
  1566. u32 hw_cid;
  1567. init_waitqueue_head(&ctx->waitq);
  1568. ctx->wait_cond = 0;
  1569. memset(&l5_data, 0, sizeof(l5_data));
  1570. hw_cid = BNX2X_HW_CID(cp, ctx->cid);
  1571. ret = cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  1572. hw_cid, NONE_CONNECTION_TYPE, &l5_data);
  1573. if (ret == 0) {
  1574. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  1575. if (unlikely(test_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags)))
  1576. return -EBUSY;
  1577. }
  1578. return 0;
  1579. }
  1580. static int cnic_bnx2x_iscsi_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  1581. {
  1582. struct cnic_local *cp = dev->cnic_priv;
  1583. struct iscsi_kwqe_conn_destroy *req =
  1584. (struct iscsi_kwqe_conn_destroy *) kwqe;
  1585. u32 l5_cid = req->reserved0;
  1586. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1587. int ret = 0;
  1588. struct iscsi_kcqe kcqe;
  1589. struct kcqe *cqes[1];
  1590. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1591. goto skip_cfc_delete;
  1592. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  1593. unsigned long delta = ctx->timestamp + (2 * HZ) - jiffies;
  1594. if (delta > (2 * HZ))
  1595. delta = 0;
  1596. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  1597. queue_delayed_work(cnic_wq, &cp->delete_task, delta);
  1598. goto destroy_reply;
  1599. }
  1600. ret = cnic_bnx2x_destroy_ramrod(dev, l5_cid);
  1601. skip_cfc_delete:
  1602. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1603. if (!ret) {
  1604. atomic_dec(&cp->iscsi_conn);
  1605. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1606. }
  1607. destroy_reply:
  1608. memset(&kcqe, 0, sizeof(kcqe));
  1609. kcqe.op_code = ISCSI_KCQE_OPCODE_DESTROY_CONN;
  1610. kcqe.iscsi_conn_id = l5_cid;
  1611. kcqe.completion_status = ISCSI_KCQE_COMPLETION_STATUS_SUCCESS;
  1612. kcqe.iscsi_conn_context_id = req->context_id;
  1613. cqes[0] = (struct kcqe *) &kcqe;
  1614. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_ISCSI, cqes, 1);
  1615. return 0;
  1616. }
  1617. static void cnic_init_storm_conn_bufs(struct cnic_dev *dev,
  1618. struct l4_kwq_connect_req1 *kwqe1,
  1619. struct l4_kwq_connect_req3 *kwqe3,
  1620. struct l5cm_active_conn_buffer *conn_buf)
  1621. {
  1622. struct l5cm_conn_addr_params *conn_addr = &conn_buf->conn_addr_buf;
  1623. struct l5cm_xstorm_conn_buffer *xstorm_buf =
  1624. &conn_buf->xstorm_conn_buffer;
  1625. struct l5cm_tstorm_conn_buffer *tstorm_buf =
  1626. &conn_buf->tstorm_conn_buffer;
  1627. struct regpair context_addr;
  1628. u32 cid = BNX2X_SW_CID(kwqe1->cid);
  1629. struct in6_addr src_ip, dst_ip;
  1630. int i;
  1631. u32 *addrp;
  1632. addrp = (u32 *) &conn_addr->local_ip_addr;
  1633. for (i = 0; i < 4; i++, addrp++)
  1634. src_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1635. addrp = (u32 *) &conn_addr->remote_ip_addr;
  1636. for (i = 0; i < 4; i++, addrp++)
  1637. dst_ip.in6_u.u6_addr32[i] = cpu_to_be32(*addrp);
  1638. cnic_get_bnx2x_ctx(dev, cid, 0, &context_addr);
  1639. xstorm_buf->context_addr.hi = context_addr.hi;
  1640. xstorm_buf->context_addr.lo = context_addr.lo;
  1641. xstorm_buf->mss = 0xffff;
  1642. xstorm_buf->rcv_buf = kwqe3->rcv_buf;
  1643. if (kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE)
  1644. xstorm_buf->params |= L5CM_XSTORM_CONN_BUFFER_NAGLE_ENABLE;
  1645. xstorm_buf->pseudo_header_checksum =
  1646. swab16(~csum_ipv6_magic(&src_ip, &dst_ip, 0, IPPROTO_TCP, 0));
  1647. if (!(kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK))
  1648. tstorm_buf->params |=
  1649. L5CM_TSTORM_CONN_BUFFER_DELAYED_ACK_ENABLE;
  1650. if (kwqe3->ka_timeout) {
  1651. tstorm_buf->ka_enable = 1;
  1652. tstorm_buf->ka_timeout = kwqe3->ka_timeout;
  1653. tstorm_buf->ka_interval = kwqe3->ka_interval;
  1654. tstorm_buf->ka_max_probe_count = kwqe3->ka_max_probe_count;
  1655. }
  1656. tstorm_buf->max_rt_time = 0xffffffff;
  1657. }
  1658. static void cnic_init_bnx2x_mac(struct cnic_dev *dev)
  1659. {
  1660. struct cnic_local *cp = dev->cnic_priv;
  1661. u32 pfid = cp->pfid;
  1662. u8 *mac = dev->mac_addr;
  1663. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1664. XSTORM_ISCSI_LOCAL_MAC_ADDR0_OFFSET(pfid), mac[0]);
  1665. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1666. XSTORM_ISCSI_LOCAL_MAC_ADDR1_OFFSET(pfid), mac[1]);
  1667. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1668. XSTORM_ISCSI_LOCAL_MAC_ADDR2_OFFSET(pfid), mac[2]);
  1669. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1670. XSTORM_ISCSI_LOCAL_MAC_ADDR3_OFFSET(pfid), mac[3]);
  1671. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1672. XSTORM_ISCSI_LOCAL_MAC_ADDR4_OFFSET(pfid), mac[4]);
  1673. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1674. XSTORM_ISCSI_LOCAL_MAC_ADDR5_OFFSET(pfid), mac[5]);
  1675. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1676. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[5]);
  1677. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1678. TSTORM_ISCSI_TCP_VARS_LSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1679. mac[4]);
  1680. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1681. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid), mac[3]);
  1682. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1683. TSTORM_ISCSI_TCP_VARS_MID_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1684. mac[2]);
  1685. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1686. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid), mac[1]);
  1687. CNIC_WR8(dev, BAR_TSTRORM_INTMEM +
  1688. TSTORM_ISCSI_TCP_VARS_MSB_LOCAL_MAC_ADDR_OFFSET(pfid) + 1,
  1689. mac[0]);
  1690. }
  1691. static void cnic_bnx2x_set_tcp_timestamp(struct cnic_dev *dev, int tcp_ts)
  1692. {
  1693. struct cnic_local *cp = dev->cnic_priv;
  1694. u8 xstorm_flags = XSTORM_L5CM_TCP_FLAGS_WND_SCL_EN;
  1695. u16 tstorm_flags = 0;
  1696. if (tcp_ts) {
  1697. xstorm_flags |= XSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1698. tstorm_flags |= TSTORM_L5CM_TCP_FLAGS_TS_ENABLED;
  1699. }
  1700. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  1701. XSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), xstorm_flags);
  1702. CNIC_WR16(dev, BAR_TSTRORM_INTMEM +
  1703. TSTORM_ISCSI_TCP_VARS_FLAGS_OFFSET(cp->pfid), tstorm_flags);
  1704. }
  1705. static int cnic_bnx2x_connect(struct cnic_dev *dev, struct kwqe *wqes[],
  1706. u32 num, int *work)
  1707. {
  1708. struct cnic_local *cp = dev->cnic_priv;
  1709. struct l4_kwq_connect_req1 *kwqe1 =
  1710. (struct l4_kwq_connect_req1 *) wqes[0];
  1711. struct l4_kwq_connect_req3 *kwqe3;
  1712. struct l5cm_active_conn_buffer *conn_buf;
  1713. struct l5cm_conn_addr_params *conn_addr;
  1714. union l5cm_specific_data l5_data;
  1715. u32 l5_cid = kwqe1->pg_cid;
  1716. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  1717. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  1718. int ret;
  1719. if (num < 2) {
  1720. *work = num;
  1721. return -EINVAL;
  1722. }
  1723. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6)
  1724. *work = 3;
  1725. else
  1726. *work = 2;
  1727. if (num < *work) {
  1728. *work = num;
  1729. return -EINVAL;
  1730. }
  1731. if (sizeof(*conn_buf) > CNIC_KWQ16_DATA_SIZE) {
  1732. netdev_err(dev->netdev, "conn_buf size too big\n");
  1733. return -ENOMEM;
  1734. }
  1735. conn_buf = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1736. if (!conn_buf)
  1737. return -ENOMEM;
  1738. memset(conn_buf, 0, sizeof(*conn_buf));
  1739. conn_addr = &conn_buf->conn_addr_buf;
  1740. conn_addr->remote_addr_0 = csk->ha[0];
  1741. conn_addr->remote_addr_1 = csk->ha[1];
  1742. conn_addr->remote_addr_2 = csk->ha[2];
  1743. conn_addr->remote_addr_3 = csk->ha[3];
  1744. conn_addr->remote_addr_4 = csk->ha[4];
  1745. conn_addr->remote_addr_5 = csk->ha[5];
  1746. if (kwqe1->conn_flags & L4_KWQ_CONNECT_REQ1_IP_V6) {
  1747. struct l4_kwq_connect_req2 *kwqe2 =
  1748. (struct l4_kwq_connect_req2 *) wqes[1];
  1749. conn_addr->local_ip_addr.ip_addr_hi_hi = kwqe2->src_ip_v6_4;
  1750. conn_addr->local_ip_addr.ip_addr_hi_lo = kwqe2->src_ip_v6_3;
  1751. conn_addr->local_ip_addr.ip_addr_lo_hi = kwqe2->src_ip_v6_2;
  1752. conn_addr->remote_ip_addr.ip_addr_hi_hi = kwqe2->dst_ip_v6_4;
  1753. conn_addr->remote_ip_addr.ip_addr_hi_lo = kwqe2->dst_ip_v6_3;
  1754. conn_addr->remote_ip_addr.ip_addr_lo_hi = kwqe2->dst_ip_v6_2;
  1755. conn_addr->params |= L5CM_CONN_ADDR_PARAMS_IP_VERSION;
  1756. }
  1757. kwqe3 = (struct l4_kwq_connect_req3 *) wqes[*work - 1];
  1758. conn_addr->local_ip_addr.ip_addr_lo_lo = kwqe1->src_ip;
  1759. conn_addr->remote_ip_addr.ip_addr_lo_lo = kwqe1->dst_ip;
  1760. conn_addr->local_tcp_port = kwqe1->src_port;
  1761. conn_addr->remote_tcp_port = kwqe1->dst_port;
  1762. conn_addr->pmtu = kwqe3->pmtu;
  1763. cnic_init_storm_conn_bufs(dev, kwqe1, kwqe3, conn_buf);
  1764. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  1765. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(cp->pfid), csk->vlan_id);
  1766. cnic_bnx2x_set_tcp_timestamp(dev,
  1767. kwqe1->tcp_flags & L4_KWQ_CONNECT_REQ1_TIME_STAMP);
  1768. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_TCP_CONNECT,
  1769. kwqe1->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1770. if (!ret)
  1771. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1772. return ret;
  1773. }
  1774. static int cnic_bnx2x_close(struct cnic_dev *dev, struct kwqe *kwqe)
  1775. {
  1776. struct l4_kwq_close_req *req = (struct l4_kwq_close_req *) kwqe;
  1777. union l5cm_specific_data l5_data;
  1778. int ret;
  1779. memset(&l5_data, 0, sizeof(l5_data));
  1780. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_CLOSE,
  1781. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1782. return ret;
  1783. }
  1784. static int cnic_bnx2x_reset(struct cnic_dev *dev, struct kwqe *kwqe)
  1785. {
  1786. struct l4_kwq_reset_req *req = (struct l4_kwq_reset_req *) kwqe;
  1787. union l5cm_specific_data l5_data;
  1788. int ret;
  1789. memset(&l5_data, 0, sizeof(l5_data));
  1790. ret = cnic_submit_kwqe_16(dev, L5CM_RAMROD_CMD_ID_ABORT,
  1791. req->cid, ISCSI_CONNECTION_TYPE, &l5_data);
  1792. return ret;
  1793. }
  1794. static int cnic_bnx2x_offload_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1795. {
  1796. struct l4_kwq_offload_pg *req = (struct l4_kwq_offload_pg *) kwqe;
  1797. struct l4_kcq kcqe;
  1798. struct kcqe *cqes[1];
  1799. memset(&kcqe, 0, sizeof(kcqe));
  1800. kcqe.pg_host_opaque = req->host_opaque;
  1801. kcqe.pg_cid = req->host_opaque;
  1802. kcqe.op_code = L4_KCQE_OPCODE_VALUE_OFFLOAD_PG;
  1803. cqes[0] = (struct kcqe *) &kcqe;
  1804. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1805. return 0;
  1806. }
  1807. static int cnic_bnx2x_update_pg(struct cnic_dev *dev, struct kwqe *kwqe)
  1808. {
  1809. struct l4_kwq_update_pg *req = (struct l4_kwq_update_pg *) kwqe;
  1810. struct l4_kcq kcqe;
  1811. struct kcqe *cqes[1];
  1812. memset(&kcqe, 0, sizeof(kcqe));
  1813. kcqe.pg_host_opaque = req->pg_host_opaque;
  1814. kcqe.pg_cid = req->pg_cid;
  1815. kcqe.op_code = L4_KCQE_OPCODE_VALUE_UPDATE_PG;
  1816. cqes[0] = (struct kcqe *) &kcqe;
  1817. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_L4, cqes, 1);
  1818. return 0;
  1819. }
  1820. static int cnic_bnx2x_fcoe_stat(struct cnic_dev *dev, struct kwqe *kwqe)
  1821. {
  1822. struct fcoe_kwqe_stat *req;
  1823. struct fcoe_stat_ramrod_params *fcoe_stat;
  1824. union l5cm_specific_data l5_data;
  1825. struct cnic_local *cp = dev->cnic_priv;
  1826. int ret;
  1827. u32 cid;
  1828. req = (struct fcoe_kwqe_stat *) kwqe;
  1829. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1830. fcoe_stat = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1831. if (!fcoe_stat)
  1832. return -ENOMEM;
  1833. memset(fcoe_stat, 0, sizeof(*fcoe_stat));
  1834. memcpy(&fcoe_stat->stat_kwqe, req, sizeof(*req));
  1835. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_STAT_FUNC, cid,
  1836. FCOE_CONNECTION_TYPE, &l5_data);
  1837. return ret;
  1838. }
  1839. static int cnic_bnx2x_fcoe_init1(struct cnic_dev *dev, struct kwqe *wqes[],
  1840. u32 num, int *work)
  1841. {
  1842. int ret;
  1843. struct cnic_local *cp = dev->cnic_priv;
  1844. u32 cid;
  1845. struct fcoe_init_ramrod_params *fcoe_init;
  1846. struct fcoe_kwqe_init1 *req1;
  1847. struct fcoe_kwqe_init2 *req2;
  1848. struct fcoe_kwqe_init3 *req3;
  1849. union l5cm_specific_data l5_data;
  1850. if (num < 3) {
  1851. *work = num;
  1852. return -EINVAL;
  1853. }
  1854. req1 = (struct fcoe_kwqe_init1 *) wqes[0];
  1855. req2 = (struct fcoe_kwqe_init2 *) wqes[1];
  1856. req3 = (struct fcoe_kwqe_init3 *) wqes[2];
  1857. if (req2->hdr.op_code != FCOE_KWQE_OPCODE_INIT2) {
  1858. *work = 1;
  1859. return -EINVAL;
  1860. }
  1861. if (req3->hdr.op_code != FCOE_KWQE_OPCODE_INIT3) {
  1862. *work = 2;
  1863. return -EINVAL;
  1864. }
  1865. if (sizeof(*fcoe_init) > CNIC_KWQ16_DATA_SIZE) {
  1866. netdev_err(dev->netdev, "fcoe_init size too big\n");
  1867. return -ENOMEM;
  1868. }
  1869. fcoe_init = cnic_get_kwqe_16_data(cp, BNX2X_FCOE_L5_CID_BASE, &l5_data);
  1870. if (!fcoe_init)
  1871. return -ENOMEM;
  1872. memset(fcoe_init, 0, sizeof(*fcoe_init));
  1873. memcpy(&fcoe_init->init_kwqe1, req1, sizeof(*req1));
  1874. memcpy(&fcoe_init->init_kwqe2, req2, sizeof(*req2));
  1875. memcpy(&fcoe_init->init_kwqe3, req3, sizeof(*req3));
  1876. fcoe_init->eq_pbl_base.lo = cp->kcq2.dma.pgtbl_map & 0xffffffff;
  1877. fcoe_init->eq_pbl_base.hi = (u64) cp->kcq2.dma.pgtbl_map >> 32;
  1878. fcoe_init->eq_pbl_size = cp->kcq2.dma.num_pages;
  1879. fcoe_init->sb_num = cp->status_blk_num;
  1880. fcoe_init->eq_prod = MAX_KCQ_IDX;
  1881. fcoe_init->sb_id = HC_INDEX_FCOE_EQ_CONS;
  1882. cp->kcq2.sw_prod_idx = 0;
  1883. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  1884. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_INIT_FUNC, cid,
  1885. FCOE_CONNECTION_TYPE, &l5_data);
  1886. *work = 3;
  1887. return ret;
  1888. }
  1889. static int cnic_bnx2x_fcoe_ofld1(struct cnic_dev *dev, struct kwqe *wqes[],
  1890. u32 num, int *work)
  1891. {
  1892. int ret = 0;
  1893. u32 cid = -1, l5_cid;
  1894. struct cnic_local *cp = dev->cnic_priv;
  1895. struct fcoe_kwqe_conn_offload1 *req1;
  1896. struct fcoe_kwqe_conn_offload2 *req2;
  1897. struct fcoe_kwqe_conn_offload3 *req3;
  1898. struct fcoe_kwqe_conn_offload4 *req4;
  1899. struct fcoe_conn_offload_ramrod_params *fcoe_offload;
  1900. struct cnic_context *ctx;
  1901. struct fcoe_context *fctx;
  1902. struct regpair ctx_addr;
  1903. union l5cm_specific_data l5_data;
  1904. struct fcoe_kcqe kcqe;
  1905. struct kcqe *cqes[1];
  1906. if (num < 4) {
  1907. *work = num;
  1908. return -EINVAL;
  1909. }
  1910. req1 = (struct fcoe_kwqe_conn_offload1 *) wqes[0];
  1911. req2 = (struct fcoe_kwqe_conn_offload2 *) wqes[1];
  1912. req3 = (struct fcoe_kwqe_conn_offload3 *) wqes[2];
  1913. req4 = (struct fcoe_kwqe_conn_offload4 *) wqes[3];
  1914. *work = 4;
  1915. l5_cid = req1->fcoe_conn_id;
  1916. if (l5_cid >= dev->max_fcoe_conn)
  1917. goto err_reply;
  1918. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  1919. ctx = &cp->ctx_tbl[l5_cid];
  1920. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  1921. goto err_reply;
  1922. ret = cnic_alloc_bnx2x_conn_resc(dev, l5_cid);
  1923. if (ret) {
  1924. ret = 0;
  1925. goto err_reply;
  1926. }
  1927. cid = ctx->cid;
  1928. fctx = cnic_get_bnx2x_ctx(dev, cid, 1, &ctx_addr);
  1929. if (fctx) {
  1930. u32 hw_cid = BNX2X_HW_CID(cp, cid);
  1931. u32 val;
  1932. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_XCM_AG,
  1933. FCOE_CONNECTION_TYPE);
  1934. fctx->xstorm_ag_context.cdu_reserved = val;
  1935. val = CDU_RSRVD_VALUE_TYPE_A(hw_cid, CDU_REGION_NUMBER_UCM_AG,
  1936. FCOE_CONNECTION_TYPE);
  1937. fctx->ustorm_ag_context.cdu_usage = val;
  1938. }
  1939. if (sizeof(*fcoe_offload) > CNIC_KWQ16_DATA_SIZE) {
  1940. netdev_err(dev->netdev, "fcoe_offload size too big\n");
  1941. goto err_reply;
  1942. }
  1943. fcoe_offload = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1944. if (!fcoe_offload)
  1945. goto err_reply;
  1946. memset(fcoe_offload, 0, sizeof(*fcoe_offload));
  1947. memcpy(&fcoe_offload->offload_kwqe1, req1, sizeof(*req1));
  1948. memcpy(&fcoe_offload->offload_kwqe2, req2, sizeof(*req2));
  1949. memcpy(&fcoe_offload->offload_kwqe3, req3, sizeof(*req3));
  1950. memcpy(&fcoe_offload->offload_kwqe4, req4, sizeof(*req4));
  1951. cid = BNX2X_HW_CID(cp, cid);
  1952. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_OFFLOAD_CONN, cid,
  1953. FCOE_CONNECTION_TYPE, &l5_data);
  1954. if (!ret)
  1955. set_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  1956. return ret;
  1957. err_reply:
  1958. if (cid != -1)
  1959. cnic_free_bnx2x_conn_resc(dev, l5_cid);
  1960. memset(&kcqe, 0, sizeof(kcqe));
  1961. kcqe.op_code = FCOE_KCQE_OPCODE_OFFLOAD_CONN;
  1962. kcqe.fcoe_conn_id = req1->fcoe_conn_id;
  1963. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAILURE;
  1964. cqes[0] = (struct kcqe *) &kcqe;
  1965. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  1966. return ret;
  1967. }
  1968. static int cnic_bnx2x_fcoe_enable(struct cnic_dev *dev, struct kwqe *kwqe)
  1969. {
  1970. struct fcoe_kwqe_conn_enable_disable *req;
  1971. struct fcoe_conn_enable_disable_ramrod_params *fcoe_enable;
  1972. union l5cm_specific_data l5_data;
  1973. int ret;
  1974. u32 cid, l5_cid;
  1975. struct cnic_local *cp = dev->cnic_priv;
  1976. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  1977. cid = req->context_id;
  1978. l5_cid = req->conn_id + BNX2X_FCOE_L5_CID_BASE;
  1979. if (sizeof(*fcoe_enable) > CNIC_KWQ16_DATA_SIZE) {
  1980. netdev_err(dev->netdev, "fcoe_enable size too big\n");
  1981. return -ENOMEM;
  1982. }
  1983. fcoe_enable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  1984. if (!fcoe_enable)
  1985. return -ENOMEM;
  1986. memset(fcoe_enable, 0, sizeof(*fcoe_enable));
  1987. memcpy(&fcoe_enable->enable_disable_kwqe, req, sizeof(*req));
  1988. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_ENABLE_CONN, cid,
  1989. FCOE_CONNECTION_TYPE, &l5_data);
  1990. return ret;
  1991. }
  1992. static int cnic_bnx2x_fcoe_disable(struct cnic_dev *dev, struct kwqe *kwqe)
  1993. {
  1994. struct fcoe_kwqe_conn_enable_disable *req;
  1995. struct fcoe_conn_enable_disable_ramrod_params *fcoe_disable;
  1996. union l5cm_specific_data l5_data;
  1997. int ret;
  1998. u32 cid, l5_cid;
  1999. struct cnic_local *cp = dev->cnic_priv;
  2000. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2001. cid = req->context_id;
  2002. l5_cid = req->conn_id;
  2003. if (l5_cid >= dev->max_fcoe_conn)
  2004. return -EINVAL;
  2005. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2006. if (sizeof(*fcoe_disable) > CNIC_KWQ16_DATA_SIZE) {
  2007. netdev_err(dev->netdev, "fcoe_disable size too big\n");
  2008. return -ENOMEM;
  2009. }
  2010. fcoe_disable = cnic_get_kwqe_16_data(cp, l5_cid, &l5_data);
  2011. if (!fcoe_disable)
  2012. return -ENOMEM;
  2013. memset(fcoe_disable, 0, sizeof(*fcoe_disable));
  2014. memcpy(&fcoe_disable->enable_disable_kwqe, req, sizeof(*req));
  2015. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DISABLE_CONN, cid,
  2016. FCOE_CONNECTION_TYPE, &l5_data);
  2017. return ret;
  2018. }
  2019. static int cnic_bnx2x_fcoe_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2020. {
  2021. struct fcoe_kwqe_conn_destroy *req;
  2022. union l5cm_specific_data l5_data;
  2023. int ret;
  2024. u32 cid, l5_cid;
  2025. struct cnic_local *cp = dev->cnic_priv;
  2026. struct cnic_context *ctx;
  2027. struct fcoe_kcqe kcqe;
  2028. struct kcqe *cqes[1];
  2029. req = (struct fcoe_kwqe_conn_destroy *) kwqe;
  2030. cid = req->context_id;
  2031. l5_cid = req->conn_id;
  2032. if (l5_cid >= dev->max_fcoe_conn)
  2033. return -EINVAL;
  2034. l5_cid += BNX2X_FCOE_L5_CID_BASE;
  2035. ctx = &cp->ctx_tbl[l5_cid];
  2036. init_waitqueue_head(&ctx->waitq);
  2037. ctx->wait_cond = 0;
  2038. memset(&kcqe, 0, sizeof(kcqe));
  2039. kcqe.completion_status = FCOE_KCQE_COMPLETION_STATUS_ERROR;
  2040. memset(&l5_data, 0, sizeof(l5_data));
  2041. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_TERMINATE_CONN, cid,
  2042. FCOE_CONNECTION_TYPE, &l5_data);
  2043. if (ret == 0) {
  2044. wait_event_timeout(ctx->waitq, ctx->wait_cond, CNIC_RAMROD_TMO);
  2045. if (ctx->wait_cond)
  2046. kcqe.completion_status = 0;
  2047. }
  2048. set_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags);
  2049. queue_delayed_work(cnic_wq, &cp->delete_task, msecs_to_jiffies(2000));
  2050. kcqe.op_code = FCOE_KCQE_OPCODE_DESTROY_CONN;
  2051. kcqe.fcoe_conn_id = req->conn_id;
  2052. kcqe.fcoe_conn_context_id = cid;
  2053. cqes[0] = (struct kcqe *) &kcqe;
  2054. cnic_reply_bnx2x_kcqes(dev, CNIC_ULP_FCOE, cqes, 1);
  2055. return ret;
  2056. }
  2057. static void cnic_bnx2x_delete_wait(struct cnic_dev *dev, u32 start_cid)
  2058. {
  2059. struct cnic_local *cp = dev->cnic_priv;
  2060. u32 i;
  2061. for (i = start_cid; i < cp->max_cid_space; i++) {
  2062. struct cnic_context *ctx = &cp->ctx_tbl[i];
  2063. int j;
  2064. while (test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  2065. msleep(10);
  2066. for (j = 0; j < 5; j++) {
  2067. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2068. break;
  2069. msleep(20);
  2070. }
  2071. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2072. netdev_warn(dev->netdev, "CID %x not deleted\n",
  2073. ctx->cid);
  2074. }
  2075. }
  2076. static int cnic_bnx2x_fcoe_fw_destroy(struct cnic_dev *dev, struct kwqe *kwqe)
  2077. {
  2078. struct fcoe_kwqe_destroy *req;
  2079. union l5cm_specific_data l5_data;
  2080. struct cnic_local *cp = dev->cnic_priv;
  2081. int ret;
  2082. u32 cid;
  2083. cnic_bnx2x_delete_wait(dev, MAX_ISCSI_TBL_SZ);
  2084. req = (struct fcoe_kwqe_destroy *) kwqe;
  2085. cid = BNX2X_HW_CID(cp, cp->fcoe_init_cid);
  2086. memset(&l5_data, 0, sizeof(l5_data));
  2087. ret = cnic_submit_kwqe_16(dev, FCOE_RAMROD_CMD_ID_DESTROY_FUNC, cid,
  2088. FCOE_CONNECTION_TYPE, &l5_data);
  2089. return ret;
  2090. }
  2091. static void cnic_bnx2x_kwqe_err(struct cnic_dev *dev, struct kwqe *kwqe)
  2092. {
  2093. struct cnic_local *cp = dev->cnic_priv;
  2094. struct kcqe kcqe;
  2095. struct kcqe *cqes[1];
  2096. u32 cid;
  2097. u32 opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2098. u32 layer_code = kwqe->kwqe_op_flag & KWQE_LAYER_MASK;
  2099. u32 kcqe_op;
  2100. int ulp_type;
  2101. cid = kwqe->kwqe_info0;
  2102. memset(&kcqe, 0, sizeof(kcqe));
  2103. if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_FCOE) {
  2104. u32 l5_cid = 0;
  2105. ulp_type = CNIC_ULP_FCOE;
  2106. if (opcode == FCOE_KWQE_OPCODE_DISABLE_CONN) {
  2107. struct fcoe_kwqe_conn_enable_disable *req;
  2108. req = (struct fcoe_kwqe_conn_enable_disable *) kwqe;
  2109. kcqe_op = FCOE_KCQE_OPCODE_DISABLE_CONN;
  2110. cid = req->context_id;
  2111. l5_cid = req->conn_id;
  2112. } else if (opcode == FCOE_KWQE_OPCODE_DESTROY) {
  2113. kcqe_op = FCOE_KCQE_OPCODE_DESTROY_FUNC;
  2114. } else {
  2115. return;
  2116. }
  2117. kcqe.kcqe_op_flag = kcqe_op << KCQE_FLAGS_OPCODE_SHIFT;
  2118. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_FCOE;
  2119. kcqe.kcqe_info1 = FCOE_KCQE_COMPLETION_STATUS_NIC_ERROR;
  2120. kcqe.kcqe_info2 = cid;
  2121. kcqe.kcqe_info0 = l5_cid;
  2122. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L5_ISCSI) {
  2123. ulp_type = CNIC_ULP_ISCSI;
  2124. if (opcode == ISCSI_KWQE_OPCODE_UPDATE_CONN)
  2125. cid = kwqe->kwqe_info1;
  2126. kcqe.kcqe_op_flag = (opcode + 0x10) << KCQE_FLAGS_OPCODE_SHIFT;
  2127. kcqe.kcqe_op_flag |= KCQE_FLAGS_LAYER_MASK_L5_ISCSI;
  2128. kcqe.kcqe_info1 = ISCSI_KCQE_COMPLETION_STATUS_NIC_ERROR;
  2129. kcqe.kcqe_info2 = cid;
  2130. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &kcqe.kcqe_info0);
  2131. } else if (layer_code == KWQE_FLAGS_LAYER_MASK_L4) {
  2132. struct l4_kcq *l4kcqe = (struct l4_kcq *) &kcqe;
  2133. ulp_type = CNIC_ULP_L4;
  2134. if (opcode == L4_KWQE_OPCODE_VALUE_CONNECT1)
  2135. kcqe_op = L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE;
  2136. else if (opcode == L4_KWQE_OPCODE_VALUE_RESET)
  2137. kcqe_op = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  2138. else if (opcode == L4_KWQE_OPCODE_VALUE_CLOSE)
  2139. kcqe_op = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  2140. else
  2141. return;
  2142. kcqe.kcqe_op_flag = (kcqe_op << KCQE_FLAGS_OPCODE_SHIFT) |
  2143. KCQE_FLAGS_LAYER_MASK_L4;
  2144. l4kcqe->status = L4_KCQE_COMPLETION_STATUS_NIC_ERROR;
  2145. l4kcqe->cid = cid;
  2146. cnic_get_l5_cid(cp, BNX2X_SW_CID(cid), &l4kcqe->conn_id);
  2147. } else {
  2148. return;
  2149. }
  2150. cqes[0] = (struct kcqe *) &kcqe;
  2151. cnic_reply_bnx2x_kcqes(dev, ulp_type, cqes, 1);
  2152. }
  2153. static int cnic_submit_bnx2x_iscsi_kwqes(struct cnic_dev *dev,
  2154. struct kwqe *wqes[], u32 num_wqes)
  2155. {
  2156. int i, work, ret;
  2157. u32 opcode;
  2158. struct kwqe *kwqe;
  2159. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2160. return -EAGAIN; /* bnx2 is down */
  2161. for (i = 0; i < num_wqes; ) {
  2162. kwqe = wqes[i];
  2163. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2164. work = 1;
  2165. switch (opcode) {
  2166. case ISCSI_KWQE_OPCODE_INIT1:
  2167. ret = cnic_bnx2x_iscsi_init1(dev, kwqe);
  2168. break;
  2169. case ISCSI_KWQE_OPCODE_INIT2:
  2170. ret = cnic_bnx2x_iscsi_init2(dev, kwqe);
  2171. break;
  2172. case ISCSI_KWQE_OPCODE_OFFLOAD_CONN1:
  2173. ret = cnic_bnx2x_iscsi_ofld1(dev, &wqes[i],
  2174. num_wqes - i, &work);
  2175. break;
  2176. case ISCSI_KWQE_OPCODE_UPDATE_CONN:
  2177. ret = cnic_bnx2x_iscsi_update(dev, kwqe);
  2178. break;
  2179. case ISCSI_KWQE_OPCODE_DESTROY_CONN:
  2180. ret = cnic_bnx2x_iscsi_destroy(dev, kwqe);
  2181. break;
  2182. case L4_KWQE_OPCODE_VALUE_CONNECT1:
  2183. ret = cnic_bnx2x_connect(dev, &wqes[i], num_wqes - i,
  2184. &work);
  2185. break;
  2186. case L4_KWQE_OPCODE_VALUE_CLOSE:
  2187. ret = cnic_bnx2x_close(dev, kwqe);
  2188. break;
  2189. case L4_KWQE_OPCODE_VALUE_RESET:
  2190. ret = cnic_bnx2x_reset(dev, kwqe);
  2191. break;
  2192. case L4_KWQE_OPCODE_VALUE_OFFLOAD_PG:
  2193. ret = cnic_bnx2x_offload_pg(dev, kwqe);
  2194. break;
  2195. case L4_KWQE_OPCODE_VALUE_UPDATE_PG:
  2196. ret = cnic_bnx2x_update_pg(dev, kwqe);
  2197. break;
  2198. case L4_KWQE_OPCODE_VALUE_UPLOAD_PG:
  2199. ret = 0;
  2200. break;
  2201. default:
  2202. ret = 0;
  2203. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2204. opcode);
  2205. break;
  2206. }
  2207. if (ret < 0) {
  2208. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2209. opcode);
  2210. /* Possibly bnx2x parity error, send completion
  2211. * to ulp drivers with error code to speed up
  2212. * cleanup and reset recovery.
  2213. */
  2214. if (ret == -EIO || ret == -EAGAIN)
  2215. cnic_bnx2x_kwqe_err(dev, kwqe);
  2216. }
  2217. i += work;
  2218. }
  2219. return 0;
  2220. }
  2221. static int cnic_submit_bnx2x_fcoe_kwqes(struct cnic_dev *dev,
  2222. struct kwqe *wqes[], u32 num_wqes)
  2223. {
  2224. struct cnic_local *cp = dev->cnic_priv;
  2225. int i, work, ret;
  2226. u32 opcode;
  2227. struct kwqe *kwqe;
  2228. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2229. return -EAGAIN; /* bnx2 is down */
  2230. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  2231. return -EINVAL;
  2232. for (i = 0; i < num_wqes; ) {
  2233. kwqe = wqes[i];
  2234. opcode = KWQE_OPCODE(kwqe->kwqe_op_flag);
  2235. work = 1;
  2236. switch (opcode) {
  2237. case FCOE_KWQE_OPCODE_INIT1:
  2238. ret = cnic_bnx2x_fcoe_init1(dev, &wqes[i],
  2239. num_wqes - i, &work);
  2240. break;
  2241. case FCOE_KWQE_OPCODE_OFFLOAD_CONN1:
  2242. ret = cnic_bnx2x_fcoe_ofld1(dev, &wqes[i],
  2243. num_wqes - i, &work);
  2244. break;
  2245. case FCOE_KWQE_OPCODE_ENABLE_CONN:
  2246. ret = cnic_bnx2x_fcoe_enable(dev, kwqe);
  2247. break;
  2248. case FCOE_KWQE_OPCODE_DISABLE_CONN:
  2249. ret = cnic_bnx2x_fcoe_disable(dev, kwqe);
  2250. break;
  2251. case FCOE_KWQE_OPCODE_DESTROY_CONN:
  2252. ret = cnic_bnx2x_fcoe_destroy(dev, kwqe);
  2253. break;
  2254. case FCOE_KWQE_OPCODE_DESTROY:
  2255. ret = cnic_bnx2x_fcoe_fw_destroy(dev, kwqe);
  2256. break;
  2257. case FCOE_KWQE_OPCODE_STAT:
  2258. ret = cnic_bnx2x_fcoe_stat(dev, kwqe);
  2259. break;
  2260. default:
  2261. ret = 0;
  2262. netdev_err(dev->netdev, "Unknown type of KWQE(0x%x)\n",
  2263. opcode);
  2264. break;
  2265. }
  2266. if (ret < 0) {
  2267. netdev_err(dev->netdev, "KWQE(0x%x) failed\n",
  2268. opcode);
  2269. /* Possibly bnx2x parity error, send completion
  2270. * to ulp drivers with error code to speed up
  2271. * cleanup and reset recovery.
  2272. */
  2273. if (ret == -EIO || ret == -EAGAIN)
  2274. cnic_bnx2x_kwqe_err(dev, kwqe);
  2275. }
  2276. i += work;
  2277. }
  2278. return 0;
  2279. }
  2280. static int cnic_submit_bnx2x_kwqes(struct cnic_dev *dev, struct kwqe *wqes[],
  2281. u32 num_wqes)
  2282. {
  2283. int ret = -EINVAL;
  2284. u32 layer_code;
  2285. if (!test_bit(CNIC_F_CNIC_UP, &dev->flags))
  2286. return -EAGAIN; /* bnx2x is down */
  2287. if (!num_wqes)
  2288. return 0;
  2289. layer_code = wqes[0]->kwqe_op_flag & KWQE_LAYER_MASK;
  2290. switch (layer_code) {
  2291. case KWQE_FLAGS_LAYER_MASK_L5_ISCSI:
  2292. case KWQE_FLAGS_LAYER_MASK_L4:
  2293. case KWQE_FLAGS_LAYER_MASK_L2:
  2294. ret = cnic_submit_bnx2x_iscsi_kwqes(dev, wqes, num_wqes);
  2295. break;
  2296. case KWQE_FLAGS_LAYER_MASK_L5_FCOE:
  2297. ret = cnic_submit_bnx2x_fcoe_kwqes(dev, wqes, num_wqes);
  2298. break;
  2299. }
  2300. return ret;
  2301. }
  2302. static inline u32 cnic_get_kcqe_layer_mask(u32 opflag)
  2303. {
  2304. if (unlikely(KCQE_OPCODE(opflag) == FCOE_RAMROD_CMD_ID_TERMINATE_CONN))
  2305. return KCQE_FLAGS_LAYER_MASK_L4;
  2306. return opflag & KCQE_FLAGS_LAYER_MASK;
  2307. }
  2308. static void service_kcqes(struct cnic_dev *dev, int num_cqes)
  2309. {
  2310. struct cnic_local *cp = dev->cnic_priv;
  2311. int i, j, comp = 0;
  2312. i = 0;
  2313. j = 1;
  2314. while (num_cqes) {
  2315. struct cnic_ulp_ops *ulp_ops;
  2316. int ulp_type;
  2317. u32 kcqe_op_flag = cp->completed_kcq[i]->kcqe_op_flag;
  2318. u32 kcqe_layer = cnic_get_kcqe_layer_mask(kcqe_op_flag);
  2319. if (unlikely(kcqe_op_flag & KCQE_RAMROD_COMPLETION))
  2320. comp++;
  2321. while (j < num_cqes) {
  2322. u32 next_op = cp->completed_kcq[i + j]->kcqe_op_flag;
  2323. if (cnic_get_kcqe_layer_mask(next_op) != kcqe_layer)
  2324. break;
  2325. if (unlikely(next_op & KCQE_RAMROD_COMPLETION))
  2326. comp++;
  2327. j++;
  2328. }
  2329. if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_RDMA)
  2330. ulp_type = CNIC_ULP_RDMA;
  2331. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_ISCSI)
  2332. ulp_type = CNIC_ULP_ISCSI;
  2333. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L5_FCOE)
  2334. ulp_type = CNIC_ULP_FCOE;
  2335. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L4)
  2336. ulp_type = CNIC_ULP_L4;
  2337. else if (kcqe_layer == KCQE_FLAGS_LAYER_MASK_L2)
  2338. goto end;
  2339. else {
  2340. netdev_err(dev->netdev, "Unknown type of KCQE(0x%x)\n",
  2341. kcqe_op_flag);
  2342. goto end;
  2343. }
  2344. rcu_read_lock();
  2345. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  2346. if (likely(ulp_ops)) {
  2347. ulp_ops->indicate_kcqes(cp->ulp_handle[ulp_type],
  2348. cp->completed_kcq + i, j);
  2349. }
  2350. rcu_read_unlock();
  2351. end:
  2352. num_cqes -= j;
  2353. i += j;
  2354. j = 1;
  2355. }
  2356. if (unlikely(comp))
  2357. cnic_spq_completion(dev, DRV_CTL_RET_L5_SPQ_CREDIT_CMD, comp);
  2358. }
  2359. static int cnic_get_kcqes(struct cnic_dev *dev, struct kcq_info *info)
  2360. {
  2361. struct cnic_local *cp = dev->cnic_priv;
  2362. u16 i, ri, hw_prod, last;
  2363. struct kcqe *kcqe;
  2364. int kcqe_cnt = 0, last_cnt = 0;
  2365. i = ri = last = info->sw_prod_idx;
  2366. ri &= MAX_KCQ_IDX;
  2367. hw_prod = *info->hw_prod_idx_ptr;
  2368. hw_prod = info->hw_idx(hw_prod);
  2369. while ((i != hw_prod) && (kcqe_cnt < MAX_COMPLETED_KCQE)) {
  2370. kcqe = &info->kcq[KCQ_PG(ri)][KCQ_IDX(ri)];
  2371. cp->completed_kcq[kcqe_cnt++] = kcqe;
  2372. i = info->next_idx(i);
  2373. ri = i & MAX_KCQ_IDX;
  2374. if (likely(!(kcqe->kcqe_op_flag & KCQE_FLAGS_NEXT))) {
  2375. last_cnt = kcqe_cnt;
  2376. last = i;
  2377. }
  2378. }
  2379. info->sw_prod_idx = last;
  2380. return last_cnt;
  2381. }
  2382. static int cnic_l2_completion(struct cnic_local *cp)
  2383. {
  2384. u16 hw_cons, sw_cons;
  2385. struct cnic_uio_dev *udev = cp->udev;
  2386. union eth_rx_cqe *cqe, *cqe_ring = (union eth_rx_cqe *)
  2387. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  2388. u32 cmd;
  2389. int comp = 0;
  2390. if (!test_bit(CNIC_F_BNX2X_CLASS, &cp->dev->flags))
  2391. return 0;
  2392. hw_cons = *cp->rx_cons_ptr;
  2393. if ((hw_cons & BNX2X_MAX_RCQ_DESC_CNT) == BNX2X_MAX_RCQ_DESC_CNT)
  2394. hw_cons++;
  2395. sw_cons = cp->rx_cons;
  2396. while (sw_cons != hw_cons) {
  2397. u8 cqe_fp_flags;
  2398. cqe = &cqe_ring[sw_cons & BNX2X_MAX_RCQ_DESC_CNT];
  2399. cqe_fp_flags = cqe->fast_path_cqe.type_error_flags;
  2400. if (cqe_fp_flags & ETH_FAST_PATH_RX_CQE_TYPE) {
  2401. cmd = le32_to_cpu(cqe->ramrod_cqe.conn_and_cmd_data);
  2402. cmd >>= COMMON_RAMROD_ETH_RX_CQE_CMD_ID_SHIFT;
  2403. if (cmd == RAMROD_CMD_ID_ETH_CLIENT_SETUP ||
  2404. cmd == RAMROD_CMD_ID_ETH_HALT)
  2405. comp++;
  2406. }
  2407. sw_cons = BNX2X_NEXT_RCQE(sw_cons);
  2408. }
  2409. return comp;
  2410. }
  2411. static void cnic_chk_pkt_rings(struct cnic_local *cp)
  2412. {
  2413. u16 rx_cons, tx_cons;
  2414. int comp = 0;
  2415. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  2416. return;
  2417. rx_cons = *cp->rx_cons_ptr;
  2418. tx_cons = *cp->tx_cons_ptr;
  2419. if (cp->tx_cons != tx_cons || cp->rx_cons != rx_cons) {
  2420. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  2421. comp = cnic_l2_completion(cp);
  2422. cp->tx_cons = tx_cons;
  2423. cp->rx_cons = rx_cons;
  2424. if (cp->udev)
  2425. uio_event_notify(&cp->udev->cnic_uinfo);
  2426. }
  2427. if (comp)
  2428. clear_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  2429. }
  2430. static u32 cnic_service_bnx2_queues(struct cnic_dev *dev)
  2431. {
  2432. struct cnic_local *cp = dev->cnic_priv;
  2433. u32 status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2434. int kcqe_cnt;
  2435. /* status block index must be read before reading other fields */
  2436. rmb();
  2437. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2438. while ((kcqe_cnt = cnic_get_kcqes(dev, &cp->kcq1))) {
  2439. service_kcqes(dev, kcqe_cnt);
  2440. /* Tell compiler that status_blk fields can change. */
  2441. barrier();
  2442. status_idx = (u16) *cp->kcq1.status_idx_ptr;
  2443. /* status block index must be read first */
  2444. rmb();
  2445. cp->kwq_con_idx = *cp->kwq_con_idx_ptr;
  2446. }
  2447. CNIC_WR16(dev, cp->kcq1.io_addr, cp->kcq1.sw_prod_idx);
  2448. cnic_chk_pkt_rings(cp);
  2449. return status_idx;
  2450. }
  2451. static int cnic_service_bnx2(void *data, void *status_blk)
  2452. {
  2453. struct cnic_dev *dev = data;
  2454. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2455. struct status_block *sblk = status_blk;
  2456. return sblk->status_idx;
  2457. }
  2458. return cnic_service_bnx2_queues(dev);
  2459. }
  2460. static void cnic_service_bnx2_msix(unsigned long data)
  2461. {
  2462. struct cnic_dev *dev = (struct cnic_dev *) data;
  2463. struct cnic_local *cp = dev->cnic_priv;
  2464. cp->last_status_idx = cnic_service_bnx2_queues(dev);
  2465. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  2466. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  2467. }
  2468. static void cnic_doirq(struct cnic_dev *dev)
  2469. {
  2470. struct cnic_local *cp = dev->cnic_priv;
  2471. if (likely(test_bit(CNIC_F_CNIC_UP, &dev->flags))) {
  2472. u16 prod = cp->kcq1.sw_prod_idx & MAX_KCQ_IDX;
  2473. prefetch(cp->status_blk.gen);
  2474. prefetch(&cp->kcq1.kcq[KCQ_PG(prod)][KCQ_IDX(prod)]);
  2475. tasklet_schedule(&cp->cnic_irq_task);
  2476. }
  2477. }
  2478. static irqreturn_t cnic_irq(int irq, void *dev_instance)
  2479. {
  2480. struct cnic_dev *dev = dev_instance;
  2481. struct cnic_local *cp = dev->cnic_priv;
  2482. if (cp->ack_int)
  2483. cp->ack_int(dev);
  2484. cnic_doirq(dev);
  2485. return IRQ_HANDLED;
  2486. }
  2487. static inline void cnic_ack_bnx2x_int(struct cnic_dev *dev, u8 id, u8 storm,
  2488. u16 index, u8 op, u8 update)
  2489. {
  2490. struct cnic_local *cp = dev->cnic_priv;
  2491. u32 hc_addr = (HC_REG_COMMAND_REG + CNIC_PORT(cp) * 32 +
  2492. COMMAND_REG_INT_ACK);
  2493. struct igu_ack_register igu_ack;
  2494. igu_ack.status_block_index = index;
  2495. igu_ack.sb_id_and_flags =
  2496. ((id << IGU_ACK_REGISTER_STATUS_BLOCK_ID_SHIFT) |
  2497. (storm << IGU_ACK_REGISTER_STORM_ID_SHIFT) |
  2498. (update << IGU_ACK_REGISTER_UPDATE_INDEX_SHIFT) |
  2499. (op << IGU_ACK_REGISTER_INTERRUPT_MODE_SHIFT));
  2500. CNIC_WR(dev, hc_addr, (*(u32 *)&igu_ack));
  2501. }
  2502. static void cnic_ack_igu_sb(struct cnic_dev *dev, u8 igu_sb_id, u8 segment,
  2503. u16 index, u8 op, u8 update)
  2504. {
  2505. struct igu_regular cmd_data;
  2506. u32 igu_addr = BAR_IGU_INTMEM + (IGU_CMD_INT_ACK_BASE + igu_sb_id) * 8;
  2507. cmd_data.sb_id_and_flags =
  2508. (index << IGU_REGULAR_SB_INDEX_SHIFT) |
  2509. (segment << IGU_REGULAR_SEGMENT_ACCESS_SHIFT) |
  2510. (update << IGU_REGULAR_BUPDATE_SHIFT) |
  2511. (op << IGU_REGULAR_ENABLE_INT_SHIFT);
  2512. CNIC_WR(dev, igu_addr, cmd_data.sb_id_and_flags);
  2513. }
  2514. static void cnic_ack_bnx2x_msix(struct cnic_dev *dev)
  2515. {
  2516. struct cnic_local *cp = dev->cnic_priv;
  2517. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, CSTORM_ID, 0,
  2518. IGU_INT_DISABLE, 0);
  2519. }
  2520. static void cnic_ack_bnx2x_e2_msix(struct cnic_dev *dev)
  2521. {
  2522. struct cnic_local *cp = dev->cnic_priv;
  2523. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF, 0,
  2524. IGU_INT_DISABLE, 0);
  2525. }
  2526. static u32 cnic_service_bnx2x_kcq(struct cnic_dev *dev, struct kcq_info *info)
  2527. {
  2528. u32 last_status = *info->status_idx_ptr;
  2529. int kcqe_cnt;
  2530. /* status block index must be read before reading the KCQ */
  2531. rmb();
  2532. while ((kcqe_cnt = cnic_get_kcqes(dev, info))) {
  2533. service_kcqes(dev, kcqe_cnt);
  2534. /* Tell compiler that sblk fields can change. */
  2535. barrier();
  2536. last_status = *info->status_idx_ptr;
  2537. /* status block index must be read before reading the KCQ */
  2538. rmb();
  2539. }
  2540. return last_status;
  2541. }
  2542. static void cnic_service_bnx2x_bh(unsigned long data)
  2543. {
  2544. struct cnic_dev *dev = (struct cnic_dev *) data;
  2545. struct cnic_local *cp = dev->cnic_priv;
  2546. u32 status_idx, new_status_idx;
  2547. if (unlikely(!test_bit(CNIC_F_CNIC_UP, &dev->flags)))
  2548. return;
  2549. while (1) {
  2550. status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq1);
  2551. CNIC_WR16(dev, cp->kcq1.io_addr,
  2552. cp->kcq1.sw_prod_idx + MAX_KCQ_IDX);
  2553. if (!BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  2554. cnic_ack_bnx2x_int(dev, cp->bnx2x_igu_sb_id, USTORM_ID,
  2555. status_idx, IGU_INT_ENABLE, 1);
  2556. break;
  2557. }
  2558. new_status_idx = cnic_service_bnx2x_kcq(dev, &cp->kcq2);
  2559. if (new_status_idx != status_idx)
  2560. continue;
  2561. CNIC_WR16(dev, cp->kcq2.io_addr, cp->kcq2.sw_prod_idx +
  2562. MAX_KCQ_IDX);
  2563. cnic_ack_igu_sb(dev, cp->bnx2x_igu_sb_id, IGU_SEG_ACCESS_DEF,
  2564. status_idx, IGU_INT_ENABLE, 1);
  2565. break;
  2566. }
  2567. }
  2568. static int cnic_service_bnx2x(void *data, void *status_blk)
  2569. {
  2570. struct cnic_dev *dev = data;
  2571. struct cnic_local *cp = dev->cnic_priv;
  2572. if (!(cp->ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  2573. cnic_doirq(dev);
  2574. cnic_chk_pkt_rings(cp);
  2575. return 0;
  2576. }
  2577. static void cnic_ulp_stop_one(struct cnic_local *cp, int if_type)
  2578. {
  2579. struct cnic_ulp_ops *ulp_ops;
  2580. if (if_type == CNIC_ULP_ISCSI)
  2581. cnic_send_nlmsg(cp, ISCSI_KEVENT_IF_DOWN, NULL);
  2582. mutex_lock(&cnic_lock);
  2583. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2584. lockdep_is_held(&cnic_lock));
  2585. if (!ulp_ops) {
  2586. mutex_unlock(&cnic_lock);
  2587. return;
  2588. }
  2589. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2590. mutex_unlock(&cnic_lock);
  2591. if (test_and_clear_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2592. ulp_ops->cnic_stop(cp->ulp_handle[if_type]);
  2593. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2594. }
  2595. static void cnic_ulp_stop(struct cnic_dev *dev)
  2596. {
  2597. struct cnic_local *cp = dev->cnic_priv;
  2598. int if_type;
  2599. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++)
  2600. cnic_ulp_stop_one(cp, if_type);
  2601. }
  2602. static void cnic_ulp_start(struct cnic_dev *dev)
  2603. {
  2604. struct cnic_local *cp = dev->cnic_priv;
  2605. int if_type;
  2606. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  2607. struct cnic_ulp_ops *ulp_ops;
  2608. mutex_lock(&cnic_lock);
  2609. ulp_ops = rcu_dereference_protected(cp->ulp_ops[if_type],
  2610. lockdep_is_held(&cnic_lock));
  2611. if (!ulp_ops || !ulp_ops->cnic_start) {
  2612. mutex_unlock(&cnic_lock);
  2613. continue;
  2614. }
  2615. set_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2616. mutex_unlock(&cnic_lock);
  2617. if (!test_and_set_bit(ULP_F_START, &cp->ulp_flags[if_type]))
  2618. ulp_ops->cnic_start(cp->ulp_handle[if_type]);
  2619. clear_bit(ULP_F_CALL_PENDING, &cp->ulp_flags[if_type]);
  2620. }
  2621. }
  2622. static int cnic_copy_ulp_stats(struct cnic_dev *dev, int ulp_type)
  2623. {
  2624. struct cnic_local *cp = dev->cnic_priv;
  2625. struct cnic_ulp_ops *ulp_ops;
  2626. int rc;
  2627. mutex_lock(&cnic_lock);
  2628. ulp_ops = cnic_ulp_tbl_prot(ulp_type);
  2629. if (ulp_ops && ulp_ops->cnic_get_stats)
  2630. rc = ulp_ops->cnic_get_stats(cp->ulp_handle[ulp_type]);
  2631. else
  2632. rc = -ENODEV;
  2633. mutex_unlock(&cnic_lock);
  2634. return rc;
  2635. }
  2636. static int cnic_ctl(void *data, struct cnic_ctl_info *info)
  2637. {
  2638. struct cnic_dev *dev = data;
  2639. int ulp_type = CNIC_ULP_ISCSI;
  2640. switch (info->cmd) {
  2641. case CNIC_CTL_STOP_CMD:
  2642. cnic_hold(dev);
  2643. cnic_ulp_stop(dev);
  2644. cnic_stop_hw(dev);
  2645. cnic_put(dev);
  2646. break;
  2647. case CNIC_CTL_START_CMD:
  2648. cnic_hold(dev);
  2649. if (!cnic_start_hw(dev))
  2650. cnic_ulp_start(dev);
  2651. cnic_put(dev);
  2652. break;
  2653. case CNIC_CTL_STOP_ISCSI_CMD: {
  2654. struct cnic_local *cp = dev->cnic_priv;
  2655. set_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags);
  2656. queue_delayed_work(cnic_wq, &cp->delete_task, 0);
  2657. break;
  2658. }
  2659. case CNIC_CTL_COMPLETION_CMD: {
  2660. struct cnic_ctl_completion *comp = &info->data.comp;
  2661. u32 cid = BNX2X_SW_CID(comp->cid);
  2662. u32 l5_cid;
  2663. struct cnic_local *cp = dev->cnic_priv;
  2664. if (cnic_get_l5_cid(cp, cid, &l5_cid) == 0) {
  2665. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2666. if (unlikely(comp->error)) {
  2667. set_bit(CTX_FL_CID_ERROR, &ctx->ctx_flags);
  2668. netdev_err(dev->netdev,
  2669. "CID %x CFC delete comp error %x\n",
  2670. cid, comp->error);
  2671. }
  2672. ctx->wait_cond = 1;
  2673. wake_up(&ctx->waitq);
  2674. }
  2675. break;
  2676. }
  2677. case CNIC_CTL_FCOE_STATS_GET_CMD:
  2678. ulp_type = CNIC_ULP_FCOE;
  2679. /* fall through */
  2680. case CNIC_CTL_ISCSI_STATS_GET_CMD:
  2681. cnic_hold(dev);
  2682. cnic_copy_ulp_stats(dev, ulp_type);
  2683. cnic_put(dev);
  2684. break;
  2685. default:
  2686. return -EINVAL;
  2687. }
  2688. return 0;
  2689. }
  2690. static void cnic_ulp_init(struct cnic_dev *dev)
  2691. {
  2692. int i;
  2693. struct cnic_local *cp = dev->cnic_priv;
  2694. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2695. struct cnic_ulp_ops *ulp_ops;
  2696. mutex_lock(&cnic_lock);
  2697. ulp_ops = cnic_ulp_tbl_prot(i);
  2698. if (!ulp_ops || !ulp_ops->cnic_init) {
  2699. mutex_unlock(&cnic_lock);
  2700. continue;
  2701. }
  2702. ulp_get(ulp_ops);
  2703. mutex_unlock(&cnic_lock);
  2704. if (!test_and_set_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2705. ulp_ops->cnic_init(dev);
  2706. ulp_put(ulp_ops);
  2707. }
  2708. }
  2709. static void cnic_ulp_exit(struct cnic_dev *dev)
  2710. {
  2711. int i;
  2712. struct cnic_local *cp = dev->cnic_priv;
  2713. for (i = 0; i < MAX_CNIC_ULP_TYPE_EXT; i++) {
  2714. struct cnic_ulp_ops *ulp_ops;
  2715. mutex_lock(&cnic_lock);
  2716. ulp_ops = cnic_ulp_tbl_prot(i);
  2717. if (!ulp_ops || !ulp_ops->cnic_exit) {
  2718. mutex_unlock(&cnic_lock);
  2719. continue;
  2720. }
  2721. ulp_get(ulp_ops);
  2722. mutex_unlock(&cnic_lock);
  2723. if (test_and_clear_bit(ULP_F_INIT, &cp->ulp_flags[i]))
  2724. ulp_ops->cnic_exit(dev);
  2725. ulp_put(ulp_ops);
  2726. }
  2727. }
  2728. static int cnic_cm_offload_pg(struct cnic_sock *csk)
  2729. {
  2730. struct cnic_dev *dev = csk->dev;
  2731. struct l4_kwq_offload_pg *l4kwqe;
  2732. struct kwqe *wqes[1];
  2733. l4kwqe = (struct l4_kwq_offload_pg *) &csk->kwqe1;
  2734. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2735. wqes[0] = (struct kwqe *) l4kwqe;
  2736. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_OFFLOAD_PG;
  2737. l4kwqe->flags =
  2738. L4_LAYER_CODE << L4_KWQ_OFFLOAD_PG_LAYER_CODE_SHIFT;
  2739. l4kwqe->l2hdr_nbytes = ETH_HLEN;
  2740. l4kwqe->da0 = csk->ha[0];
  2741. l4kwqe->da1 = csk->ha[1];
  2742. l4kwqe->da2 = csk->ha[2];
  2743. l4kwqe->da3 = csk->ha[3];
  2744. l4kwqe->da4 = csk->ha[4];
  2745. l4kwqe->da5 = csk->ha[5];
  2746. l4kwqe->sa0 = dev->mac_addr[0];
  2747. l4kwqe->sa1 = dev->mac_addr[1];
  2748. l4kwqe->sa2 = dev->mac_addr[2];
  2749. l4kwqe->sa3 = dev->mac_addr[3];
  2750. l4kwqe->sa4 = dev->mac_addr[4];
  2751. l4kwqe->sa5 = dev->mac_addr[5];
  2752. l4kwqe->etype = ETH_P_IP;
  2753. l4kwqe->ipid_start = DEF_IPID_START;
  2754. l4kwqe->host_opaque = csk->l5_cid;
  2755. if (csk->vlan_id) {
  2756. l4kwqe->pg_flags |= L4_KWQ_OFFLOAD_PG_VLAN_TAGGING;
  2757. l4kwqe->vlan_tag = csk->vlan_id;
  2758. l4kwqe->l2hdr_nbytes += 4;
  2759. }
  2760. return dev->submit_kwqes(dev, wqes, 1);
  2761. }
  2762. static int cnic_cm_update_pg(struct cnic_sock *csk)
  2763. {
  2764. struct cnic_dev *dev = csk->dev;
  2765. struct l4_kwq_update_pg *l4kwqe;
  2766. struct kwqe *wqes[1];
  2767. l4kwqe = (struct l4_kwq_update_pg *) &csk->kwqe1;
  2768. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2769. wqes[0] = (struct kwqe *) l4kwqe;
  2770. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPDATE_PG;
  2771. l4kwqe->flags =
  2772. L4_LAYER_CODE << L4_KWQ_UPDATE_PG_LAYER_CODE_SHIFT;
  2773. l4kwqe->pg_cid = csk->pg_cid;
  2774. l4kwqe->da0 = csk->ha[0];
  2775. l4kwqe->da1 = csk->ha[1];
  2776. l4kwqe->da2 = csk->ha[2];
  2777. l4kwqe->da3 = csk->ha[3];
  2778. l4kwqe->da4 = csk->ha[4];
  2779. l4kwqe->da5 = csk->ha[5];
  2780. l4kwqe->pg_host_opaque = csk->l5_cid;
  2781. l4kwqe->pg_valids = L4_KWQ_UPDATE_PG_VALIDS_DA;
  2782. return dev->submit_kwqes(dev, wqes, 1);
  2783. }
  2784. static int cnic_cm_upload_pg(struct cnic_sock *csk)
  2785. {
  2786. struct cnic_dev *dev = csk->dev;
  2787. struct l4_kwq_upload *l4kwqe;
  2788. struct kwqe *wqes[1];
  2789. l4kwqe = (struct l4_kwq_upload *) &csk->kwqe1;
  2790. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2791. wqes[0] = (struct kwqe *) l4kwqe;
  2792. l4kwqe->opcode = L4_KWQE_OPCODE_VALUE_UPLOAD_PG;
  2793. l4kwqe->flags =
  2794. L4_LAYER_CODE << L4_KWQ_UPLOAD_LAYER_CODE_SHIFT;
  2795. l4kwqe->cid = csk->pg_cid;
  2796. return dev->submit_kwqes(dev, wqes, 1);
  2797. }
  2798. static int cnic_cm_conn_req(struct cnic_sock *csk)
  2799. {
  2800. struct cnic_dev *dev = csk->dev;
  2801. struct l4_kwq_connect_req1 *l4kwqe1;
  2802. struct l4_kwq_connect_req2 *l4kwqe2;
  2803. struct l4_kwq_connect_req3 *l4kwqe3;
  2804. struct kwqe *wqes[3];
  2805. u8 tcp_flags = 0;
  2806. int num_wqes = 2;
  2807. l4kwqe1 = (struct l4_kwq_connect_req1 *) &csk->kwqe1;
  2808. l4kwqe2 = (struct l4_kwq_connect_req2 *) &csk->kwqe2;
  2809. l4kwqe3 = (struct l4_kwq_connect_req3 *) &csk->kwqe3;
  2810. memset(l4kwqe1, 0, sizeof(*l4kwqe1));
  2811. memset(l4kwqe2, 0, sizeof(*l4kwqe2));
  2812. memset(l4kwqe3, 0, sizeof(*l4kwqe3));
  2813. l4kwqe3->op_code = L4_KWQE_OPCODE_VALUE_CONNECT3;
  2814. l4kwqe3->flags =
  2815. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ3_LAYER_CODE_SHIFT;
  2816. l4kwqe3->ka_timeout = csk->ka_timeout;
  2817. l4kwqe3->ka_interval = csk->ka_interval;
  2818. l4kwqe3->ka_max_probe_count = csk->ka_max_probe_count;
  2819. l4kwqe3->tos = csk->tos;
  2820. l4kwqe3->ttl = csk->ttl;
  2821. l4kwqe3->snd_seq_scale = csk->snd_seq_scale;
  2822. l4kwqe3->pmtu = csk->mtu;
  2823. l4kwqe3->rcv_buf = csk->rcv_buf;
  2824. l4kwqe3->snd_buf = csk->snd_buf;
  2825. l4kwqe3->seed = csk->seed;
  2826. wqes[0] = (struct kwqe *) l4kwqe1;
  2827. if (test_bit(SK_F_IPV6, &csk->flags)) {
  2828. wqes[1] = (struct kwqe *) l4kwqe2;
  2829. wqes[2] = (struct kwqe *) l4kwqe3;
  2830. num_wqes = 3;
  2831. l4kwqe1->conn_flags = L4_KWQ_CONNECT_REQ1_IP_V6;
  2832. l4kwqe2->op_code = L4_KWQE_OPCODE_VALUE_CONNECT2;
  2833. l4kwqe2->flags =
  2834. L4_KWQ_CONNECT_REQ2_LINKED_WITH_NEXT |
  2835. L4_LAYER_CODE << L4_KWQ_CONNECT_REQ2_LAYER_CODE_SHIFT;
  2836. l4kwqe2->src_ip_v6_2 = be32_to_cpu(csk->src_ip[1]);
  2837. l4kwqe2->src_ip_v6_3 = be32_to_cpu(csk->src_ip[2]);
  2838. l4kwqe2->src_ip_v6_4 = be32_to_cpu(csk->src_ip[3]);
  2839. l4kwqe2->dst_ip_v6_2 = be32_to_cpu(csk->dst_ip[1]);
  2840. l4kwqe2->dst_ip_v6_3 = be32_to_cpu(csk->dst_ip[2]);
  2841. l4kwqe2->dst_ip_v6_4 = be32_to_cpu(csk->dst_ip[3]);
  2842. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct ipv6hdr) -
  2843. sizeof(struct tcphdr);
  2844. } else {
  2845. wqes[1] = (struct kwqe *) l4kwqe3;
  2846. l4kwqe3->mss = l4kwqe3->pmtu - sizeof(struct iphdr) -
  2847. sizeof(struct tcphdr);
  2848. }
  2849. l4kwqe1->op_code = L4_KWQE_OPCODE_VALUE_CONNECT1;
  2850. l4kwqe1->flags =
  2851. (L4_LAYER_CODE << L4_KWQ_CONNECT_REQ1_LAYER_CODE_SHIFT) |
  2852. L4_KWQ_CONNECT_REQ3_LINKED_WITH_NEXT;
  2853. l4kwqe1->cid = csk->cid;
  2854. l4kwqe1->pg_cid = csk->pg_cid;
  2855. l4kwqe1->src_ip = be32_to_cpu(csk->src_ip[0]);
  2856. l4kwqe1->dst_ip = be32_to_cpu(csk->dst_ip[0]);
  2857. l4kwqe1->src_port = be16_to_cpu(csk->src_port);
  2858. l4kwqe1->dst_port = be16_to_cpu(csk->dst_port);
  2859. if (csk->tcp_flags & SK_TCP_NO_DELAY_ACK)
  2860. tcp_flags |= L4_KWQ_CONNECT_REQ1_NO_DELAY_ACK;
  2861. if (csk->tcp_flags & SK_TCP_KEEP_ALIVE)
  2862. tcp_flags |= L4_KWQ_CONNECT_REQ1_KEEP_ALIVE;
  2863. if (csk->tcp_flags & SK_TCP_NAGLE)
  2864. tcp_flags |= L4_KWQ_CONNECT_REQ1_NAGLE_ENABLE;
  2865. if (csk->tcp_flags & SK_TCP_TIMESTAMP)
  2866. tcp_flags |= L4_KWQ_CONNECT_REQ1_TIME_STAMP;
  2867. if (csk->tcp_flags & SK_TCP_SACK)
  2868. tcp_flags |= L4_KWQ_CONNECT_REQ1_SACK;
  2869. if (csk->tcp_flags & SK_TCP_SEG_SCALING)
  2870. tcp_flags |= L4_KWQ_CONNECT_REQ1_SEG_SCALING;
  2871. l4kwqe1->tcp_flags = tcp_flags;
  2872. return dev->submit_kwqes(dev, wqes, num_wqes);
  2873. }
  2874. static int cnic_cm_close_req(struct cnic_sock *csk)
  2875. {
  2876. struct cnic_dev *dev = csk->dev;
  2877. struct l4_kwq_close_req *l4kwqe;
  2878. struct kwqe *wqes[1];
  2879. l4kwqe = (struct l4_kwq_close_req *) &csk->kwqe2;
  2880. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2881. wqes[0] = (struct kwqe *) l4kwqe;
  2882. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_CLOSE;
  2883. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_CLOSE_REQ_LAYER_CODE_SHIFT;
  2884. l4kwqe->cid = csk->cid;
  2885. return dev->submit_kwqes(dev, wqes, 1);
  2886. }
  2887. static int cnic_cm_abort_req(struct cnic_sock *csk)
  2888. {
  2889. struct cnic_dev *dev = csk->dev;
  2890. struct l4_kwq_reset_req *l4kwqe;
  2891. struct kwqe *wqes[1];
  2892. l4kwqe = (struct l4_kwq_reset_req *) &csk->kwqe2;
  2893. memset(l4kwqe, 0, sizeof(*l4kwqe));
  2894. wqes[0] = (struct kwqe *) l4kwqe;
  2895. l4kwqe->op_code = L4_KWQE_OPCODE_VALUE_RESET;
  2896. l4kwqe->flags = L4_LAYER_CODE << L4_KWQ_RESET_REQ_LAYER_CODE_SHIFT;
  2897. l4kwqe->cid = csk->cid;
  2898. return dev->submit_kwqes(dev, wqes, 1);
  2899. }
  2900. static int cnic_cm_create(struct cnic_dev *dev, int ulp_type, u32 cid,
  2901. u32 l5_cid, struct cnic_sock **csk, void *context)
  2902. {
  2903. struct cnic_local *cp = dev->cnic_priv;
  2904. struct cnic_sock *csk1;
  2905. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  2906. return -EINVAL;
  2907. if (cp->ctx_tbl) {
  2908. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  2909. if (test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags))
  2910. return -EAGAIN;
  2911. }
  2912. csk1 = &cp->csk_tbl[l5_cid];
  2913. if (atomic_read(&csk1->ref_count))
  2914. return -EAGAIN;
  2915. if (test_and_set_bit(SK_F_INUSE, &csk1->flags))
  2916. return -EBUSY;
  2917. csk1->dev = dev;
  2918. csk1->cid = cid;
  2919. csk1->l5_cid = l5_cid;
  2920. csk1->ulp_type = ulp_type;
  2921. csk1->context = context;
  2922. csk1->ka_timeout = DEF_KA_TIMEOUT;
  2923. csk1->ka_interval = DEF_KA_INTERVAL;
  2924. csk1->ka_max_probe_count = DEF_KA_MAX_PROBE_COUNT;
  2925. csk1->tos = DEF_TOS;
  2926. csk1->ttl = DEF_TTL;
  2927. csk1->snd_seq_scale = DEF_SND_SEQ_SCALE;
  2928. csk1->rcv_buf = DEF_RCV_BUF;
  2929. csk1->snd_buf = DEF_SND_BUF;
  2930. csk1->seed = DEF_SEED;
  2931. *csk = csk1;
  2932. return 0;
  2933. }
  2934. static void cnic_cm_cleanup(struct cnic_sock *csk)
  2935. {
  2936. if (csk->src_port) {
  2937. struct cnic_dev *dev = csk->dev;
  2938. struct cnic_local *cp = dev->cnic_priv;
  2939. cnic_free_id(&cp->csk_port_tbl, be16_to_cpu(csk->src_port));
  2940. csk->src_port = 0;
  2941. }
  2942. }
  2943. static void cnic_close_conn(struct cnic_sock *csk)
  2944. {
  2945. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags)) {
  2946. cnic_cm_upload_pg(csk);
  2947. clear_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  2948. }
  2949. cnic_cm_cleanup(csk);
  2950. }
  2951. static int cnic_cm_destroy(struct cnic_sock *csk)
  2952. {
  2953. if (!cnic_in_use(csk))
  2954. return -EINVAL;
  2955. csk_hold(csk);
  2956. clear_bit(SK_F_INUSE, &csk->flags);
  2957. smp_mb__after_clear_bit();
  2958. while (atomic_read(&csk->ref_count) != 1)
  2959. msleep(1);
  2960. cnic_cm_cleanup(csk);
  2961. csk->flags = 0;
  2962. csk_put(csk);
  2963. return 0;
  2964. }
  2965. static inline u16 cnic_get_vlan(struct net_device *dev,
  2966. struct net_device **vlan_dev)
  2967. {
  2968. if (dev->priv_flags & IFF_802_1Q_VLAN) {
  2969. *vlan_dev = vlan_dev_real_dev(dev);
  2970. return vlan_dev_vlan_id(dev);
  2971. }
  2972. *vlan_dev = dev;
  2973. return 0;
  2974. }
  2975. static int cnic_get_v4_route(struct sockaddr_in *dst_addr,
  2976. struct dst_entry **dst)
  2977. {
  2978. #if defined(CONFIG_INET)
  2979. struct rtable *rt;
  2980. rt = ip_route_output(&init_net, dst_addr->sin_addr.s_addr, 0, 0, 0);
  2981. if (!IS_ERR(rt)) {
  2982. *dst = &rt->dst;
  2983. return 0;
  2984. }
  2985. return PTR_ERR(rt);
  2986. #else
  2987. return -ENETUNREACH;
  2988. #endif
  2989. }
  2990. static int cnic_get_v6_route(struct sockaddr_in6 *dst_addr,
  2991. struct dst_entry **dst)
  2992. {
  2993. #if defined(CONFIG_IPV6) || (defined(CONFIG_IPV6_MODULE) && defined(MODULE))
  2994. struct flowi6 fl6;
  2995. memset(&fl6, 0, sizeof(fl6));
  2996. fl6.daddr = dst_addr->sin6_addr;
  2997. if (ipv6_addr_type(&fl6.daddr) & IPV6_ADDR_LINKLOCAL)
  2998. fl6.flowi6_oif = dst_addr->sin6_scope_id;
  2999. *dst = ip6_route_output(&init_net, NULL, &fl6);
  3000. if ((*dst)->error) {
  3001. dst_release(*dst);
  3002. *dst = NULL;
  3003. return -ENETUNREACH;
  3004. } else
  3005. return 0;
  3006. #endif
  3007. return -ENETUNREACH;
  3008. }
  3009. static struct cnic_dev *cnic_cm_select_dev(struct sockaddr_in *dst_addr,
  3010. int ulp_type)
  3011. {
  3012. struct cnic_dev *dev = NULL;
  3013. struct dst_entry *dst;
  3014. struct net_device *netdev = NULL;
  3015. int err = -ENETUNREACH;
  3016. if (dst_addr->sin_family == AF_INET)
  3017. err = cnic_get_v4_route(dst_addr, &dst);
  3018. else if (dst_addr->sin_family == AF_INET6) {
  3019. struct sockaddr_in6 *dst_addr6 =
  3020. (struct sockaddr_in6 *) dst_addr;
  3021. err = cnic_get_v6_route(dst_addr6, &dst);
  3022. } else
  3023. return NULL;
  3024. if (err)
  3025. return NULL;
  3026. if (!dst->dev)
  3027. goto done;
  3028. cnic_get_vlan(dst->dev, &netdev);
  3029. dev = cnic_from_netdev(netdev);
  3030. done:
  3031. dst_release(dst);
  3032. if (dev)
  3033. cnic_put(dev);
  3034. return dev;
  3035. }
  3036. static int cnic_resolve_addr(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3037. {
  3038. struct cnic_dev *dev = csk->dev;
  3039. struct cnic_local *cp = dev->cnic_priv;
  3040. return cnic_send_nlmsg(cp, ISCSI_KEVENT_PATH_REQ, csk);
  3041. }
  3042. static int cnic_get_route(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3043. {
  3044. struct cnic_dev *dev = csk->dev;
  3045. struct cnic_local *cp = dev->cnic_priv;
  3046. int is_v6, rc = 0;
  3047. struct dst_entry *dst = NULL;
  3048. struct net_device *realdev;
  3049. __be16 local_port;
  3050. u32 port_id;
  3051. if (saddr->local.v6.sin6_family == AF_INET6 &&
  3052. saddr->remote.v6.sin6_family == AF_INET6)
  3053. is_v6 = 1;
  3054. else if (saddr->local.v4.sin_family == AF_INET &&
  3055. saddr->remote.v4.sin_family == AF_INET)
  3056. is_v6 = 0;
  3057. else
  3058. return -EINVAL;
  3059. clear_bit(SK_F_IPV6, &csk->flags);
  3060. if (is_v6) {
  3061. set_bit(SK_F_IPV6, &csk->flags);
  3062. cnic_get_v6_route(&saddr->remote.v6, &dst);
  3063. memcpy(&csk->dst_ip[0], &saddr->remote.v6.sin6_addr,
  3064. sizeof(struct in6_addr));
  3065. csk->dst_port = saddr->remote.v6.sin6_port;
  3066. local_port = saddr->local.v6.sin6_port;
  3067. } else {
  3068. cnic_get_v4_route(&saddr->remote.v4, &dst);
  3069. csk->dst_ip[0] = saddr->remote.v4.sin_addr.s_addr;
  3070. csk->dst_port = saddr->remote.v4.sin_port;
  3071. local_port = saddr->local.v4.sin_port;
  3072. }
  3073. csk->vlan_id = 0;
  3074. csk->mtu = dev->netdev->mtu;
  3075. if (dst && dst->dev) {
  3076. u16 vlan = cnic_get_vlan(dst->dev, &realdev);
  3077. if (realdev == dev->netdev) {
  3078. csk->vlan_id = vlan;
  3079. csk->mtu = dst_mtu(dst);
  3080. }
  3081. }
  3082. port_id = be16_to_cpu(local_port);
  3083. if (port_id >= CNIC_LOCAL_PORT_MIN &&
  3084. port_id < CNIC_LOCAL_PORT_MAX) {
  3085. if (cnic_alloc_id(&cp->csk_port_tbl, port_id))
  3086. port_id = 0;
  3087. } else
  3088. port_id = 0;
  3089. if (!port_id) {
  3090. port_id = cnic_alloc_new_id(&cp->csk_port_tbl);
  3091. if (port_id == -1) {
  3092. rc = -ENOMEM;
  3093. goto err_out;
  3094. }
  3095. local_port = cpu_to_be16(port_id);
  3096. }
  3097. csk->src_port = local_port;
  3098. err_out:
  3099. dst_release(dst);
  3100. return rc;
  3101. }
  3102. static void cnic_init_csk_state(struct cnic_sock *csk)
  3103. {
  3104. csk->state = 0;
  3105. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3106. clear_bit(SK_F_CLOSING, &csk->flags);
  3107. }
  3108. static int cnic_cm_connect(struct cnic_sock *csk, struct cnic_sockaddr *saddr)
  3109. {
  3110. struct cnic_local *cp = csk->dev->cnic_priv;
  3111. int err = 0;
  3112. if (cp->ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI)
  3113. return -EOPNOTSUPP;
  3114. if (!cnic_in_use(csk))
  3115. return -EINVAL;
  3116. if (test_and_set_bit(SK_F_CONNECT_START, &csk->flags))
  3117. return -EINVAL;
  3118. cnic_init_csk_state(csk);
  3119. err = cnic_get_route(csk, saddr);
  3120. if (err)
  3121. goto err_out;
  3122. err = cnic_resolve_addr(csk, saddr);
  3123. if (!err)
  3124. return 0;
  3125. err_out:
  3126. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3127. return err;
  3128. }
  3129. static int cnic_cm_abort(struct cnic_sock *csk)
  3130. {
  3131. struct cnic_local *cp = csk->dev->cnic_priv;
  3132. u32 opcode = L4_KCQE_OPCODE_VALUE_RESET_COMP;
  3133. if (!cnic_in_use(csk))
  3134. return -EINVAL;
  3135. if (cnic_abort_prep(csk))
  3136. return cnic_cm_abort_req(csk);
  3137. /* Getting here means that we haven't started connect, or
  3138. * connect was not successful.
  3139. */
  3140. cp->close_conn(csk, opcode);
  3141. if (csk->state != opcode)
  3142. return -EALREADY;
  3143. return 0;
  3144. }
  3145. static int cnic_cm_close(struct cnic_sock *csk)
  3146. {
  3147. if (!cnic_in_use(csk))
  3148. return -EINVAL;
  3149. if (cnic_close_prep(csk)) {
  3150. csk->state = L4_KCQE_OPCODE_VALUE_CLOSE_COMP;
  3151. return cnic_cm_close_req(csk);
  3152. } else {
  3153. return -EALREADY;
  3154. }
  3155. return 0;
  3156. }
  3157. static void cnic_cm_upcall(struct cnic_local *cp, struct cnic_sock *csk,
  3158. u8 opcode)
  3159. {
  3160. struct cnic_ulp_ops *ulp_ops;
  3161. int ulp_type = csk->ulp_type;
  3162. rcu_read_lock();
  3163. ulp_ops = rcu_dereference(cp->ulp_ops[ulp_type]);
  3164. if (ulp_ops) {
  3165. if (opcode == L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE)
  3166. ulp_ops->cm_connect_complete(csk);
  3167. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3168. ulp_ops->cm_close_complete(csk);
  3169. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED)
  3170. ulp_ops->cm_remote_abort(csk);
  3171. else if (opcode == L4_KCQE_OPCODE_VALUE_RESET_COMP)
  3172. ulp_ops->cm_abort_complete(csk);
  3173. else if (opcode == L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED)
  3174. ulp_ops->cm_remote_close(csk);
  3175. }
  3176. rcu_read_unlock();
  3177. }
  3178. static int cnic_cm_set_pg(struct cnic_sock *csk)
  3179. {
  3180. if (cnic_offld_prep(csk)) {
  3181. if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3182. cnic_cm_update_pg(csk);
  3183. else
  3184. cnic_cm_offload_pg(csk);
  3185. }
  3186. return 0;
  3187. }
  3188. static void cnic_cm_process_offld_pg(struct cnic_dev *dev, struct l4_kcq *kcqe)
  3189. {
  3190. struct cnic_local *cp = dev->cnic_priv;
  3191. u32 l5_cid = kcqe->pg_host_opaque;
  3192. u8 opcode = kcqe->op_code;
  3193. struct cnic_sock *csk = &cp->csk_tbl[l5_cid];
  3194. csk_hold(csk);
  3195. if (!cnic_in_use(csk))
  3196. goto done;
  3197. if (opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3198. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3199. goto done;
  3200. }
  3201. /* Possible PG kcqe status: SUCCESS, OFFLOADED_PG, or CTX_ALLOC_FAIL */
  3202. if (kcqe->status == L4_KCQE_COMPLETION_STATUS_CTX_ALLOC_FAIL) {
  3203. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3204. cnic_cm_upcall(cp, csk,
  3205. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3206. goto done;
  3207. }
  3208. csk->pg_cid = kcqe->pg_cid;
  3209. set_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags);
  3210. cnic_cm_conn_req(csk);
  3211. done:
  3212. csk_put(csk);
  3213. }
  3214. static void cnic_process_fcoe_term_conn(struct cnic_dev *dev, struct kcqe *kcqe)
  3215. {
  3216. struct cnic_local *cp = dev->cnic_priv;
  3217. struct fcoe_kcqe *fc_kcqe = (struct fcoe_kcqe *) kcqe;
  3218. u32 l5_cid = fc_kcqe->fcoe_conn_id + BNX2X_FCOE_L5_CID_BASE;
  3219. struct cnic_context *ctx = &cp->ctx_tbl[l5_cid];
  3220. ctx->timestamp = jiffies;
  3221. ctx->wait_cond = 1;
  3222. wake_up(&ctx->waitq);
  3223. }
  3224. static void cnic_cm_process_kcqe(struct cnic_dev *dev, struct kcqe *kcqe)
  3225. {
  3226. struct cnic_local *cp = dev->cnic_priv;
  3227. struct l4_kcq *l4kcqe = (struct l4_kcq *) kcqe;
  3228. u8 opcode = l4kcqe->op_code;
  3229. u32 l5_cid;
  3230. struct cnic_sock *csk;
  3231. if (opcode == FCOE_RAMROD_CMD_ID_TERMINATE_CONN) {
  3232. cnic_process_fcoe_term_conn(dev, kcqe);
  3233. return;
  3234. }
  3235. if (opcode == L4_KCQE_OPCODE_VALUE_OFFLOAD_PG ||
  3236. opcode == L4_KCQE_OPCODE_VALUE_UPDATE_PG) {
  3237. cnic_cm_process_offld_pg(dev, l4kcqe);
  3238. return;
  3239. }
  3240. l5_cid = l4kcqe->conn_id;
  3241. if (opcode & 0x80)
  3242. l5_cid = l4kcqe->cid;
  3243. if (l5_cid >= MAX_CM_SK_TBL_SZ)
  3244. return;
  3245. csk = &cp->csk_tbl[l5_cid];
  3246. csk_hold(csk);
  3247. if (!cnic_in_use(csk)) {
  3248. csk_put(csk);
  3249. return;
  3250. }
  3251. switch (opcode) {
  3252. case L5CM_RAMROD_CMD_ID_TCP_CONNECT:
  3253. if (l4kcqe->status != 0) {
  3254. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3255. cnic_cm_upcall(cp, csk,
  3256. L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE);
  3257. }
  3258. break;
  3259. case L4_KCQE_OPCODE_VALUE_CONNECT_COMPLETE:
  3260. if (l4kcqe->status == 0)
  3261. set_bit(SK_F_OFFLD_COMPLETE, &csk->flags);
  3262. else if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_NIC_ERROR)
  3263. set_bit(SK_F_HW_ERR, &csk->flags);
  3264. smp_mb__before_clear_bit();
  3265. clear_bit(SK_F_OFFLD_SCHED, &csk->flags);
  3266. cnic_cm_upcall(cp, csk, opcode);
  3267. break;
  3268. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3269. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3270. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3271. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3272. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3273. if (l4kcqe->status == L4_KCQE_COMPLETION_STATUS_NIC_ERROR)
  3274. set_bit(SK_F_HW_ERR, &csk->flags);
  3275. cp->close_conn(csk, opcode);
  3276. break;
  3277. case L4_KCQE_OPCODE_VALUE_CLOSE_RECEIVED:
  3278. /* after we already sent CLOSE_REQ */
  3279. if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags) &&
  3280. !test_bit(SK_F_OFFLD_COMPLETE, &csk->flags) &&
  3281. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP)
  3282. cp->close_conn(csk, L4_KCQE_OPCODE_VALUE_RESET_COMP);
  3283. else
  3284. cnic_cm_upcall(cp, csk, opcode);
  3285. break;
  3286. }
  3287. csk_put(csk);
  3288. }
  3289. static void cnic_cm_indicate_kcqe(void *data, struct kcqe *kcqe[], u32 num)
  3290. {
  3291. struct cnic_dev *dev = data;
  3292. int i;
  3293. for (i = 0; i < num; i++)
  3294. cnic_cm_process_kcqe(dev, kcqe[i]);
  3295. }
  3296. static struct cnic_ulp_ops cm_ulp_ops = {
  3297. .indicate_kcqes = cnic_cm_indicate_kcqe,
  3298. };
  3299. static void cnic_cm_free_mem(struct cnic_dev *dev)
  3300. {
  3301. struct cnic_local *cp = dev->cnic_priv;
  3302. kfree(cp->csk_tbl);
  3303. cp->csk_tbl = NULL;
  3304. cnic_free_id_tbl(&cp->csk_port_tbl);
  3305. }
  3306. static int cnic_cm_alloc_mem(struct cnic_dev *dev)
  3307. {
  3308. struct cnic_local *cp = dev->cnic_priv;
  3309. u32 port_id;
  3310. cp->csk_tbl = kzalloc(sizeof(struct cnic_sock) * MAX_CM_SK_TBL_SZ,
  3311. GFP_KERNEL);
  3312. if (!cp->csk_tbl)
  3313. return -ENOMEM;
  3314. port_id = random32();
  3315. port_id %= CNIC_LOCAL_PORT_RANGE;
  3316. if (cnic_init_id_tbl(&cp->csk_port_tbl, CNIC_LOCAL_PORT_RANGE,
  3317. CNIC_LOCAL_PORT_MIN, port_id)) {
  3318. cnic_cm_free_mem(dev);
  3319. return -ENOMEM;
  3320. }
  3321. return 0;
  3322. }
  3323. static int cnic_ready_to_close(struct cnic_sock *csk, u32 opcode)
  3324. {
  3325. if (test_and_clear_bit(SK_F_OFFLD_COMPLETE, &csk->flags)) {
  3326. /* Unsolicited RESET_COMP or RESET_RECEIVED */
  3327. opcode = L4_KCQE_OPCODE_VALUE_RESET_RECEIVED;
  3328. csk->state = opcode;
  3329. }
  3330. /* 1. If event opcode matches the expected event in csk->state
  3331. * 2. If the expected event is CLOSE_COMP or RESET_COMP, we accept any
  3332. * event
  3333. * 3. If the expected event is 0, meaning the connection was never
  3334. * never established, we accept the opcode from cm_abort.
  3335. */
  3336. if (opcode == csk->state || csk->state == 0 ||
  3337. csk->state == L4_KCQE_OPCODE_VALUE_CLOSE_COMP ||
  3338. csk->state == L4_KCQE_OPCODE_VALUE_RESET_COMP) {
  3339. if (!test_and_set_bit(SK_F_CLOSING, &csk->flags)) {
  3340. if (csk->state == 0)
  3341. csk->state = opcode;
  3342. return 1;
  3343. }
  3344. }
  3345. return 0;
  3346. }
  3347. static void cnic_close_bnx2_conn(struct cnic_sock *csk, u32 opcode)
  3348. {
  3349. struct cnic_dev *dev = csk->dev;
  3350. struct cnic_local *cp = dev->cnic_priv;
  3351. if (opcode == L4_KCQE_OPCODE_VALUE_RESET_RECEIVED) {
  3352. cnic_cm_upcall(cp, csk, opcode);
  3353. return;
  3354. }
  3355. clear_bit(SK_F_CONNECT_START, &csk->flags);
  3356. cnic_close_conn(csk);
  3357. csk->state = opcode;
  3358. cnic_cm_upcall(cp, csk, opcode);
  3359. }
  3360. static void cnic_cm_stop_bnx2_hw(struct cnic_dev *dev)
  3361. {
  3362. }
  3363. static int cnic_cm_init_bnx2_hw(struct cnic_dev *dev)
  3364. {
  3365. u32 seed;
  3366. seed = random32();
  3367. cnic_ctx_wr(dev, 45, 0, seed);
  3368. return 0;
  3369. }
  3370. static void cnic_close_bnx2x_conn(struct cnic_sock *csk, u32 opcode)
  3371. {
  3372. struct cnic_dev *dev = csk->dev;
  3373. struct cnic_local *cp = dev->cnic_priv;
  3374. struct cnic_context *ctx = &cp->ctx_tbl[csk->l5_cid];
  3375. union l5cm_specific_data l5_data;
  3376. u32 cmd = 0;
  3377. int close_complete = 0;
  3378. switch (opcode) {
  3379. case L4_KCQE_OPCODE_VALUE_RESET_RECEIVED:
  3380. case L4_KCQE_OPCODE_VALUE_CLOSE_COMP:
  3381. case L4_KCQE_OPCODE_VALUE_RESET_COMP:
  3382. if (cnic_ready_to_close(csk, opcode)) {
  3383. if (test_bit(SK_F_HW_ERR, &csk->flags))
  3384. close_complete = 1;
  3385. else if (test_bit(SK_F_PG_OFFLD_COMPLETE, &csk->flags))
  3386. cmd = L5CM_RAMROD_CMD_ID_SEARCHER_DELETE;
  3387. else
  3388. close_complete = 1;
  3389. }
  3390. break;
  3391. case L5CM_RAMROD_CMD_ID_SEARCHER_DELETE:
  3392. cmd = L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD;
  3393. break;
  3394. case L5CM_RAMROD_CMD_ID_TERMINATE_OFFLOAD:
  3395. close_complete = 1;
  3396. break;
  3397. }
  3398. if (cmd) {
  3399. memset(&l5_data, 0, sizeof(l5_data));
  3400. cnic_submit_kwqe_16(dev, cmd, csk->cid, ISCSI_CONNECTION_TYPE,
  3401. &l5_data);
  3402. } else if (close_complete) {
  3403. ctx->timestamp = jiffies;
  3404. cnic_close_conn(csk);
  3405. cnic_cm_upcall(cp, csk, csk->state);
  3406. }
  3407. }
  3408. static void cnic_cm_stop_bnx2x_hw(struct cnic_dev *dev)
  3409. {
  3410. struct cnic_local *cp = dev->cnic_priv;
  3411. if (!cp->ctx_tbl)
  3412. return;
  3413. if (!netif_running(dev->netdev))
  3414. return;
  3415. cnic_bnx2x_delete_wait(dev, 0);
  3416. cancel_delayed_work(&cp->delete_task);
  3417. flush_workqueue(cnic_wq);
  3418. if (atomic_read(&cp->iscsi_conn) != 0)
  3419. netdev_warn(dev->netdev, "%d iSCSI connections not destroyed\n",
  3420. atomic_read(&cp->iscsi_conn));
  3421. }
  3422. static int cnic_cm_init_bnx2x_hw(struct cnic_dev *dev)
  3423. {
  3424. struct cnic_local *cp = dev->cnic_priv;
  3425. u32 pfid = cp->pfid;
  3426. u32 port = CNIC_PORT(cp);
  3427. cnic_init_bnx2x_mac(dev);
  3428. cnic_bnx2x_set_tcp_timestamp(dev, 1);
  3429. CNIC_WR16(dev, BAR_XSTRORM_INTMEM +
  3430. XSTORM_ISCSI_LOCAL_VLAN_OFFSET(pfid), 0);
  3431. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3432. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_ENABLED_OFFSET(port), 1);
  3433. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3434. XSTORM_TCP_GLOBAL_DEL_ACK_COUNTER_MAX_COUNT_OFFSET(port),
  3435. DEF_MAX_DA_COUNT);
  3436. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3437. XSTORM_ISCSI_TCP_VARS_TTL_OFFSET(pfid), DEF_TTL);
  3438. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3439. XSTORM_ISCSI_TCP_VARS_TOS_OFFSET(pfid), DEF_TOS);
  3440. CNIC_WR8(dev, BAR_XSTRORM_INTMEM +
  3441. XSTORM_ISCSI_TCP_VARS_ADV_WND_SCL_OFFSET(pfid), 2);
  3442. CNIC_WR(dev, BAR_XSTRORM_INTMEM +
  3443. XSTORM_TCP_TX_SWS_TIMER_VAL_OFFSET(pfid), DEF_SWS_TIMER);
  3444. CNIC_WR(dev, BAR_TSTRORM_INTMEM + TSTORM_TCP_MAX_CWND_OFFSET(pfid),
  3445. DEF_MAX_CWND);
  3446. return 0;
  3447. }
  3448. static void cnic_delete_task(struct work_struct *work)
  3449. {
  3450. struct cnic_local *cp;
  3451. struct cnic_dev *dev;
  3452. u32 i;
  3453. int need_resched = 0;
  3454. cp = container_of(work, struct cnic_local, delete_task.work);
  3455. dev = cp->dev;
  3456. if (test_and_clear_bit(CNIC_LCL_FL_STOP_ISCSI, &cp->cnic_local_flags)) {
  3457. struct drv_ctl_info info;
  3458. cnic_ulp_stop_one(cp, CNIC_ULP_ISCSI);
  3459. info.cmd = DRV_CTL_ISCSI_STOPPED_CMD;
  3460. cp->ethdev->drv_ctl(dev->netdev, &info);
  3461. }
  3462. for (i = 0; i < cp->max_cid_space; i++) {
  3463. struct cnic_context *ctx = &cp->ctx_tbl[i];
  3464. int err;
  3465. if (!test_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags) ||
  3466. !test_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3467. continue;
  3468. if (!time_after(jiffies, ctx->timestamp + (2 * HZ))) {
  3469. need_resched = 1;
  3470. continue;
  3471. }
  3472. if (!test_and_clear_bit(CTX_FL_DELETE_WAIT, &ctx->ctx_flags))
  3473. continue;
  3474. err = cnic_bnx2x_destroy_ramrod(dev, i);
  3475. cnic_free_bnx2x_conn_resc(dev, i);
  3476. if (!err) {
  3477. if (ctx->ulp_proto_id == CNIC_ULP_ISCSI)
  3478. atomic_dec(&cp->iscsi_conn);
  3479. clear_bit(CTX_FL_OFFLD_START, &ctx->ctx_flags);
  3480. }
  3481. }
  3482. if (need_resched)
  3483. queue_delayed_work(cnic_wq, &cp->delete_task,
  3484. msecs_to_jiffies(10));
  3485. }
  3486. static int cnic_cm_open(struct cnic_dev *dev)
  3487. {
  3488. struct cnic_local *cp = dev->cnic_priv;
  3489. int err;
  3490. err = cnic_cm_alloc_mem(dev);
  3491. if (err)
  3492. return err;
  3493. err = cp->start_cm(dev);
  3494. if (err)
  3495. goto err_out;
  3496. INIT_DELAYED_WORK(&cp->delete_task, cnic_delete_task);
  3497. dev->cm_create = cnic_cm_create;
  3498. dev->cm_destroy = cnic_cm_destroy;
  3499. dev->cm_connect = cnic_cm_connect;
  3500. dev->cm_abort = cnic_cm_abort;
  3501. dev->cm_close = cnic_cm_close;
  3502. dev->cm_select_dev = cnic_cm_select_dev;
  3503. cp->ulp_handle[CNIC_ULP_L4] = dev;
  3504. rcu_assign_pointer(cp->ulp_ops[CNIC_ULP_L4], &cm_ulp_ops);
  3505. return 0;
  3506. err_out:
  3507. cnic_cm_free_mem(dev);
  3508. return err;
  3509. }
  3510. static int cnic_cm_shutdown(struct cnic_dev *dev)
  3511. {
  3512. struct cnic_local *cp = dev->cnic_priv;
  3513. int i;
  3514. cp->stop_cm(dev);
  3515. if (!cp->csk_tbl)
  3516. return 0;
  3517. for (i = 0; i < MAX_CM_SK_TBL_SZ; i++) {
  3518. struct cnic_sock *csk = &cp->csk_tbl[i];
  3519. clear_bit(SK_F_INUSE, &csk->flags);
  3520. cnic_cm_cleanup(csk);
  3521. }
  3522. cnic_cm_free_mem(dev);
  3523. return 0;
  3524. }
  3525. static void cnic_init_context(struct cnic_dev *dev, u32 cid)
  3526. {
  3527. u32 cid_addr;
  3528. int i;
  3529. cid_addr = GET_CID_ADDR(cid);
  3530. for (i = 0; i < CTX_SIZE; i += 4)
  3531. cnic_ctx_wr(dev, cid_addr, i, 0);
  3532. }
  3533. static int cnic_setup_5709_context(struct cnic_dev *dev, int valid)
  3534. {
  3535. struct cnic_local *cp = dev->cnic_priv;
  3536. int ret = 0, i;
  3537. u32 valid_bit = valid ? BNX2_CTX_HOST_PAGE_TBL_DATA0_VALID : 0;
  3538. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3539. return 0;
  3540. for (i = 0; i < cp->ctx_blks; i++) {
  3541. int j;
  3542. u32 idx = cp->ctx_arr[i].cid / cp->cids_per_blk;
  3543. u32 val;
  3544. memset(cp->ctx_arr[i].ctx, 0, BCM_PAGE_SIZE);
  3545. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA0,
  3546. (cp->ctx_arr[i].mapping & 0xffffffff) | valid_bit);
  3547. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_DATA1,
  3548. (u64) cp->ctx_arr[i].mapping >> 32);
  3549. CNIC_WR(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL, idx |
  3550. BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ);
  3551. for (j = 0; j < 10; j++) {
  3552. val = CNIC_RD(dev, BNX2_CTX_HOST_PAGE_TBL_CTRL);
  3553. if (!(val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ))
  3554. break;
  3555. udelay(5);
  3556. }
  3557. if (val & BNX2_CTX_HOST_PAGE_TBL_CTRL_WRITE_REQ) {
  3558. ret = -EBUSY;
  3559. break;
  3560. }
  3561. }
  3562. return ret;
  3563. }
  3564. static void cnic_free_irq(struct cnic_dev *dev)
  3565. {
  3566. struct cnic_local *cp = dev->cnic_priv;
  3567. struct cnic_eth_dev *ethdev = cp->ethdev;
  3568. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3569. cp->disable_int_sync(dev);
  3570. tasklet_kill(&cp->cnic_irq_task);
  3571. free_irq(ethdev->irq_arr[0].vector, dev);
  3572. }
  3573. }
  3574. static int cnic_request_irq(struct cnic_dev *dev)
  3575. {
  3576. struct cnic_local *cp = dev->cnic_priv;
  3577. struct cnic_eth_dev *ethdev = cp->ethdev;
  3578. int err;
  3579. err = request_irq(ethdev->irq_arr[0].vector, cnic_irq, 0, "cnic", dev);
  3580. if (err)
  3581. tasklet_disable(&cp->cnic_irq_task);
  3582. return err;
  3583. }
  3584. static int cnic_init_bnx2_irq(struct cnic_dev *dev)
  3585. {
  3586. struct cnic_local *cp = dev->cnic_priv;
  3587. struct cnic_eth_dev *ethdev = cp->ethdev;
  3588. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3589. int err, i = 0;
  3590. int sblk_num = cp->status_blk_num;
  3591. u32 base = ((sblk_num - 1) * BNX2_HC_SB_CONFIG_SIZE) +
  3592. BNX2_HC_SB_CONFIG_1;
  3593. CNIC_WR(dev, base, BNX2_HC_SB_CONFIG_1_ONE_SHOT);
  3594. CNIC_WR(dev, base + BNX2_HC_COMP_PROD_TRIP_OFF, (2 << 16) | 8);
  3595. CNIC_WR(dev, base + BNX2_HC_COM_TICKS_OFF, (64 << 16) | 220);
  3596. CNIC_WR(dev, base + BNX2_HC_CMD_TICKS_OFF, (64 << 16) | 220);
  3597. cp->last_status_idx = cp->status_blk.bnx2->status_idx;
  3598. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2_msix,
  3599. (unsigned long) dev);
  3600. err = cnic_request_irq(dev);
  3601. if (err)
  3602. return err;
  3603. while (cp->status_blk.bnx2->status_completion_producer_index &&
  3604. i < 10) {
  3605. CNIC_WR(dev, BNX2_HC_COALESCE_NOW,
  3606. 1 << (11 + sblk_num));
  3607. udelay(10);
  3608. i++;
  3609. barrier();
  3610. }
  3611. if (cp->status_blk.bnx2->status_completion_producer_index) {
  3612. cnic_free_irq(dev);
  3613. goto failed;
  3614. }
  3615. } else {
  3616. struct status_block *sblk = cp->status_blk.gen;
  3617. u32 hc_cmd = CNIC_RD(dev, BNX2_HC_COMMAND);
  3618. int i = 0;
  3619. while (sblk->status_completion_producer_index && i < 10) {
  3620. CNIC_WR(dev, BNX2_HC_COMMAND,
  3621. hc_cmd | BNX2_HC_COMMAND_COAL_NOW_WO_INT);
  3622. udelay(10);
  3623. i++;
  3624. barrier();
  3625. }
  3626. if (sblk->status_completion_producer_index)
  3627. goto failed;
  3628. }
  3629. return 0;
  3630. failed:
  3631. netdev_err(dev->netdev, "KCQ index not resetting to 0\n");
  3632. return -EBUSY;
  3633. }
  3634. static void cnic_enable_bnx2_int(struct cnic_dev *dev)
  3635. {
  3636. struct cnic_local *cp = dev->cnic_priv;
  3637. struct cnic_eth_dev *ethdev = cp->ethdev;
  3638. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3639. return;
  3640. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3641. BNX2_PCICFG_INT_ACK_CMD_INDEX_VALID | cp->last_status_idx);
  3642. }
  3643. static void cnic_disable_bnx2_int_sync(struct cnic_dev *dev)
  3644. {
  3645. struct cnic_local *cp = dev->cnic_priv;
  3646. struct cnic_eth_dev *ethdev = cp->ethdev;
  3647. if (!(ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX))
  3648. return;
  3649. CNIC_WR(dev, BNX2_PCICFG_INT_ACK_CMD, cp->int_num |
  3650. BNX2_PCICFG_INT_ACK_CMD_MASK_INT);
  3651. CNIC_RD(dev, BNX2_PCICFG_INT_ACK_CMD);
  3652. synchronize_irq(ethdev->irq_arr[0].vector);
  3653. }
  3654. static void cnic_init_bnx2_tx_ring(struct cnic_dev *dev)
  3655. {
  3656. struct cnic_local *cp = dev->cnic_priv;
  3657. struct cnic_eth_dev *ethdev = cp->ethdev;
  3658. struct cnic_uio_dev *udev = cp->udev;
  3659. u32 cid_addr, tx_cid, sb_id;
  3660. u32 val, offset0, offset1, offset2, offset3;
  3661. int i;
  3662. struct tx_bd *txbd;
  3663. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3664. struct status_block *s_blk = cp->status_blk.gen;
  3665. sb_id = cp->status_blk_num;
  3666. tx_cid = 20;
  3667. cp->tx_cons_ptr = &s_blk->status_tx_quick_consumer_index2;
  3668. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3669. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3670. tx_cid = TX_TSS_CID + sb_id - 1;
  3671. CNIC_WR(dev, BNX2_TSCH_TSS_CFG, (sb_id << 24) |
  3672. (TX_TSS_CID << 7));
  3673. cp->tx_cons_ptr = &sblk->status_tx_quick_consumer_index;
  3674. }
  3675. cp->tx_cons = *cp->tx_cons_ptr;
  3676. cid_addr = GET_CID_ADDR(tx_cid);
  3677. if (CHIP_NUM(cp) == CHIP_NUM_5709) {
  3678. u32 cid_addr2 = GET_CID_ADDR(tx_cid + 4) + 0x40;
  3679. for (i = 0; i < PHY_CTX_SIZE; i += 4)
  3680. cnic_ctx_wr(dev, cid_addr2, i, 0);
  3681. offset0 = BNX2_L2CTX_TYPE_XI;
  3682. offset1 = BNX2_L2CTX_CMD_TYPE_XI;
  3683. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI_XI;
  3684. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO_XI;
  3685. } else {
  3686. cnic_init_context(dev, tx_cid);
  3687. cnic_init_context(dev, tx_cid + 1);
  3688. offset0 = BNX2_L2CTX_TYPE;
  3689. offset1 = BNX2_L2CTX_CMD_TYPE;
  3690. offset2 = BNX2_L2CTX_TBDR_BHADDR_HI;
  3691. offset3 = BNX2_L2CTX_TBDR_BHADDR_LO;
  3692. }
  3693. val = BNX2_L2CTX_TYPE_TYPE_L2 | BNX2_L2CTX_TYPE_SIZE_L2;
  3694. cnic_ctx_wr(dev, cid_addr, offset0, val);
  3695. val = BNX2_L2CTX_CMD_TYPE_TYPE_L2 | (8 << 16);
  3696. cnic_ctx_wr(dev, cid_addr, offset1, val);
  3697. txbd = udev->l2_ring;
  3698. buf_map = udev->l2_buf_map;
  3699. for (i = 0; i < MAX_TX_DESC_CNT; i++, txbd++) {
  3700. txbd->tx_bd_haddr_hi = (u64) buf_map >> 32;
  3701. txbd->tx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3702. }
  3703. val = (u64) ring_map >> 32;
  3704. cnic_ctx_wr(dev, cid_addr, offset2, val);
  3705. txbd->tx_bd_haddr_hi = val;
  3706. val = (u64) ring_map & 0xffffffff;
  3707. cnic_ctx_wr(dev, cid_addr, offset3, val);
  3708. txbd->tx_bd_haddr_lo = val;
  3709. }
  3710. static void cnic_init_bnx2_rx_ring(struct cnic_dev *dev)
  3711. {
  3712. struct cnic_local *cp = dev->cnic_priv;
  3713. struct cnic_eth_dev *ethdev = cp->ethdev;
  3714. struct cnic_uio_dev *udev = cp->udev;
  3715. u32 cid_addr, sb_id, val, coal_reg, coal_val;
  3716. int i;
  3717. struct rx_bd *rxbd;
  3718. struct status_block *s_blk = cp->status_blk.gen;
  3719. dma_addr_t ring_map = udev->l2_ring_map;
  3720. sb_id = cp->status_blk_num;
  3721. cnic_init_context(dev, 2);
  3722. cp->rx_cons_ptr = &s_blk->status_rx_quick_consumer_index2;
  3723. coal_reg = BNX2_HC_COMMAND;
  3724. coal_val = CNIC_RD(dev, coal_reg);
  3725. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3726. struct status_block_msix *sblk = cp->status_blk.bnx2;
  3727. cp->rx_cons_ptr = &sblk->status_rx_quick_consumer_index;
  3728. coal_reg = BNX2_HC_COALESCE_NOW;
  3729. coal_val = 1 << (11 + sb_id);
  3730. }
  3731. i = 0;
  3732. while (!(*cp->rx_cons_ptr != 0) && i < 10) {
  3733. CNIC_WR(dev, coal_reg, coal_val);
  3734. udelay(10);
  3735. i++;
  3736. barrier();
  3737. }
  3738. cp->rx_cons = *cp->rx_cons_ptr;
  3739. cid_addr = GET_CID_ADDR(2);
  3740. val = BNX2_L2CTX_CTX_TYPE_CTX_BD_CHN_TYPE_VALUE |
  3741. BNX2_L2CTX_CTX_TYPE_SIZE_L2 | (0x02 << 8);
  3742. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_CTX_TYPE, val);
  3743. if (sb_id == 0)
  3744. val = 2 << BNX2_L2CTX_L2_STATUSB_NUM_SHIFT;
  3745. else
  3746. val = BNX2_L2CTX_L2_STATUSB_NUM(sb_id);
  3747. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_HOST_BDIDX, val);
  3748. rxbd = udev->l2_ring + BCM_PAGE_SIZE;
  3749. for (i = 0; i < MAX_RX_DESC_CNT; i++, rxbd++) {
  3750. dma_addr_t buf_map;
  3751. int n = (i % cp->l2_rx_ring_size) + 1;
  3752. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  3753. rxbd->rx_bd_len = cp->l2_single_buf_size;
  3754. rxbd->rx_bd_flags = RX_BD_FLAGS_START | RX_BD_FLAGS_END;
  3755. rxbd->rx_bd_haddr_hi = (u64) buf_map >> 32;
  3756. rxbd->rx_bd_haddr_lo = (u64) buf_map & 0xffffffff;
  3757. }
  3758. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  3759. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_HI, val);
  3760. rxbd->rx_bd_haddr_hi = val;
  3761. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  3762. cnic_ctx_wr(dev, cid_addr, BNX2_L2CTX_NX_BDHADDR_LO, val);
  3763. rxbd->rx_bd_haddr_lo = val;
  3764. val = cnic_reg_rd_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD);
  3765. cnic_reg_wr_ind(dev, BNX2_RXP_SCRATCH_RXP_FLOOD, val | (1 << 2));
  3766. }
  3767. static void cnic_shutdown_bnx2_rx_ring(struct cnic_dev *dev)
  3768. {
  3769. struct kwqe *wqes[1], l2kwqe;
  3770. memset(&l2kwqe, 0, sizeof(l2kwqe));
  3771. wqes[0] = &l2kwqe;
  3772. l2kwqe.kwqe_op_flag = (L2_LAYER_CODE << KWQE_LAYER_SHIFT) |
  3773. (L2_KWQE_OPCODE_VALUE_FLUSH <<
  3774. KWQE_OPCODE_SHIFT) | 2;
  3775. dev->submit_kwqes(dev, wqes, 1);
  3776. }
  3777. static void cnic_set_bnx2_mac(struct cnic_dev *dev)
  3778. {
  3779. struct cnic_local *cp = dev->cnic_priv;
  3780. u32 val;
  3781. val = cp->func << 2;
  3782. cp->shmem_base = cnic_reg_rd_ind(dev, BNX2_SHM_HDR_ADDR_0 + val);
  3783. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3784. BNX2_PORT_HW_CFG_ISCSI_MAC_UPPER);
  3785. dev->mac_addr[0] = (u8) (val >> 8);
  3786. dev->mac_addr[1] = (u8) val;
  3787. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH4, val);
  3788. val = cnic_reg_rd_ind(dev, cp->shmem_base +
  3789. BNX2_PORT_HW_CFG_ISCSI_MAC_LOWER);
  3790. dev->mac_addr[2] = (u8) (val >> 24);
  3791. dev->mac_addr[3] = (u8) (val >> 16);
  3792. dev->mac_addr[4] = (u8) (val >> 8);
  3793. dev->mac_addr[5] = (u8) val;
  3794. CNIC_WR(dev, BNX2_EMAC_MAC_MATCH5, val);
  3795. val = 4 | BNX2_RPM_SORT_USER2_BC_EN;
  3796. if (CHIP_NUM(cp) != CHIP_NUM_5709)
  3797. val |= BNX2_RPM_SORT_USER2_PROM_VLAN;
  3798. CNIC_WR(dev, BNX2_RPM_SORT_USER2, 0x0);
  3799. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val);
  3800. CNIC_WR(dev, BNX2_RPM_SORT_USER2, val | BNX2_RPM_SORT_USER2_ENA);
  3801. }
  3802. static int cnic_start_bnx2_hw(struct cnic_dev *dev)
  3803. {
  3804. struct cnic_local *cp = dev->cnic_priv;
  3805. struct cnic_eth_dev *ethdev = cp->ethdev;
  3806. struct status_block *sblk = cp->status_blk.gen;
  3807. u32 val, kcq_cid_addr, kwq_cid_addr;
  3808. int err;
  3809. cnic_set_bnx2_mac(dev);
  3810. val = CNIC_RD(dev, BNX2_MQ_CONFIG);
  3811. val &= ~BNX2_MQ_CONFIG_KNL_BYP_BLK_SIZE;
  3812. if (BCM_PAGE_BITS > 12)
  3813. val |= (12 - 8) << 4;
  3814. else
  3815. val |= (BCM_PAGE_BITS - 8) << 4;
  3816. CNIC_WR(dev, BNX2_MQ_CONFIG, val);
  3817. CNIC_WR(dev, BNX2_HC_COMP_PROD_TRIP, (2 << 16) | 8);
  3818. CNIC_WR(dev, BNX2_HC_COM_TICKS, (64 << 16) | 220);
  3819. CNIC_WR(dev, BNX2_HC_CMD_TICKS, (64 << 16) | 220);
  3820. err = cnic_setup_5709_context(dev, 1);
  3821. if (err)
  3822. return err;
  3823. cnic_init_context(dev, KWQ_CID);
  3824. cnic_init_context(dev, KCQ_CID);
  3825. kwq_cid_addr = GET_CID_ADDR(KWQ_CID);
  3826. cp->kwq_io_addr = MB_GET_CID_ADDR(KWQ_CID) + L5_KRNLQ_HOST_QIDX;
  3827. cp->max_kwq_idx = MAX_KWQ_IDX;
  3828. cp->kwq_prod_idx = 0;
  3829. cp->kwq_con_idx = 0;
  3830. set_bit(CNIC_LCL_FL_KWQ_INIT, &cp->cnic_local_flags);
  3831. if (CHIP_NUM(cp) == CHIP_NUM_5706 || CHIP_NUM(cp) == CHIP_NUM_5708)
  3832. cp->kwq_con_idx_ptr = &sblk->status_rx_quick_consumer_index15;
  3833. else
  3834. cp->kwq_con_idx_ptr = &sblk->status_cmd_consumer_index;
  3835. /* Initialize the kernel work queue context. */
  3836. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3837. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3838. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_TYPE, val);
  3839. val = (BCM_PAGE_SIZE / sizeof(struct kwqe) - 1) << 16;
  3840. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3841. val = ((BCM_PAGE_SIZE / sizeof(struct kwqe)) << 16) | KWQ_PAGE_CNT;
  3842. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3843. val = (u32) ((u64) cp->kwq_info.pgtbl_map >> 32);
  3844. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3845. val = (u32) cp->kwq_info.pgtbl_map;
  3846. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3847. kcq_cid_addr = GET_CID_ADDR(KCQ_CID);
  3848. cp->kcq1.io_addr = MB_GET_CID_ADDR(KCQ_CID) + L5_KRNLQ_HOST_QIDX;
  3849. cp->kcq1.sw_prod_idx = 0;
  3850. cp->kcq1.hw_prod_idx_ptr =
  3851. (u16 *) &sblk->status_completion_producer_index;
  3852. cp->kcq1.status_idx_ptr = (u16 *) &sblk->status_idx;
  3853. /* Initialize the kernel complete queue context. */
  3854. val = KRNLQ_TYPE_TYPE_KRNLQ | KRNLQ_SIZE_TYPE_SIZE |
  3855. (BCM_PAGE_BITS - 8) | KRNLQ_FLAGS_QE_SELF_SEQ;
  3856. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_TYPE, val);
  3857. val = (BCM_PAGE_SIZE / sizeof(struct kcqe) - 1) << 16;
  3858. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_QE_SELF_SEQ_MAX, val);
  3859. val = ((BCM_PAGE_SIZE / sizeof(struct kcqe)) << 16) | KCQ_PAGE_CNT;
  3860. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_NPAGES, val);
  3861. val = (u32) ((u64) cp->kcq1.dma.pgtbl_map >> 32);
  3862. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_HI, val);
  3863. val = (u32) cp->kcq1.dma.pgtbl_map;
  3864. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_PGTBL_HADDR_LO, val);
  3865. cp->int_num = 0;
  3866. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX) {
  3867. struct status_block_msix *msblk = cp->status_blk.bnx2;
  3868. u32 sb_id = cp->status_blk_num;
  3869. u32 sb = BNX2_L2CTX_L5_STATUSB_NUM(sb_id);
  3870. cp->kcq1.hw_prod_idx_ptr =
  3871. (u16 *) &msblk->status_completion_producer_index;
  3872. cp->kcq1.status_idx_ptr = (u16 *) &msblk->status_idx;
  3873. cp->kwq_con_idx_ptr = (u16 *) &msblk->status_cmd_consumer_index;
  3874. cp->int_num = sb_id << BNX2_PCICFG_INT_ACK_CMD_INT_NUM_SHIFT;
  3875. cnic_ctx_wr(dev, kwq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3876. cnic_ctx_wr(dev, kcq_cid_addr, L5_KRNLQ_HOST_QIDX, sb);
  3877. }
  3878. /* Enable Commnad Scheduler notification when we write to the
  3879. * host producer index of the kernel contexts. */
  3880. CNIC_WR(dev, BNX2_MQ_KNL_CMD_MASK1, 2);
  3881. /* Enable Command Scheduler notification when we write to either
  3882. * the Send Queue or Receive Queue producer indexes of the kernel
  3883. * bypass contexts. */
  3884. CNIC_WR(dev, BNX2_MQ_KNL_BYP_CMD_MASK1, 7);
  3885. CNIC_WR(dev, BNX2_MQ_KNL_BYP_WRITE_MASK1, 7);
  3886. /* Notify COM when the driver post an application buffer. */
  3887. CNIC_WR(dev, BNX2_MQ_KNL_RX_V2P_MASK2, 0x2000);
  3888. /* Set the CP and COM doorbells. These two processors polls the
  3889. * doorbell for a non zero value before running. This must be done
  3890. * after setting up the kernel queue contexts. */
  3891. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 1);
  3892. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 1);
  3893. cnic_init_bnx2_tx_ring(dev);
  3894. cnic_init_bnx2_rx_ring(dev);
  3895. err = cnic_init_bnx2_irq(dev);
  3896. if (err) {
  3897. netdev_err(dev->netdev, "cnic_init_irq failed\n");
  3898. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  3899. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  3900. return err;
  3901. }
  3902. return 0;
  3903. }
  3904. static void cnic_setup_bnx2x_context(struct cnic_dev *dev)
  3905. {
  3906. struct cnic_local *cp = dev->cnic_priv;
  3907. struct cnic_eth_dev *ethdev = cp->ethdev;
  3908. u32 start_offset = ethdev->ctx_tbl_offset;
  3909. int i;
  3910. for (i = 0; i < cp->ctx_blks; i++) {
  3911. struct cnic_ctx *ctx = &cp->ctx_arr[i];
  3912. dma_addr_t map = ctx->mapping;
  3913. if (cp->ctx_align) {
  3914. unsigned long mask = cp->ctx_align - 1;
  3915. map = (map + mask) & ~mask;
  3916. }
  3917. cnic_ctx_tbl_wr(dev, start_offset + i, map);
  3918. }
  3919. }
  3920. static int cnic_init_bnx2x_irq(struct cnic_dev *dev)
  3921. {
  3922. struct cnic_local *cp = dev->cnic_priv;
  3923. struct cnic_eth_dev *ethdev = cp->ethdev;
  3924. int err = 0;
  3925. tasklet_init(&cp->cnic_irq_task, cnic_service_bnx2x_bh,
  3926. (unsigned long) dev);
  3927. if (ethdev->drv_state & CNIC_DRV_STATE_USING_MSIX)
  3928. err = cnic_request_irq(dev);
  3929. return err;
  3930. }
  3931. static inline void cnic_storm_memset_hc_disable(struct cnic_dev *dev,
  3932. u16 sb_id, u8 sb_index,
  3933. u8 disable)
  3934. {
  3935. u32 addr = BAR_CSTRORM_INTMEM +
  3936. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3937. offsetof(struct hc_status_block_data_e1x, index_data) +
  3938. sizeof(struct hc_index_data)*sb_index +
  3939. offsetof(struct hc_index_data, flags);
  3940. u16 flags = CNIC_RD16(dev, addr);
  3941. /* clear and set */
  3942. flags &= ~HC_INDEX_DATA_HC_ENABLED;
  3943. flags |= (((~disable) << HC_INDEX_DATA_HC_ENABLED_SHIFT) &
  3944. HC_INDEX_DATA_HC_ENABLED);
  3945. CNIC_WR16(dev, addr, flags);
  3946. }
  3947. static void cnic_enable_bnx2x_int(struct cnic_dev *dev)
  3948. {
  3949. struct cnic_local *cp = dev->cnic_priv;
  3950. u8 sb_id = cp->status_blk_num;
  3951. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  3952. CSTORM_STATUS_BLOCK_DATA_OFFSET(sb_id) +
  3953. offsetof(struct hc_status_block_data_e1x, index_data) +
  3954. sizeof(struct hc_index_data)*HC_INDEX_ISCSI_EQ_CONS +
  3955. offsetof(struct hc_index_data, timeout), 64 / 4);
  3956. cnic_storm_memset_hc_disable(dev, sb_id, HC_INDEX_ISCSI_EQ_CONS, 0);
  3957. }
  3958. static void cnic_disable_bnx2x_int_sync(struct cnic_dev *dev)
  3959. {
  3960. }
  3961. static void cnic_init_bnx2x_tx_ring(struct cnic_dev *dev,
  3962. struct client_init_ramrod_data *data)
  3963. {
  3964. struct cnic_local *cp = dev->cnic_priv;
  3965. struct cnic_uio_dev *udev = cp->udev;
  3966. union eth_tx_bd_types *txbd = (union eth_tx_bd_types *) udev->l2_ring;
  3967. dma_addr_t buf_map, ring_map = udev->l2_ring_map;
  3968. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  3969. int i;
  3970. u32 cli = cp->ethdev->iscsi_l2_client_id;
  3971. u32 val;
  3972. memset(txbd, 0, BCM_PAGE_SIZE);
  3973. buf_map = udev->l2_buf_map;
  3974. for (i = 0; i < MAX_TX_DESC_CNT; i += 3, txbd += 3) {
  3975. struct eth_tx_start_bd *start_bd = &txbd->start_bd;
  3976. struct eth_tx_bd *reg_bd = &((txbd + 2)->reg_bd);
  3977. start_bd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  3978. start_bd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  3979. reg_bd->addr_hi = start_bd->addr_hi;
  3980. reg_bd->addr_lo = start_bd->addr_lo + 0x10;
  3981. start_bd->nbytes = cpu_to_le16(0x10);
  3982. start_bd->nbd = cpu_to_le16(3);
  3983. start_bd->bd_flags.as_bitfield = ETH_TX_BD_FLAGS_START_BD;
  3984. start_bd->general_data = (UNICAST_ADDRESS <<
  3985. ETH_TX_START_BD_ETH_ADDR_TYPE_SHIFT);
  3986. start_bd->general_data |= (1 << ETH_TX_START_BD_HDR_NBDS_SHIFT);
  3987. }
  3988. val = (u64) ring_map >> 32;
  3989. txbd->next_bd.addr_hi = cpu_to_le32(val);
  3990. data->tx.tx_bd_page_base.hi = cpu_to_le32(val);
  3991. val = (u64) ring_map & 0xffffffff;
  3992. txbd->next_bd.addr_lo = cpu_to_le32(val);
  3993. data->tx.tx_bd_page_base.lo = cpu_to_le32(val);
  3994. /* Other ramrod params */
  3995. data->tx.tx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_CQ_CONS;
  3996. data->tx.tx_status_block_id = BNX2X_DEF_SB_ID;
  3997. /* reset xstorm per client statistics */
  3998. if (cli < MAX_STAT_COUNTER_ID) {
  3999. data->general.statistics_zero_flg = 1;
  4000. data->general.statistics_en_flg = 1;
  4001. data->general.statistics_counter_id = cli;
  4002. }
  4003. cp->tx_cons_ptr =
  4004. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_CQ_CONS];
  4005. }
  4006. static void cnic_init_bnx2x_rx_ring(struct cnic_dev *dev,
  4007. struct client_init_ramrod_data *data)
  4008. {
  4009. struct cnic_local *cp = dev->cnic_priv;
  4010. struct cnic_uio_dev *udev = cp->udev;
  4011. struct eth_rx_bd *rxbd = (struct eth_rx_bd *) (udev->l2_ring +
  4012. BCM_PAGE_SIZE);
  4013. struct eth_rx_cqe_next_page *rxcqe = (struct eth_rx_cqe_next_page *)
  4014. (udev->l2_ring + (2 * BCM_PAGE_SIZE));
  4015. struct host_sp_status_block *sb = cp->bnx2x_def_status_blk;
  4016. int i;
  4017. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4018. int cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4019. u32 val;
  4020. dma_addr_t ring_map = udev->l2_ring_map;
  4021. /* General data */
  4022. data->general.client_id = cli;
  4023. data->general.activate_flg = 1;
  4024. data->general.sp_client_id = cli;
  4025. data->general.mtu = cpu_to_le16(cp->l2_single_buf_size - 14);
  4026. data->general.func_id = cp->pfid;
  4027. for (i = 0; i < BNX2X_MAX_RX_DESC_CNT; i++, rxbd++) {
  4028. dma_addr_t buf_map;
  4029. int n = (i % cp->l2_rx_ring_size) + 1;
  4030. buf_map = udev->l2_buf_map + (n * cp->l2_single_buf_size);
  4031. rxbd->addr_hi = cpu_to_le32((u64) buf_map >> 32);
  4032. rxbd->addr_lo = cpu_to_le32(buf_map & 0xffffffff);
  4033. }
  4034. val = (u64) (ring_map + BCM_PAGE_SIZE) >> 32;
  4035. rxbd->addr_hi = cpu_to_le32(val);
  4036. data->rx.bd_page_base.hi = cpu_to_le32(val);
  4037. val = (u64) (ring_map + BCM_PAGE_SIZE) & 0xffffffff;
  4038. rxbd->addr_lo = cpu_to_le32(val);
  4039. data->rx.bd_page_base.lo = cpu_to_le32(val);
  4040. rxcqe += BNX2X_MAX_RCQ_DESC_CNT;
  4041. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) >> 32;
  4042. rxcqe->addr_hi = cpu_to_le32(val);
  4043. data->rx.cqe_page_base.hi = cpu_to_le32(val);
  4044. val = (u64) (ring_map + (2 * BCM_PAGE_SIZE)) & 0xffffffff;
  4045. rxcqe->addr_lo = cpu_to_le32(val);
  4046. data->rx.cqe_page_base.lo = cpu_to_le32(val);
  4047. /* Other ramrod params */
  4048. data->rx.client_qzone_id = cl_qzone_id;
  4049. data->rx.rx_sb_index_number = HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS;
  4050. data->rx.status_block_id = BNX2X_DEF_SB_ID;
  4051. data->rx.cache_line_alignment_log_size = L1_CACHE_SHIFT;
  4052. data->rx.max_bytes_on_bd = cpu_to_le16(cp->l2_single_buf_size);
  4053. data->rx.outer_vlan_removal_enable_flg = 1;
  4054. data->rx.silent_vlan_removal_flg = 1;
  4055. data->rx.silent_vlan_value = 0;
  4056. data->rx.silent_vlan_mask = 0xffff;
  4057. cp->rx_cons_ptr =
  4058. &sb->sp_sb.index_values[HC_SP_INDEX_ETH_ISCSI_RX_CQ_CONS];
  4059. cp->rx_cons = *cp->rx_cons_ptr;
  4060. }
  4061. static void cnic_init_bnx2x_kcq(struct cnic_dev *dev)
  4062. {
  4063. struct cnic_local *cp = dev->cnic_priv;
  4064. u32 pfid = cp->pfid;
  4065. cp->kcq1.io_addr = BAR_CSTRORM_INTMEM +
  4066. CSTORM_ISCSI_EQ_PROD_OFFSET(pfid, 0);
  4067. cp->kcq1.sw_prod_idx = 0;
  4068. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4069. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4070. cp->kcq1.hw_prod_idx_ptr =
  4071. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4072. cp->kcq1.status_idx_ptr =
  4073. &sb->sb.running_index[SM_RX_ID];
  4074. } else {
  4075. struct host_hc_status_block_e1x *sb = cp->status_blk.gen;
  4076. cp->kcq1.hw_prod_idx_ptr =
  4077. &sb->sb.index_values[HC_INDEX_ISCSI_EQ_CONS];
  4078. cp->kcq1.status_idx_ptr =
  4079. &sb->sb.running_index[SM_RX_ID];
  4080. }
  4081. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4082. struct host_hc_status_block_e2 *sb = cp->status_blk.gen;
  4083. cp->kcq2.io_addr = BAR_USTRORM_INTMEM +
  4084. USTORM_FCOE_EQ_PROD_OFFSET(pfid);
  4085. cp->kcq2.sw_prod_idx = 0;
  4086. cp->kcq2.hw_prod_idx_ptr =
  4087. &sb->sb.index_values[HC_INDEX_FCOE_EQ_CONS];
  4088. cp->kcq2.status_idx_ptr =
  4089. &sb->sb.running_index[SM_RX_ID];
  4090. }
  4091. }
  4092. static int cnic_start_bnx2x_hw(struct cnic_dev *dev)
  4093. {
  4094. struct cnic_local *cp = dev->cnic_priv;
  4095. struct cnic_eth_dev *ethdev = cp->ethdev;
  4096. int func = CNIC_FUNC(cp), ret;
  4097. u32 pfid;
  4098. dev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4099. cp->port_mode = CHIP_PORT_MODE_NONE;
  4100. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4101. u32 val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN_OVWR);
  4102. if (!(val & 1))
  4103. val = CNIC_RD(dev, MISC_REG_PORT4MODE_EN);
  4104. else
  4105. val = (val >> 1) & 1;
  4106. if (val) {
  4107. cp->port_mode = CHIP_4_PORT_MODE;
  4108. cp->pfid = func >> 1;
  4109. } else {
  4110. cp->port_mode = CHIP_2_PORT_MODE;
  4111. cp->pfid = func & 0x6;
  4112. }
  4113. } else {
  4114. cp->pfid = func;
  4115. }
  4116. pfid = cp->pfid;
  4117. ret = cnic_init_id_tbl(&cp->cid_tbl, MAX_ISCSI_TBL_SZ,
  4118. cp->iscsi_start_cid, 0);
  4119. if (ret)
  4120. return -ENOMEM;
  4121. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id)) {
  4122. ret = cnic_init_id_tbl(&cp->fcoe_cid_tbl, dev->max_fcoe_conn,
  4123. cp->fcoe_start_cid, 0);
  4124. if (ret)
  4125. return -ENOMEM;
  4126. }
  4127. cp->bnx2x_igu_sb_id = ethdev->irq_arr[0].status_blk_num2;
  4128. cnic_init_bnx2x_kcq(dev);
  4129. /* Only 1 EQ */
  4130. CNIC_WR16(dev, cp->kcq1.io_addr, MAX_KCQ_IDX);
  4131. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4132. CSTORM_ISCSI_EQ_CONS_OFFSET(pfid, 0), 0);
  4133. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4134. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0),
  4135. cp->kcq1.dma.pg_map_arr[1] & 0xffffffff);
  4136. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4137. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_OFFSET(pfid, 0) + 4,
  4138. (u64) cp->kcq1.dma.pg_map_arr[1] >> 32);
  4139. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4140. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0),
  4141. cp->kcq1.dma.pg_map_arr[0] & 0xffffffff);
  4142. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4143. CSTORM_ISCSI_EQ_NEXT_EQE_ADDR_OFFSET(pfid, 0) + 4,
  4144. (u64) cp->kcq1.dma.pg_map_arr[0] >> 32);
  4145. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4146. CSTORM_ISCSI_EQ_NEXT_PAGE_ADDR_VALID_OFFSET(pfid, 0), 1);
  4147. CNIC_WR16(dev, BAR_CSTRORM_INTMEM +
  4148. CSTORM_ISCSI_EQ_SB_NUM_OFFSET(pfid, 0), cp->status_blk_num);
  4149. CNIC_WR8(dev, BAR_CSTRORM_INTMEM +
  4150. CSTORM_ISCSI_EQ_SB_INDEX_OFFSET(pfid, 0),
  4151. HC_INDEX_ISCSI_EQ_CONS);
  4152. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4153. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid),
  4154. cp->gbl_buf_info.pg_map_arr[0] & 0xffffffff);
  4155. CNIC_WR(dev, BAR_USTRORM_INTMEM +
  4156. USTORM_ISCSI_GLOBAL_BUF_PHYS_ADDR_OFFSET(pfid) + 4,
  4157. (u64) cp->gbl_buf_info.pg_map_arr[0] >> 32);
  4158. CNIC_WR(dev, BAR_TSTRORM_INTMEM +
  4159. TSTORM_ISCSI_TCP_LOCAL_ADV_WND_OFFSET(pfid), DEF_RCV_BUF);
  4160. cnic_setup_bnx2x_context(dev);
  4161. ret = cnic_init_bnx2x_irq(dev);
  4162. if (ret)
  4163. return ret;
  4164. return 0;
  4165. }
  4166. static void cnic_init_rings(struct cnic_dev *dev)
  4167. {
  4168. struct cnic_local *cp = dev->cnic_priv;
  4169. struct cnic_uio_dev *udev = cp->udev;
  4170. if (test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4171. return;
  4172. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4173. cnic_init_bnx2_tx_ring(dev);
  4174. cnic_init_bnx2_rx_ring(dev);
  4175. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4176. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4177. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4178. u32 cid = cp->ethdev->iscsi_l2_cid;
  4179. u32 cl_qzone_id;
  4180. struct client_init_ramrod_data *data;
  4181. union l5cm_specific_data l5_data;
  4182. struct ustorm_eth_rx_producers rx_prods = {0};
  4183. u32 off, i, *cid_ptr;
  4184. rx_prods.bd_prod = 0;
  4185. rx_prods.cqe_prod = BNX2X_MAX_RCQ_DESC_CNT;
  4186. barrier();
  4187. cl_qzone_id = BNX2X_CL_QZONE_ID(cp, cli);
  4188. off = BAR_USTRORM_INTMEM +
  4189. (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) ?
  4190. USTORM_RX_PRODS_E2_OFFSET(cl_qzone_id) :
  4191. USTORM_RX_PRODS_E1X_OFFSET(CNIC_PORT(cp), cli));
  4192. for (i = 0; i < sizeof(struct ustorm_eth_rx_producers) / 4; i++)
  4193. CNIC_WR(dev, off + i * 4, ((u32 *) &rx_prods)[i]);
  4194. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4195. data = udev->l2_buf;
  4196. cid_ptr = udev->l2_buf + 12;
  4197. memset(data, 0, sizeof(*data));
  4198. cnic_init_bnx2x_tx_ring(dev, data);
  4199. cnic_init_bnx2x_rx_ring(dev, data);
  4200. l5_data.phy_address.lo = udev->l2_buf_map & 0xffffffff;
  4201. l5_data.phy_address.hi = (u64) udev->l2_buf_map >> 32;
  4202. set_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4203. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_CLIENT_SETUP,
  4204. cid, ETH_CONNECTION_TYPE, &l5_data);
  4205. i = 0;
  4206. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4207. ++i < 10)
  4208. msleep(1);
  4209. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4210. netdev_err(dev->netdev,
  4211. "iSCSI CLIENT_SETUP did not complete\n");
  4212. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4213. cnic_ring_ctl(dev, cid, cli, 1);
  4214. *cid_ptr = cid;
  4215. }
  4216. }
  4217. static void cnic_shutdown_rings(struct cnic_dev *dev)
  4218. {
  4219. struct cnic_local *cp = dev->cnic_priv;
  4220. struct cnic_uio_dev *udev = cp->udev;
  4221. void *rx_ring;
  4222. if (!test_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags))
  4223. return;
  4224. if (test_bit(CNIC_F_BNX2_CLASS, &dev->flags)) {
  4225. cnic_shutdown_bnx2_rx_ring(dev);
  4226. } else if (test_bit(CNIC_F_BNX2X_CLASS, &dev->flags)) {
  4227. u32 cli = cp->ethdev->iscsi_l2_client_id;
  4228. u32 cid = cp->ethdev->iscsi_l2_cid;
  4229. union l5cm_specific_data l5_data;
  4230. int i;
  4231. cnic_ring_ctl(dev, cid, cli, 0);
  4232. set_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags);
  4233. l5_data.phy_address.lo = cli;
  4234. l5_data.phy_address.hi = 0;
  4235. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_ETH_HALT,
  4236. cid, ETH_CONNECTION_TYPE, &l5_data);
  4237. i = 0;
  4238. while (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags) &&
  4239. ++i < 10)
  4240. msleep(1);
  4241. if (test_bit(CNIC_LCL_FL_L2_WAIT, &cp->cnic_local_flags))
  4242. netdev_err(dev->netdev,
  4243. "iSCSI CLIENT_HALT did not complete\n");
  4244. cnic_spq_completion(dev, DRV_CTL_RET_L2_SPQ_CREDIT_CMD, 1);
  4245. memset(&l5_data, 0, sizeof(l5_data));
  4246. cnic_submit_kwqe_16(dev, RAMROD_CMD_ID_COMMON_CFC_DEL,
  4247. cid, NONE_CONNECTION_TYPE, &l5_data);
  4248. msleep(10);
  4249. }
  4250. clear_bit(CNIC_LCL_FL_RINGS_INITED, &cp->cnic_local_flags);
  4251. rx_ring = udev->l2_ring + BCM_PAGE_SIZE;
  4252. memset(rx_ring, 0, BCM_PAGE_SIZE);
  4253. }
  4254. static int cnic_register_netdev(struct cnic_dev *dev)
  4255. {
  4256. struct cnic_local *cp = dev->cnic_priv;
  4257. struct cnic_eth_dev *ethdev = cp->ethdev;
  4258. int err;
  4259. if (!ethdev)
  4260. return -ENODEV;
  4261. if (ethdev->drv_state & CNIC_DRV_STATE_REGD)
  4262. return 0;
  4263. err = ethdev->drv_register_cnic(dev->netdev, cp->cnic_ops, dev);
  4264. if (err)
  4265. netdev_err(dev->netdev, "register_cnic failed\n");
  4266. return err;
  4267. }
  4268. static void cnic_unregister_netdev(struct cnic_dev *dev)
  4269. {
  4270. struct cnic_local *cp = dev->cnic_priv;
  4271. struct cnic_eth_dev *ethdev = cp->ethdev;
  4272. if (!ethdev)
  4273. return;
  4274. ethdev->drv_unregister_cnic(dev->netdev);
  4275. }
  4276. static int cnic_start_hw(struct cnic_dev *dev)
  4277. {
  4278. struct cnic_local *cp = dev->cnic_priv;
  4279. struct cnic_eth_dev *ethdev = cp->ethdev;
  4280. int err;
  4281. if (test_bit(CNIC_F_CNIC_UP, &dev->flags))
  4282. return -EALREADY;
  4283. dev->regview = ethdev->io_base;
  4284. pci_dev_get(dev->pcidev);
  4285. cp->func = PCI_FUNC(dev->pcidev->devfn);
  4286. cp->status_blk.gen = ethdev->irq_arr[0].status_blk;
  4287. cp->status_blk_num = ethdev->irq_arr[0].status_blk_num;
  4288. err = cp->alloc_resc(dev);
  4289. if (err) {
  4290. netdev_err(dev->netdev, "allocate resource failure\n");
  4291. goto err1;
  4292. }
  4293. err = cp->start_hw(dev);
  4294. if (err)
  4295. goto err1;
  4296. err = cnic_cm_open(dev);
  4297. if (err)
  4298. goto err1;
  4299. set_bit(CNIC_F_CNIC_UP, &dev->flags);
  4300. cp->enable_int(dev);
  4301. return 0;
  4302. err1:
  4303. cp->free_resc(dev);
  4304. pci_dev_put(dev->pcidev);
  4305. return err;
  4306. }
  4307. static void cnic_stop_bnx2_hw(struct cnic_dev *dev)
  4308. {
  4309. cnic_disable_bnx2_int_sync(dev);
  4310. cnic_reg_wr_ind(dev, BNX2_CP_SCRATCH + 0x20, 0);
  4311. cnic_reg_wr_ind(dev, BNX2_COM_SCRATCH + 0x20, 0);
  4312. cnic_init_context(dev, KWQ_CID);
  4313. cnic_init_context(dev, KCQ_CID);
  4314. cnic_setup_5709_context(dev, 0);
  4315. cnic_free_irq(dev);
  4316. cnic_free_resc(dev);
  4317. }
  4318. static void cnic_stop_bnx2x_hw(struct cnic_dev *dev)
  4319. {
  4320. struct cnic_local *cp = dev->cnic_priv;
  4321. cnic_free_irq(dev);
  4322. *cp->kcq1.hw_prod_idx_ptr = 0;
  4323. CNIC_WR(dev, BAR_CSTRORM_INTMEM +
  4324. CSTORM_ISCSI_EQ_CONS_OFFSET(cp->pfid, 0), 0);
  4325. CNIC_WR16(dev, cp->kcq1.io_addr, 0);
  4326. cnic_free_resc(dev);
  4327. }
  4328. static void cnic_stop_hw(struct cnic_dev *dev)
  4329. {
  4330. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4331. struct cnic_local *cp = dev->cnic_priv;
  4332. int i = 0;
  4333. /* Need to wait for the ring shutdown event to complete
  4334. * before clearing the CNIC_UP flag.
  4335. */
  4336. while (cp->udev->uio_dev != -1 && i < 15) {
  4337. msleep(100);
  4338. i++;
  4339. }
  4340. cnic_shutdown_rings(dev);
  4341. clear_bit(CNIC_F_CNIC_UP, &dev->flags);
  4342. RCU_INIT_POINTER(cp->ulp_ops[CNIC_ULP_L4], NULL);
  4343. synchronize_rcu();
  4344. cnic_cm_shutdown(dev);
  4345. cp->stop_hw(dev);
  4346. pci_dev_put(dev->pcidev);
  4347. }
  4348. }
  4349. static void cnic_free_dev(struct cnic_dev *dev)
  4350. {
  4351. int i = 0;
  4352. while ((atomic_read(&dev->ref_count) != 0) && i < 10) {
  4353. msleep(100);
  4354. i++;
  4355. }
  4356. if (atomic_read(&dev->ref_count) != 0)
  4357. netdev_err(dev->netdev, "Failed waiting for ref count to go to zero\n");
  4358. netdev_info(dev->netdev, "Removed CNIC device\n");
  4359. dev_put(dev->netdev);
  4360. kfree(dev);
  4361. }
  4362. static struct cnic_dev *cnic_alloc_dev(struct net_device *dev,
  4363. struct pci_dev *pdev)
  4364. {
  4365. struct cnic_dev *cdev;
  4366. struct cnic_local *cp;
  4367. int alloc_size;
  4368. alloc_size = sizeof(struct cnic_dev) + sizeof(struct cnic_local);
  4369. cdev = kzalloc(alloc_size , GFP_KERNEL);
  4370. if (cdev == NULL) {
  4371. netdev_err(dev, "allocate dev struct failure\n");
  4372. return NULL;
  4373. }
  4374. cdev->netdev = dev;
  4375. cdev->cnic_priv = (char *)cdev + sizeof(struct cnic_dev);
  4376. cdev->register_device = cnic_register_device;
  4377. cdev->unregister_device = cnic_unregister_device;
  4378. cdev->iscsi_nl_msg_recv = cnic_iscsi_nl_msg_recv;
  4379. cp = cdev->cnic_priv;
  4380. cp->dev = cdev;
  4381. cp->l2_single_buf_size = 0x400;
  4382. cp->l2_rx_ring_size = 3;
  4383. spin_lock_init(&cp->cnic_ulp_lock);
  4384. netdev_info(dev, "Added CNIC device\n");
  4385. return cdev;
  4386. }
  4387. static struct cnic_dev *init_bnx2_cnic(struct net_device *dev)
  4388. {
  4389. struct pci_dev *pdev;
  4390. struct cnic_dev *cdev;
  4391. struct cnic_local *cp;
  4392. struct cnic_eth_dev *ethdev = NULL;
  4393. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4394. probe = symbol_get(bnx2_cnic_probe);
  4395. if (probe) {
  4396. ethdev = (*probe)(dev);
  4397. symbol_put(bnx2_cnic_probe);
  4398. }
  4399. if (!ethdev)
  4400. return NULL;
  4401. pdev = ethdev->pdev;
  4402. if (!pdev)
  4403. return NULL;
  4404. dev_hold(dev);
  4405. pci_dev_get(pdev);
  4406. if ((pdev->device == PCI_DEVICE_ID_NX2_5709 ||
  4407. pdev->device == PCI_DEVICE_ID_NX2_5709S) &&
  4408. (pdev->revision < 0x10)) {
  4409. pci_dev_put(pdev);
  4410. goto cnic_err;
  4411. }
  4412. pci_dev_put(pdev);
  4413. cdev = cnic_alloc_dev(dev, pdev);
  4414. if (cdev == NULL)
  4415. goto cnic_err;
  4416. set_bit(CNIC_F_BNX2_CLASS, &cdev->flags);
  4417. cdev->submit_kwqes = cnic_submit_bnx2_kwqes;
  4418. cp = cdev->cnic_priv;
  4419. cp->ethdev = ethdev;
  4420. cdev->pcidev = pdev;
  4421. cp->chip_id = ethdev->chip_id;
  4422. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4423. cp->cnic_ops = &cnic_bnx2_ops;
  4424. cp->start_hw = cnic_start_bnx2_hw;
  4425. cp->stop_hw = cnic_stop_bnx2_hw;
  4426. cp->setup_pgtbl = cnic_setup_page_tbl;
  4427. cp->alloc_resc = cnic_alloc_bnx2_resc;
  4428. cp->free_resc = cnic_free_resc;
  4429. cp->start_cm = cnic_cm_init_bnx2_hw;
  4430. cp->stop_cm = cnic_cm_stop_bnx2_hw;
  4431. cp->enable_int = cnic_enable_bnx2_int;
  4432. cp->disable_int_sync = cnic_disable_bnx2_int_sync;
  4433. cp->close_conn = cnic_close_bnx2_conn;
  4434. return cdev;
  4435. cnic_err:
  4436. dev_put(dev);
  4437. return NULL;
  4438. }
  4439. static struct cnic_dev *init_bnx2x_cnic(struct net_device *dev)
  4440. {
  4441. struct pci_dev *pdev;
  4442. struct cnic_dev *cdev;
  4443. struct cnic_local *cp;
  4444. struct cnic_eth_dev *ethdev = NULL;
  4445. struct cnic_eth_dev *(*probe)(struct net_device *) = NULL;
  4446. probe = symbol_get(bnx2x_cnic_probe);
  4447. if (probe) {
  4448. ethdev = (*probe)(dev);
  4449. symbol_put(bnx2x_cnic_probe);
  4450. }
  4451. if (!ethdev)
  4452. return NULL;
  4453. pdev = ethdev->pdev;
  4454. if (!pdev)
  4455. return NULL;
  4456. dev_hold(dev);
  4457. cdev = cnic_alloc_dev(dev, pdev);
  4458. if (cdev == NULL) {
  4459. dev_put(dev);
  4460. return NULL;
  4461. }
  4462. set_bit(CNIC_F_BNX2X_CLASS, &cdev->flags);
  4463. cdev->submit_kwqes = cnic_submit_bnx2x_kwqes;
  4464. cp = cdev->cnic_priv;
  4465. cp->ethdev = ethdev;
  4466. cdev->pcidev = pdev;
  4467. cp->chip_id = ethdev->chip_id;
  4468. cdev->stats_addr = ethdev->addr_drv_info_to_mcp;
  4469. if (!(ethdev->drv_state & CNIC_DRV_STATE_NO_ISCSI))
  4470. cdev->max_iscsi_conn = ethdev->max_iscsi_conn;
  4471. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id) &&
  4472. !(ethdev->drv_state & CNIC_DRV_STATE_NO_FCOE))
  4473. cdev->max_fcoe_conn = ethdev->max_fcoe_conn;
  4474. if (cdev->max_fcoe_conn > BNX2X_FCOE_NUM_CONNECTIONS)
  4475. cdev->max_fcoe_conn = BNX2X_FCOE_NUM_CONNECTIONS;
  4476. memcpy(cdev->mac_addr, ethdev->iscsi_mac, 6);
  4477. cp->cnic_ops = &cnic_bnx2x_ops;
  4478. cp->start_hw = cnic_start_bnx2x_hw;
  4479. cp->stop_hw = cnic_stop_bnx2x_hw;
  4480. cp->setup_pgtbl = cnic_setup_page_tbl_le;
  4481. cp->alloc_resc = cnic_alloc_bnx2x_resc;
  4482. cp->free_resc = cnic_free_resc;
  4483. cp->start_cm = cnic_cm_init_bnx2x_hw;
  4484. cp->stop_cm = cnic_cm_stop_bnx2x_hw;
  4485. cp->enable_int = cnic_enable_bnx2x_int;
  4486. cp->disable_int_sync = cnic_disable_bnx2x_int_sync;
  4487. if (BNX2X_CHIP_IS_E2_PLUS(cp->chip_id))
  4488. cp->ack_int = cnic_ack_bnx2x_e2_msix;
  4489. else
  4490. cp->ack_int = cnic_ack_bnx2x_msix;
  4491. cp->close_conn = cnic_close_bnx2x_conn;
  4492. return cdev;
  4493. }
  4494. static struct cnic_dev *is_cnic_dev(struct net_device *dev)
  4495. {
  4496. struct ethtool_drvinfo drvinfo;
  4497. struct cnic_dev *cdev = NULL;
  4498. if (dev->ethtool_ops && dev->ethtool_ops->get_drvinfo) {
  4499. memset(&drvinfo, 0, sizeof(drvinfo));
  4500. dev->ethtool_ops->get_drvinfo(dev, &drvinfo);
  4501. if (!strcmp(drvinfo.driver, "bnx2"))
  4502. cdev = init_bnx2_cnic(dev);
  4503. if (!strcmp(drvinfo.driver, "bnx2x"))
  4504. cdev = init_bnx2x_cnic(dev);
  4505. if (cdev) {
  4506. write_lock(&cnic_dev_lock);
  4507. list_add(&cdev->list, &cnic_dev_list);
  4508. write_unlock(&cnic_dev_lock);
  4509. }
  4510. }
  4511. return cdev;
  4512. }
  4513. static void cnic_rcv_netevent(struct cnic_local *cp, unsigned long event,
  4514. u16 vlan_id)
  4515. {
  4516. int if_type;
  4517. rcu_read_lock();
  4518. for (if_type = 0; if_type < MAX_CNIC_ULP_TYPE; if_type++) {
  4519. struct cnic_ulp_ops *ulp_ops;
  4520. void *ctx;
  4521. ulp_ops = rcu_dereference(cp->ulp_ops[if_type]);
  4522. if (!ulp_ops || !ulp_ops->indicate_netevent)
  4523. continue;
  4524. ctx = cp->ulp_handle[if_type];
  4525. ulp_ops->indicate_netevent(ctx, event, vlan_id);
  4526. }
  4527. rcu_read_unlock();
  4528. }
  4529. /**
  4530. * netdev event handler
  4531. */
  4532. static int cnic_netdev_event(struct notifier_block *this, unsigned long event,
  4533. void *ptr)
  4534. {
  4535. struct net_device *netdev = ptr;
  4536. struct cnic_dev *dev;
  4537. int new_dev = 0;
  4538. dev = cnic_from_netdev(netdev);
  4539. if (!dev && (event == NETDEV_REGISTER || netif_running(netdev))) {
  4540. /* Check for the hot-plug device */
  4541. dev = is_cnic_dev(netdev);
  4542. if (dev) {
  4543. new_dev = 1;
  4544. cnic_hold(dev);
  4545. }
  4546. }
  4547. if (dev) {
  4548. struct cnic_local *cp = dev->cnic_priv;
  4549. if (new_dev)
  4550. cnic_ulp_init(dev);
  4551. else if (event == NETDEV_UNREGISTER)
  4552. cnic_ulp_exit(dev);
  4553. if (event == NETDEV_UP || (new_dev && netif_running(netdev))) {
  4554. if (cnic_register_netdev(dev) != 0) {
  4555. cnic_put(dev);
  4556. goto done;
  4557. }
  4558. if (!cnic_start_hw(dev))
  4559. cnic_ulp_start(dev);
  4560. }
  4561. cnic_rcv_netevent(cp, event, 0);
  4562. if (event == NETDEV_GOING_DOWN) {
  4563. cnic_ulp_stop(dev);
  4564. cnic_stop_hw(dev);
  4565. cnic_unregister_netdev(dev);
  4566. } else if (event == NETDEV_UNREGISTER) {
  4567. write_lock(&cnic_dev_lock);
  4568. list_del_init(&dev->list);
  4569. write_unlock(&cnic_dev_lock);
  4570. cnic_put(dev);
  4571. cnic_free_dev(dev);
  4572. goto done;
  4573. }
  4574. cnic_put(dev);
  4575. } else {
  4576. struct net_device *realdev;
  4577. u16 vid;
  4578. vid = cnic_get_vlan(netdev, &realdev);
  4579. if (realdev) {
  4580. dev = cnic_from_netdev(realdev);
  4581. if (dev) {
  4582. vid |= VLAN_TAG_PRESENT;
  4583. cnic_rcv_netevent(dev->cnic_priv, event, vid);
  4584. cnic_put(dev);
  4585. }
  4586. }
  4587. }
  4588. done:
  4589. return NOTIFY_DONE;
  4590. }
  4591. static struct notifier_block cnic_netdev_notifier = {
  4592. .notifier_call = cnic_netdev_event
  4593. };
  4594. static void cnic_release(void)
  4595. {
  4596. struct cnic_dev *dev;
  4597. struct cnic_uio_dev *udev;
  4598. while (!list_empty(&cnic_dev_list)) {
  4599. dev = list_entry(cnic_dev_list.next, struct cnic_dev, list);
  4600. if (test_bit(CNIC_F_CNIC_UP, &dev->flags)) {
  4601. cnic_ulp_stop(dev);
  4602. cnic_stop_hw(dev);
  4603. }
  4604. cnic_ulp_exit(dev);
  4605. cnic_unregister_netdev(dev);
  4606. list_del_init(&dev->list);
  4607. cnic_free_dev(dev);
  4608. }
  4609. while (!list_empty(&cnic_udev_list)) {
  4610. udev = list_entry(cnic_udev_list.next, struct cnic_uio_dev,
  4611. list);
  4612. cnic_free_uio(udev);
  4613. }
  4614. }
  4615. static int __init cnic_init(void)
  4616. {
  4617. int rc = 0;
  4618. pr_info("%s", version);
  4619. rc = register_netdevice_notifier(&cnic_netdev_notifier);
  4620. if (rc) {
  4621. cnic_release();
  4622. return rc;
  4623. }
  4624. cnic_wq = create_singlethread_workqueue("cnic_wq");
  4625. if (!cnic_wq) {
  4626. cnic_release();
  4627. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4628. return -ENOMEM;
  4629. }
  4630. return 0;
  4631. }
  4632. static void __exit cnic_exit(void)
  4633. {
  4634. unregister_netdevice_notifier(&cnic_netdev_notifier);
  4635. cnic_release();
  4636. destroy_workqueue(cnic_wq);
  4637. }
  4638. module_init(cnic_init);
  4639. module_exit(cnic_exit);