tegra30-cardhu.dtsi 13 KB

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  1. #include "tegra30.dtsi"
  2. /**
  3. * This file contains common DT entry for all fab version of Cardhu.
  4. * There is multiple fab version of Cardhu starting from A01 to A07.
  5. * Cardhu fab version A01 and A03 are not supported. Cardhu fab version
  6. * A02 will have different sets of GPIOs for fixed regulator compare to
  7. * Cardhu fab version A04. The Cardhu fab version A05, A06, A07 are
  8. * compatible with fab version A04. Based on Cardhu fab version, the
  9. * related dts file need to be chosen like for Cardhu fab version A02,
  10. * use tegra30-cardhu-a02.dts, Cardhu fab version A04 and later, use
  11. * tegra30-cardhu-a04.dts.
  12. * The identification of board is done in two ways, by looking the sticker
  13. * on PCB and by reading board id eeprom.
  14. * The stciker will have number like 600-81291-1000-002 C.3. In this 4th
  15. * number is the fab version like here it is 002 and hence fab version A02.
  16. * The (downstream internal) U-Boot of Cardhu display the board-id as
  17. * follows:
  18. * BoardID: 0C5B, SKU: 0A01, Fab: 02, Rev: 45.00
  19. * In this Fab version is 02 i.e. A02.
  20. * The BoardID I2C eeprom is interfaced through i2c5 (pwr_i2c address 0x56).
  21. * The location 0x8 of this eeprom contains the Fab version. It is 1 byte
  22. * wide.
  23. */
  24. / {
  25. model = "NVIDIA Tegra30 Cardhu evaluation board";
  26. compatible = "nvidia,cardhu", "nvidia,tegra30";
  27. memory {
  28. reg = <0x80000000 0x40000000>;
  29. };
  30. pinmux {
  31. pinctrl-names = "default";
  32. pinctrl-0 = <&state_default>;
  33. state_default: pinmux {
  34. sdmmc1_clk_pz0 {
  35. nvidia,pins = "sdmmc1_clk_pz0";
  36. nvidia,function = "sdmmc1";
  37. nvidia,pull = <0>;
  38. nvidia,tristate = <0>;
  39. };
  40. sdmmc1_cmd_pz1 {
  41. nvidia,pins = "sdmmc1_cmd_pz1",
  42. "sdmmc1_dat0_py7",
  43. "sdmmc1_dat1_py6",
  44. "sdmmc1_dat2_py5",
  45. "sdmmc1_dat3_py4";
  46. nvidia,function = "sdmmc1";
  47. nvidia,pull = <2>;
  48. nvidia,tristate = <0>;
  49. };
  50. sdmmc3_clk_pa6 {
  51. nvidia,pins = "sdmmc3_clk_pa6";
  52. nvidia,function = "sdmmc3";
  53. nvidia,pull = <0>;
  54. nvidia,tristate = <0>;
  55. };
  56. sdmmc3_cmd_pa7 {
  57. nvidia,pins = "sdmmc3_cmd_pa7",
  58. "sdmmc3_dat0_pb7",
  59. "sdmmc3_dat1_pb6",
  60. "sdmmc3_dat2_pb5",
  61. "sdmmc3_dat3_pb4";
  62. nvidia,function = "sdmmc3";
  63. nvidia,pull = <2>;
  64. nvidia,tristate = <0>;
  65. };
  66. sdmmc4_clk_pcc4 {
  67. nvidia,pins = "sdmmc4_clk_pcc4",
  68. "sdmmc4_rst_n_pcc3";
  69. nvidia,function = "sdmmc4";
  70. nvidia,pull = <0>;
  71. nvidia,tristate = <0>;
  72. };
  73. sdmmc4_dat0_paa0 {
  74. nvidia,pins = "sdmmc4_dat0_paa0",
  75. "sdmmc4_dat1_paa1",
  76. "sdmmc4_dat2_paa2",
  77. "sdmmc4_dat3_paa3",
  78. "sdmmc4_dat4_paa4",
  79. "sdmmc4_dat5_paa5",
  80. "sdmmc4_dat6_paa6",
  81. "sdmmc4_dat7_paa7";
  82. nvidia,function = "sdmmc4";
  83. nvidia,pull = <2>;
  84. nvidia,tristate = <0>;
  85. };
  86. dap2_fs_pa2 {
  87. nvidia,pins = "dap2_fs_pa2",
  88. "dap2_sclk_pa3",
  89. "dap2_din_pa4",
  90. "dap2_dout_pa5";
  91. nvidia,function = "i2s1";
  92. nvidia,pull = <0>;
  93. nvidia,tristate = <0>;
  94. };
  95. sdio3 {
  96. nvidia,pins = "drive_sdio3";
  97. nvidia,high-speed-mode = <0>;
  98. nvidia,schmitt = <0>;
  99. nvidia,pull-down-strength = <46>;
  100. nvidia,pull-up-strength = <42>;
  101. nvidia,slew-rate-rising = <1>;
  102. nvidia,slew-rate-falling = <1>;
  103. };
  104. uart3_txd_pw6 {
  105. nvidia,pins = "uart3_txd_pw6",
  106. "uart3_cts_n_pa1",
  107. "uart3_rts_n_pc0",
  108. "uart3_rxd_pw7";
  109. nvidia,function = "uartc";
  110. nvidia,pull = <0>;
  111. nvidia,tristate = <0>;
  112. };
  113. };
  114. };
  115. serial@70006000 {
  116. status = "okay";
  117. };
  118. serial@70006200 {
  119. compatible = "nvidia,tegra30-hsuart";
  120. status = "okay";
  121. };
  122. i2c@7000c000 {
  123. status = "okay";
  124. clock-frequency = <100000>;
  125. };
  126. i2c@7000c400 {
  127. status = "okay";
  128. clock-frequency = <100000>;
  129. };
  130. i2c@7000c500 {
  131. status = "okay";
  132. clock-frequency = <100000>;
  133. /* ALS and Proximity sensor */
  134. isl29028@44 {
  135. compatible = "isil,isl29028";
  136. reg = <0x44>;
  137. interrupt-parent = <&gpio>;
  138. interrupts = <TEGRA_GPIO(L, 0) IRQ_TYPE_LEVEL_HIGH>;
  139. };
  140. };
  141. i2c@7000c700 {
  142. status = "okay";
  143. clock-frequency = <100000>;
  144. };
  145. i2c@7000d000 {
  146. status = "okay";
  147. clock-frequency = <100000>;
  148. wm8903: wm8903@1a {
  149. compatible = "wlf,wm8903";
  150. reg = <0x1a>;
  151. interrupt-parent = <&gpio>;
  152. interrupts = <TEGRA_GPIO(W, 3) IRQ_TYPE_LEVEL_HIGH>;
  153. gpio-controller;
  154. #gpio-cells = <2>;
  155. micdet-cfg = <0>;
  156. micdet-delay = <100>;
  157. gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
  158. };
  159. pmic: tps65911@2d {
  160. compatible = "ti,tps65911";
  161. reg = <0x2d>;
  162. interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
  163. #interrupt-cells = <2>;
  164. interrupt-controller;
  165. ti,system-power-controller;
  166. #gpio-cells = <2>;
  167. gpio-controller;
  168. vcc1-supply = <&vdd_ac_bat_reg>;
  169. vcc2-supply = <&vdd_ac_bat_reg>;
  170. vcc3-supply = <&vio_reg>;
  171. vcc4-supply = <&vdd_5v0_reg>;
  172. vcc5-supply = <&vdd_ac_bat_reg>;
  173. vcc6-supply = <&vdd2_reg>;
  174. vcc7-supply = <&vdd_ac_bat_reg>;
  175. vccio-supply = <&vdd_ac_bat_reg>;
  176. regulators {
  177. vdd1_reg: vdd1 {
  178. regulator-name = "vddio_ddr_1v2";
  179. regulator-min-microvolt = <1200000>;
  180. regulator-max-microvolt = <1200000>;
  181. regulator-always-on;
  182. };
  183. vdd2_reg: vdd2 {
  184. regulator-name = "vdd_1v5_gen";
  185. regulator-min-microvolt = <1500000>;
  186. regulator-max-microvolt = <1500000>;
  187. regulator-always-on;
  188. };
  189. vddctrl_reg: vddctrl {
  190. regulator-name = "vdd_cpu,vdd_sys";
  191. regulator-min-microvolt = <1000000>;
  192. regulator-max-microvolt = <1000000>;
  193. regulator-always-on;
  194. };
  195. vio_reg: vio {
  196. regulator-name = "vdd_1v8_gen";
  197. regulator-min-microvolt = <1800000>;
  198. regulator-max-microvolt = <1800000>;
  199. regulator-always-on;
  200. };
  201. ldo1_reg: ldo1 {
  202. regulator-name = "vdd_pexa,vdd_pexb";
  203. regulator-min-microvolt = <1050000>;
  204. regulator-max-microvolt = <1050000>;
  205. };
  206. ldo2_reg: ldo2 {
  207. regulator-name = "vdd_sata,avdd_plle";
  208. regulator-min-microvolt = <1050000>;
  209. regulator-max-microvolt = <1050000>;
  210. };
  211. /* LDO3 is not connected to anything */
  212. ldo4_reg: ldo4 {
  213. regulator-name = "vdd_rtc";
  214. regulator-min-microvolt = <1200000>;
  215. regulator-max-microvolt = <1200000>;
  216. regulator-always-on;
  217. };
  218. ldo5_reg: ldo5 {
  219. regulator-name = "vddio_sdmmc,avdd_vdac";
  220. regulator-min-microvolt = <3300000>;
  221. regulator-max-microvolt = <3300000>;
  222. regulator-always-on;
  223. };
  224. ldo6_reg: ldo6 {
  225. regulator-name = "avdd_dsi_csi,pwrdet_mipi";
  226. regulator-min-microvolt = <1200000>;
  227. regulator-max-microvolt = <1200000>;
  228. };
  229. ldo7_reg: ldo7 {
  230. regulator-name = "vdd_pllm,x,u,a_p_c_s";
  231. regulator-min-microvolt = <1200000>;
  232. regulator-max-microvolt = <1200000>;
  233. regulator-always-on;
  234. };
  235. ldo8_reg: ldo8 {
  236. regulator-name = "vdd_ddr_hs";
  237. regulator-min-microvolt = <1000000>;
  238. regulator-max-microvolt = <1000000>;
  239. regulator-always-on;
  240. };
  241. };
  242. };
  243. nct1008 {
  244. compatible = "onnn,nct1008";
  245. reg = <0x4c>;
  246. interrupt-parent = <&gpio>;
  247. interrupts = <TEGRA_GPIO(CC, 2) IRQ_TYPE_LEVEL_LOW>;
  248. };
  249. tps62361 {
  250. compatible = "ti,tps62361";
  251. reg = <0x60>;
  252. regulator-name = "tps62361-vout";
  253. regulator-min-microvolt = <500000>;
  254. regulator-max-microvolt = <1500000>;
  255. regulator-boot-on;
  256. regulator-always-on;
  257. ti,vsel0-state-high;
  258. ti,vsel1-state-high;
  259. };
  260. };
  261. spi@7000da00 {
  262. status = "okay";
  263. spi-max-frequency = <25000000>;
  264. spi-flash@1 {
  265. compatible = "winbond,w25q32";
  266. reg = <1>;
  267. spi-max-frequency = <20000000>;
  268. };
  269. };
  270. ahub {
  271. i2s@70080400 {
  272. status = "okay";
  273. };
  274. };
  275. pmc {
  276. status = "okay";
  277. nvidia,invert-interrupt;
  278. nvidia,suspend-mode = <2>;
  279. nvidia,cpu-pwr-good-time = <2000>;
  280. nvidia,cpu-pwr-off-time = <200>;
  281. nvidia,core-pwr-good-time = <3845 3845>;
  282. nvidia,core-pwr-off-time = <0>;
  283. nvidia,core-power-req-active-high;
  284. nvidia,sys-clock-req-active-high;
  285. };
  286. sdhci@78000000 {
  287. status = "okay";
  288. cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
  289. wp-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
  290. power-gpios = <&gpio TEGRA_GPIO(D, 7) GPIO_ACTIVE_HIGH>;
  291. bus-width = <4>;
  292. };
  293. sdhci@78000600 {
  294. status = "okay";
  295. bus-width = <8>;
  296. non-removable;
  297. };
  298. clocks {
  299. compatible = "simple-bus";
  300. #address-cells = <1>;
  301. #size-cells = <0>;
  302. clk32k_in: clock {
  303. compatible = "fixed-clock";
  304. reg=<0>;
  305. #clock-cells = <0>;
  306. clock-frequency = <32768>;
  307. };
  308. };
  309. regulators {
  310. compatible = "simple-bus";
  311. #address-cells = <1>;
  312. #size-cells = <0>;
  313. vdd_ac_bat_reg: regulator@0 {
  314. compatible = "regulator-fixed";
  315. reg = <0>;
  316. regulator-name = "vdd_ac_bat";
  317. regulator-min-microvolt = <5000000>;
  318. regulator-max-microvolt = <5000000>;
  319. regulator-always-on;
  320. };
  321. cam_1v8_reg: regulator@1 {
  322. compatible = "regulator-fixed";
  323. reg = <1>;
  324. regulator-name = "cam_1v8";
  325. regulator-min-microvolt = <1800000>;
  326. regulator-max-microvolt = <1800000>;
  327. enable-active-high;
  328. gpio = <&gpio TEGRA_GPIO(BB, 4) GPIO_ACTIVE_HIGH>;
  329. vin-supply = <&vio_reg>;
  330. };
  331. cp_5v_reg: regulator@2 {
  332. compatible = "regulator-fixed";
  333. reg = <2>;
  334. regulator-name = "cp_5v";
  335. regulator-min-microvolt = <5000000>;
  336. regulator-max-microvolt = <5000000>;
  337. regulator-boot-on;
  338. regulator-always-on;
  339. enable-active-high;
  340. gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
  341. };
  342. emmc_3v3_reg: regulator@3 {
  343. compatible = "regulator-fixed";
  344. reg = <3>;
  345. regulator-name = "emmc_3v3";
  346. regulator-min-microvolt = <3300000>;
  347. regulator-max-microvolt = <3300000>;
  348. regulator-always-on;
  349. regulator-boot-on;
  350. enable-active-high;
  351. gpio = <&gpio TEGRA_GPIO(D, 1) GPIO_ACTIVE_HIGH>;
  352. vin-supply = <&sys_3v3_reg>;
  353. };
  354. modem_3v3_reg: regulator@4 {
  355. compatible = "regulator-fixed";
  356. reg = <4>;
  357. regulator-name = "modem_3v3";
  358. regulator-min-microvolt = <3300000>;
  359. regulator-max-microvolt = <3300000>;
  360. enable-active-high;
  361. gpio = <&gpio TEGRA_GPIO(D, 6) GPIO_ACTIVE_HIGH>;
  362. };
  363. pex_hvdd_3v3_reg: regulator@5 {
  364. compatible = "regulator-fixed";
  365. reg = <5>;
  366. regulator-name = "pex_hvdd_3v3";
  367. regulator-min-microvolt = <3300000>;
  368. regulator-max-microvolt = <3300000>;
  369. enable-active-high;
  370. gpio = <&gpio TEGRA_GPIO(L, 7) GPIO_ACTIVE_HIGH>;
  371. vin-supply = <&sys_3v3_reg>;
  372. };
  373. vdd_cam1_ldo_reg: regulator@6 {
  374. compatible = "regulator-fixed";
  375. reg = <6>;
  376. regulator-name = "vdd_cam1_ldo";
  377. regulator-min-microvolt = <2800000>;
  378. regulator-max-microvolt = <2800000>;
  379. enable-active-high;
  380. gpio = <&gpio TEGRA_GPIO(R, 6) GPIO_ACTIVE_HIGH>;
  381. vin-supply = <&sys_3v3_reg>;
  382. };
  383. vdd_cam2_ldo_reg: regulator@7 {
  384. compatible = "regulator-fixed";
  385. reg = <7>;
  386. regulator-name = "vdd_cam2_ldo";
  387. regulator-min-microvolt = <2800000>;
  388. regulator-max-microvolt = <2800000>;
  389. enable-active-high;
  390. gpio = <&gpio TEGRA_GPIO(R, 7) GPIO_ACTIVE_HIGH>;
  391. vin-supply = <&sys_3v3_reg>;
  392. };
  393. vdd_cam3_ldo_reg: regulator@8 {
  394. compatible = "regulator-fixed";
  395. reg = <8>;
  396. regulator-name = "vdd_cam3_ldo";
  397. regulator-min-microvolt = <3300000>;
  398. regulator-max-microvolt = <3300000>;
  399. enable-active-high;
  400. gpio = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_HIGH>;
  401. vin-supply = <&sys_3v3_reg>;
  402. };
  403. vdd_com_reg: regulator@9 {
  404. compatible = "regulator-fixed";
  405. reg = <9>;
  406. regulator-name = "vdd_com";
  407. regulator-min-microvolt = <3300000>;
  408. regulator-max-microvolt = <3300000>;
  409. regulator-always-on;
  410. regulator-boot-on;
  411. enable-active-high;
  412. gpio = <&gpio TEGRA_GPIO(D, 0) GPIO_ACTIVE_HIGH>;
  413. vin-supply = <&sys_3v3_reg>;
  414. };
  415. vdd_fuse_3v3_reg: regulator@10 {
  416. compatible = "regulator-fixed";
  417. reg = <10>;
  418. regulator-name = "vdd_fuse_3v3";
  419. regulator-min-microvolt = <3300000>;
  420. regulator-max-microvolt = <3300000>;
  421. enable-active-high;
  422. gpio = <&gpio TEGRA_GPIO(L, 6) GPIO_ACTIVE_HIGH>;
  423. vin-supply = <&sys_3v3_reg>;
  424. };
  425. vdd_pnl1_reg: regulator@11 {
  426. compatible = "regulator-fixed";
  427. reg = <11>;
  428. regulator-name = "vdd_pnl1";
  429. regulator-min-microvolt = <3300000>;
  430. regulator-max-microvolt = <3300000>;
  431. regulator-always-on;
  432. regulator-boot-on;
  433. enable-active-high;
  434. gpio = <&gpio TEGRA_GPIO(L, 4) GPIO_ACTIVE_HIGH>;
  435. vin-supply = <&sys_3v3_reg>;
  436. };
  437. vdd_vid_reg: regulator@12 {
  438. compatible = "regulator-fixed";
  439. reg = <12>;
  440. regulator-name = "vddio_vid";
  441. regulator-min-microvolt = <5000000>;
  442. regulator-max-microvolt = <5000000>;
  443. enable-active-high;
  444. gpio = <&gpio TEGRA_GPIO(T, 0) GPIO_ACTIVE_HIGH>;
  445. gpio-open-drain;
  446. vin-supply = <&vdd_5v0_reg>;
  447. };
  448. };
  449. sound {
  450. compatible = "nvidia,tegra-audio-wm8903-cardhu",
  451. "nvidia,tegra-audio-wm8903";
  452. nvidia,model = "NVIDIA Tegra Cardhu";
  453. nvidia,audio-routing =
  454. "Headphone Jack", "HPOUTR",
  455. "Headphone Jack", "HPOUTL",
  456. "Int Spk", "ROP",
  457. "Int Spk", "RON",
  458. "Int Spk", "LOP",
  459. "Int Spk", "LON",
  460. "Mic Jack", "MICBIAS",
  461. "IN1L", "Mic Jack";
  462. nvidia,i2s-controller = <&tegra_i2s1>;
  463. nvidia,audio-codec = <&wm8903>;
  464. nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
  465. nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
  466. GPIO_ACTIVE_HIGH>;
  467. clocks = <&tegra_car TEGRA30_CLK_PLL_A>,
  468. <&tegra_car TEGRA30_CLK_PLL_A_OUT0>,
  469. <&tegra_car TEGRA30_CLK_EXTERN1>;
  470. clock-names = "pll_a", "pll_a_out0", "mclk";
  471. };
  472. };