fsi.c 48 KB

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  1. /*
  2. * Fifo-attached Serial Interface (FSI) support for SH7724
  3. *
  4. * Copyright (C) 2009 Renesas Solutions Corp.
  5. * Kuninori Morimoto <morimoto.kuninori@renesas.com>
  6. *
  7. * Based on ssi.c
  8. * Copyright (c) 2007 Manuel Lauss <mano@roarinelk.homelinux.net>
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/delay.h>
  15. #include <linux/dma-mapping.h>
  16. #include <linux/pm_runtime.h>
  17. #include <linux/io.h>
  18. #include <linux/of.h>
  19. #include <linux/of_device.h>
  20. #include <linux/scatterlist.h>
  21. #include <linux/sh_dma.h>
  22. #include <linux/slab.h>
  23. #include <linux/module.h>
  24. #include <linux/workqueue.h>
  25. #include <sound/soc.h>
  26. #include <sound/pcm_params.h>
  27. #include <sound/sh_fsi.h>
  28. /* PortA/PortB register */
  29. #define REG_DO_FMT 0x0000
  30. #define REG_DOFF_CTL 0x0004
  31. #define REG_DOFF_ST 0x0008
  32. #define REG_DI_FMT 0x000C
  33. #define REG_DIFF_CTL 0x0010
  34. #define REG_DIFF_ST 0x0014
  35. #define REG_CKG1 0x0018
  36. #define REG_CKG2 0x001C
  37. #define REG_DIDT 0x0020
  38. #define REG_DODT 0x0024
  39. #define REG_MUTE_ST 0x0028
  40. #define REG_OUT_DMAC 0x002C
  41. #define REG_OUT_SEL 0x0030
  42. #define REG_IN_DMAC 0x0038
  43. /* master register */
  44. #define MST_CLK_RST 0x0210
  45. #define MST_SOFT_RST 0x0214
  46. #define MST_FIFO_SZ 0x0218
  47. /* core register (depend on FSI version) */
  48. #define A_MST_CTLR 0x0180
  49. #define B_MST_CTLR 0x01A0
  50. #define CPU_INT_ST 0x01F4
  51. #define CPU_IEMSK 0x01F8
  52. #define CPU_IMSK 0x01FC
  53. #define INT_ST 0x0200
  54. #define IEMSK 0x0204
  55. #define IMSK 0x0208
  56. /* DO_FMT */
  57. /* DI_FMT */
  58. #define CR_BWS_MASK (0x3 << 20) /* FSI2 */
  59. #define CR_BWS_24 (0x0 << 20) /* FSI2 */
  60. #define CR_BWS_16 (0x1 << 20) /* FSI2 */
  61. #define CR_BWS_20 (0x2 << 20) /* FSI2 */
  62. #define CR_DTMD_PCM (0x0 << 8) /* FSI2 */
  63. #define CR_DTMD_SPDIF_PCM (0x1 << 8) /* FSI2 */
  64. #define CR_DTMD_SPDIF_STREAM (0x2 << 8) /* FSI2 */
  65. #define CR_MONO (0x0 << 4)
  66. #define CR_MONO_D (0x1 << 4)
  67. #define CR_PCM (0x2 << 4)
  68. #define CR_I2S (0x3 << 4)
  69. #define CR_TDM (0x4 << 4)
  70. #define CR_TDM_D (0x5 << 4)
  71. /* OUT_DMAC */
  72. /* IN_DMAC */
  73. #define VDMD_MASK (0x3 << 4)
  74. #define VDMD_FRONT (0x0 << 4) /* Package in front */
  75. #define VDMD_BACK (0x1 << 4) /* Package in back */
  76. #define VDMD_STREAM (0x2 << 4) /* Stream mode(16bit * 2) */
  77. #define DMA_ON (0x1 << 0)
  78. /* DOFF_CTL */
  79. /* DIFF_CTL */
  80. #define IRQ_HALF 0x00100000
  81. #define FIFO_CLR 0x00000001
  82. /* DOFF_ST */
  83. #define ERR_OVER 0x00000010
  84. #define ERR_UNDER 0x00000001
  85. #define ST_ERR (ERR_OVER | ERR_UNDER)
  86. /* CKG1 */
  87. #define ACKMD_MASK 0x00007000
  88. #define BPFMD_MASK 0x00000700
  89. #define DIMD (1 << 4)
  90. #define DOMD (1 << 0)
  91. /* A/B MST_CTLR */
  92. #define BP (1 << 4) /* Fix the signal of Biphase output */
  93. #define SE (1 << 0) /* Fix the master clock */
  94. /* CLK_RST */
  95. #define CRB (1 << 4)
  96. #define CRA (1 << 0)
  97. /* IO SHIFT / MACRO */
  98. #define BI_SHIFT 12
  99. #define BO_SHIFT 8
  100. #define AI_SHIFT 4
  101. #define AO_SHIFT 0
  102. #define AB_IO(param, shift) (param << shift)
  103. /* SOFT_RST */
  104. #define PBSR (1 << 12) /* Port B Software Reset */
  105. #define PASR (1 << 8) /* Port A Software Reset */
  106. #define IR (1 << 4) /* Interrupt Reset */
  107. #define FSISR (1 << 0) /* Software Reset */
  108. /* OUT_SEL (FSI2) */
  109. #define DMMD (1 << 4) /* SPDIF output timing 0: Biphase only */
  110. /* 1: Biphase and serial */
  111. /* FIFO_SZ */
  112. #define FIFO_SZ_MASK 0x7
  113. #define FSI_RATES SNDRV_PCM_RATE_8000_96000
  114. #define FSI_FMTS (SNDRV_PCM_FMTBIT_S24_LE | SNDRV_PCM_FMTBIT_S16_LE)
  115. /*
  116. * bus options
  117. *
  118. * 0x000000BA
  119. *
  120. * A : sample widtht 16bit setting
  121. * B : sample widtht 24bit setting
  122. */
  123. #define SHIFT_16DATA 0
  124. #define SHIFT_24DATA 4
  125. #define PACKAGE_24BITBUS_BACK 0
  126. #define PACKAGE_24BITBUS_FRONT 1
  127. #define PACKAGE_16BITBUS_STREAM 2
  128. #define BUSOP_SET(s, a) ((a) << SHIFT_ ## s ## DATA)
  129. #define BUSOP_GET(s, a) (((a) >> SHIFT_ ## s ## DATA) & 0xF)
  130. /*
  131. * FSI driver use below type name for variable
  132. *
  133. * xxx_num : number of data
  134. * xxx_pos : position of data
  135. * xxx_capa : capacity of data
  136. */
  137. /*
  138. * period/frame/sample image
  139. *
  140. * ex) PCM (2ch)
  141. *
  142. * period pos period pos
  143. * [n] [n + 1]
  144. * |<-------------------- period--------------------->|
  145. * ==|============================================ ... =|==
  146. * | |
  147. * ||<----- frame ----->|<------ frame ----->| ... |
  148. * |+--------------------+--------------------+- ... |
  149. * ||[ sample ][ sample ]|[ sample ][ sample ]| ... |
  150. * |+--------------------+--------------------+- ... |
  151. * ==|============================================ ... =|==
  152. */
  153. /*
  154. * FSI FIFO image
  155. *
  156. * | |
  157. * | |
  158. * | [ sample ] |
  159. * | [ sample ] |
  160. * | [ sample ] |
  161. * | [ sample ] |
  162. * --> go to codecs
  163. */
  164. /*
  165. * FSI clock
  166. *
  167. * FSIxCLK [CPG] (ick) -------> |
  168. * |-> FSI_DIV (div)-> FSI2
  169. * FSIxCK [external] (xck) ---> |
  170. */
  171. /*
  172. * struct
  173. */
  174. struct fsi_stream_handler;
  175. struct fsi_stream {
  176. /*
  177. * these are initialized by fsi_stream_init()
  178. */
  179. struct snd_pcm_substream *substream;
  180. int fifo_sample_capa; /* sample capacity of FSI FIFO */
  181. int buff_sample_capa; /* sample capacity of ALSA buffer */
  182. int buff_sample_pos; /* sample position of ALSA buffer */
  183. int period_samples; /* sample number / 1 period */
  184. int period_pos; /* current period position */
  185. int sample_width; /* sample width */
  186. int uerr_num;
  187. int oerr_num;
  188. /*
  189. * bus options
  190. */
  191. u32 bus_option;
  192. /*
  193. * thse are initialized by fsi_handler_init()
  194. */
  195. struct fsi_stream_handler *handler;
  196. struct fsi_priv *priv;
  197. /*
  198. * these are for DMAEngine
  199. */
  200. struct dma_chan *chan;
  201. struct sh_dmae_slave slave; /* see fsi_handler_init() */
  202. struct work_struct work;
  203. dma_addr_t dma;
  204. };
  205. struct fsi_clk {
  206. /* see [FSI clock] */
  207. struct clk *own;
  208. struct clk *xck;
  209. struct clk *ick;
  210. struct clk *div;
  211. int (*set_rate)(struct device *dev,
  212. struct fsi_priv *fsi);
  213. unsigned long rate;
  214. unsigned int count;
  215. };
  216. struct fsi_priv {
  217. void __iomem *base;
  218. struct fsi_master *master;
  219. struct fsi_stream playback;
  220. struct fsi_stream capture;
  221. struct fsi_clk clock;
  222. u32 fmt;
  223. int chan_num:16;
  224. int clk_master:1;
  225. int clk_cpg:1;
  226. int spdif:1;
  227. int enable_stream:1;
  228. int bit_clk_inv:1;
  229. int lr_clk_inv:1;
  230. };
  231. struct fsi_stream_handler {
  232. int (*init)(struct fsi_priv *fsi, struct fsi_stream *io);
  233. int (*quit)(struct fsi_priv *fsi, struct fsi_stream *io);
  234. int (*probe)(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev);
  235. int (*transfer)(struct fsi_priv *fsi, struct fsi_stream *io);
  236. int (*remove)(struct fsi_priv *fsi, struct fsi_stream *io);
  237. int (*start_stop)(struct fsi_priv *fsi, struct fsi_stream *io,
  238. int enable);
  239. };
  240. #define fsi_stream_handler_call(io, func, args...) \
  241. (!(io) ? -ENODEV : \
  242. !((io)->handler->func) ? 0 : \
  243. (io)->handler->func(args))
  244. struct fsi_core {
  245. int ver;
  246. u32 int_st;
  247. u32 iemsk;
  248. u32 imsk;
  249. u32 a_mclk;
  250. u32 b_mclk;
  251. };
  252. struct fsi_master {
  253. void __iomem *base;
  254. struct fsi_priv fsia;
  255. struct fsi_priv fsib;
  256. const struct fsi_core *core;
  257. spinlock_t lock;
  258. };
  259. static int fsi_stream_is_play(struct fsi_priv *fsi, struct fsi_stream *io);
  260. /*
  261. * basic read write function
  262. */
  263. static void __fsi_reg_write(u32 __iomem *reg, u32 data)
  264. {
  265. /* valid data area is 24bit */
  266. data &= 0x00ffffff;
  267. __raw_writel(data, reg);
  268. }
  269. static u32 __fsi_reg_read(u32 __iomem *reg)
  270. {
  271. return __raw_readl(reg);
  272. }
  273. static void __fsi_reg_mask_set(u32 __iomem *reg, u32 mask, u32 data)
  274. {
  275. u32 val = __fsi_reg_read(reg);
  276. val &= ~mask;
  277. val |= data & mask;
  278. __fsi_reg_write(reg, val);
  279. }
  280. #define fsi_reg_write(p, r, d)\
  281. __fsi_reg_write((p->base + REG_##r), d)
  282. #define fsi_reg_read(p, r)\
  283. __fsi_reg_read((p->base + REG_##r))
  284. #define fsi_reg_mask_set(p, r, m, d)\
  285. __fsi_reg_mask_set((p->base + REG_##r), m, d)
  286. #define fsi_master_read(p, r) _fsi_master_read(p, MST_##r)
  287. #define fsi_core_read(p, r) _fsi_master_read(p, p->core->r)
  288. static u32 _fsi_master_read(struct fsi_master *master, u32 reg)
  289. {
  290. u32 ret;
  291. unsigned long flags;
  292. spin_lock_irqsave(&master->lock, flags);
  293. ret = __fsi_reg_read(master->base + reg);
  294. spin_unlock_irqrestore(&master->lock, flags);
  295. return ret;
  296. }
  297. #define fsi_master_mask_set(p, r, m, d) _fsi_master_mask_set(p, MST_##r, m, d)
  298. #define fsi_core_mask_set(p, r, m, d) _fsi_master_mask_set(p, p->core->r, m, d)
  299. static void _fsi_master_mask_set(struct fsi_master *master,
  300. u32 reg, u32 mask, u32 data)
  301. {
  302. unsigned long flags;
  303. spin_lock_irqsave(&master->lock, flags);
  304. __fsi_reg_mask_set(master->base + reg, mask, data);
  305. spin_unlock_irqrestore(&master->lock, flags);
  306. }
  307. /*
  308. * basic function
  309. */
  310. static int fsi_version(struct fsi_master *master)
  311. {
  312. return master->core->ver;
  313. }
  314. static struct fsi_master *fsi_get_master(struct fsi_priv *fsi)
  315. {
  316. return fsi->master;
  317. }
  318. static int fsi_is_clk_master(struct fsi_priv *fsi)
  319. {
  320. return fsi->clk_master;
  321. }
  322. static int fsi_is_port_a(struct fsi_priv *fsi)
  323. {
  324. return fsi->master->base == fsi->base;
  325. }
  326. static int fsi_is_spdif(struct fsi_priv *fsi)
  327. {
  328. return fsi->spdif;
  329. }
  330. static int fsi_is_enable_stream(struct fsi_priv *fsi)
  331. {
  332. return fsi->enable_stream;
  333. }
  334. static int fsi_is_play(struct snd_pcm_substream *substream)
  335. {
  336. return substream->stream == SNDRV_PCM_STREAM_PLAYBACK;
  337. }
  338. static struct snd_soc_dai *fsi_get_dai(struct snd_pcm_substream *substream)
  339. {
  340. struct snd_soc_pcm_runtime *rtd = substream->private_data;
  341. return rtd->cpu_dai;
  342. }
  343. static struct fsi_priv *fsi_get_priv_frm_dai(struct snd_soc_dai *dai)
  344. {
  345. struct fsi_master *master = snd_soc_dai_get_drvdata(dai);
  346. if (dai->id == 0)
  347. return &master->fsia;
  348. else
  349. return &master->fsib;
  350. }
  351. static struct fsi_priv *fsi_get_priv(struct snd_pcm_substream *substream)
  352. {
  353. return fsi_get_priv_frm_dai(fsi_get_dai(substream));
  354. }
  355. static u32 fsi_get_port_shift(struct fsi_priv *fsi, struct fsi_stream *io)
  356. {
  357. int is_play = fsi_stream_is_play(fsi, io);
  358. int is_porta = fsi_is_port_a(fsi);
  359. u32 shift;
  360. if (is_porta)
  361. shift = is_play ? AO_SHIFT : AI_SHIFT;
  362. else
  363. shift = is_play ? BO_SHIFT : BI_SHIFT;
  364. return shift;
  365. }
  366. static int fsi_frame2sample(struct fsi_priv *fsi, int frames)
  367. {
  368. return frames * fsi->chan_num;
  369. }
  370. static int fsi_sample2frame(struct fsi_priv *fsi, int samples)
  371. {
  372. return samples / fsi->chan_num;
  373. }
  374. static int fsi_get_current_fifo_samples(struct fsi_priv *fsi,
  375. struct fsi_stream *io)
  376. {
  377. int is_play = fsi_stream_is_play(fsi, io);
  378. u32 status;
  379. int frames;
  380. status = is_play ?
  381. fsi_reg_read(fsi, DOFF_ST) :
  382. fsi_reg_read(fsi, DIFF_ST);
  383. frames = 0x1ff & (status >> 8);
  384. return fsi_frame2sample(fsi, frames);
  385. }
  386. static void fsi_count_fifo_err(struct fsi_priv *fsi)
  387. {
  388. u32 ostatus = fsi_reg_read(fsi, DOFF_ST);
  389. u32 istatus = fsi_reg_read(fsi, DIFF_ST);
  390. if (ostatus & ERR_OVER)
  391. fsi->playback.oerr_num++;
  392. if (ostatus & ERR_UNDER)
  393. fsi->playback.uerr_num++;
  394. if (istatus & ERR_OVER)
  395. fsi->capture.oerr_num++;
  396. if (istatus & ERR_UNDER)
  397. fsi->capture.uerr_num++;
  398. fsi_reg_write(fsi, DOFF_ST, 0);
  399. fsi_reg_write(fsi, DIFF_ST, 0);
  400. }
  401. /*
  402. * fsi_stream_xx() function
  403. */
  404. static inline int fsi_stream_is_play(struct fsi_priv *fsi,
  405. struct fsi_stream *io)
  406. {
  407. return &fsi->playback == io;
  408. }
  409. static inline struct fsi_stream *fsi_stream_get(struct fsi_priv *fsi,
  410. struct snd_pcm_substream *substream)
  411. {
  412. return fsi_is_play(substream) ? &fsi->playback : &fsi->capture;
  413. }
  414. static int fsi_stream_is_working(struct fsi_priv *fsi,
  415. struct fsi_stream *io)
  416. {
  417. struct fsi_master *master = fsi_get_master(fsi);
  418. unsigned long flags;
  419. int ret;
  420. spin_lock_irqsave(&master->lock, flags);
  421. ret = !!(io->substream && io->substream->runtime);
  422. spin_unlock_irqrestore(&master->lock, flags);
  423. return ret;
  424. }
  425. static struct fsi_priv *fsi_stream_to_priv(struct fsi_stream *io)
  426. {
  427. return io->priv;
  428. }
  429. static void fsi_stream_init(struct fsi_priv *fsi,
  430. struct fsi_stream *io,
  431. struct snd_pcm_substream *substream)
  432. {
  433. struct snd_pcm_runtime *runtime = substream->runtime;
  434. struct fsi_master *master = fsi_get_master(fsi);
  435. unsigned long flags;
  436. spin_lock_irqsave(&master->lock, flags);
  437. io->substream = substream;
  438. io->buff_sample_capa = fsi_frame2sample(fsi, runtime->buffer_size);
  439. io->buff_sample_pos = 0;
  440. io->period_samples = fsi_frame2sample(fsi, runtime->period_size);
  441. io->period_pos = 0;
  442. io->sample_width = samples_to_bytes(runtime, 1);
  443. io->bus_option = 0;
  444. io->oerr_num = -1; /* ignore 1st err */
  445. io->uerr_num = -1; /* ignore 1st err */
  446. fsi_stream_handler_call(io, init, fsi, io);
  447. spin_unlock_irqrestore(&master->lock, flags);
  448. }
  449. static void fsi_stream_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  450. {
  451. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  452. struct fsi_master *master = fsi_get_master(fsi);
  453. unsigned long flags;
  454. spin_lock_irqsave(&master->lock, flags);
  455. if (io->oerr_num > 0)
  456. dev_err(dai->dev, "over_run = %d\n", io->oerr_num);
  457. if (io->uerr_num > 0)
  458. dev_err(dai->dev, "under_run = %d\n", io->uerr_num);
  459. fsi_stream_handler_call(io, quit, fsi, io);
  460. io->substream = NULL;
  461. io->buff_sample_capa = 0;
  462. io->buff_sample_pos = 0;
  463. io->period_samples = 0;
  464. io->period_pos = 0;
  465. io->sample_width = 0;
  466. io->bus_option = 0;
  467. io->oerr_num = 0;
  468. io->uerr_num = 0;
  469. spin_unlock_irqrestore(&master->lock, flags);
  470. }
  471. static int fsi_stream_transfer(struct fsi_stream *io)
  472. {
  473. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  474. if (!fsi)
  475. return -EIO;
  476. return fsi_stream_handler_call(io, transfer, fsi, io);
  477. }
  478. #define fsi_stream_start(fsi, io)\
  479. fsi_stream_handler_call(io, start_stop, fsi, io, 1)
  480. #define fsi_stream_stop(fsi, io)\
  481. fsi_stream_handler_call(io, start_stop, fsi, io, 0)
  482. static int fsi_stream_probe(struct fsi_priv *fsi, struct device *dev)
  483. {
  484. struct fsi_stream *io;
  485. int ret1, ret2;
  486. io = &fsi->playback;
  487. ret1 = fsi_stream_handler_call(io, probe, fsi, io, dev);
  488. io = &fsi->capture;
  489. ret2 = fsi_stream_handler_call(io, probe, fsi, io, dev);
  490. if (ret1 < 0)
  491. return ret1;
  492. if (ret2 < 0)
  493. return ret2;
  494. return 0;
  495. }
  496. static int fsi_stream_remove(struct fsi_priv *fsi)
  497. {
  498. struct fsi_stream *io;
  499. int ret1, ret2;
  500. io = &fsi->playback;
  501. ret1 = fsi_stream_handler_call(io, remove, fsi, io);
  502. io = &fsi->capture;
  503. ret2 = fsi_stream_handler_call(io, remove, fsi, io);
  504. if (ret1 < 0)
  505. return ret1;
  506. if (ret2 < 0)
  507. return ret2;
  508. return 0;
  509. }
  510. /*
  511. * format/bus/dma setting
  512. */
  513. static void fsi_format_bus_setup(struct fsi_priv *fsi, struct fsi_stream *io,
  514. u32 bus, struct device *dev)
  515. {
  516. struct fsi_master *master = fsi_get_master(fsi);
  517. int is_play = fsi_stream_is_play(fsi, io);
  518. u32 fmt = fsi->fmt;
  519. if (fsi_version(master) >= 2) {
  520. u32 dma = 0;
  521. /*
  522. * FSI2 needs DMA/Bus setting
  523. */
  524. switch (bus) {
  525. case PACKAGE_24BITBUS_FRONT:
  526. fmt |= CR_BWS_24;
  527. dma |= VDMD_FRONT;
  528. dev_dbg(dev, "24bit bus / package in front\n");
  529. break;
  530. case PACKAGE_16BITBUS_STREAM:
  531. fmt |= CR_BWS_16;
  532. dma |= VDMD_STREAM;
  533. dev_dbg(dev, "16bit bus / stream mode\n");
  534. break;
  535. case PACKAGE_24BITBUS_BACK:
  536. default:
  537. fmt |= CR_BWS_24;
  538. dma |= VDMD_BACK;
  539. dev_dbg(dev, "24bit bus / package in back\n");
  540. break;
  541. }
  542. if (is_play)
  543. fsi_reg_write(fsi, OUT_DMAC, dma);
  544. else
  545. fsi_reg_write(fsi, IN_DMAC, dma);
  546. }
  547. if (is_play)
  548. fsi_reg_write(fsi, DO_FMT, fmt);
  549. else
  550. fsi_reg_write(fsi, DI_FMT, fmt);
  551. }
  552. /*
  553. * irq function
  554. */
  555. static void fsi_irq_enable(struct fsi_priv *fsi, struct fsi_stream *io)
  556. {
  557. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  558. struct fsi_master *master = fsi_get_master(fsi);
  559. fsi_core_mask_set(master, imsk, data, data);
  560. fsi_core_mask_set(master, iemsk, data, data);
  561. }
  562. static void fsi_irq_disable(struct fsi_priv *fsi, struct fsi_stream *io)
  563. {
  564. u32 data = AB_IO(1, fsi_get_port_shift(fsi, io));
  565. struct fsi_master *master = fsi_get_master(fsi);
  566. fsi_core_mask_set(master, imsk, data, 0);
  567. fsi_core_mask_set(master, iemsk, data, 0);
  568. }
  569. static u32 fsi_irq_get_status(struct fsi_master *master)
  570. {
  571. return fsi_core_read(master, int_st);
  572. }
  573. static void fsi_irq_clear_status(struct fsi_priv *fsi)
  574. {
  575. u32 data = 0;
  576. struct fsi_master *master = fsi_get_master(fsi);
  577. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->playback));
  578. data |= AB_IO(1, fsi_get_port_shift(fsi, &fsi->capture));
  579. /* clear interrupt factor */
  580. fsi_core_mask_set(master, int_st, data, 0);
  581. }
  582. /*
  583. * SPDIF master clock function
  584. *
  585. * These functions are used later FSI2
  586. */
  587. static void fsi_spdif_clk_ctrl(struct fsi_priv *fsi, int enable)
  588. {
  589. struct fsi_master *master = fsi_get_master(fsi);
  590. u32 mask, val;
  591. mask = BP | SE;
  592. val = enable ? mask : 0;
  593. fsi_is_port_a(fsi) ?
  594. fsi_core_mask_set(master, a_mclk, mask, val) :
  595. fsi_core_mask_set(master, b_mclk, mask, val);
  596. }
  597. /*
  598. * clock function
  599. */
  600. static int fsi_clk_init(struct device *dev,
  601. struct fsi_priv *fsi,
  602. int xck,
  603. int ick,
  604. int div,
  605. int (*set_rate)(struct device *dev,
  606. struct fsi_priv *fsi))
  607. {
  608. struct fsi_clk *clock = &fsi->clock;
  609. int is_porta = fsi_is_port_a(fsi);
  610. clock->xck = NULL;
  611. clock->ick = NULL;
  612. clock->div = NULL;
  613. clock->rate = 0;
  614. clock->count = 0;
  615. clock->set_rate = set_rate;
  616. clock->own = devm_clk_get(dev, NULL);
  617. if (IS_ERR(clock->own))
  618. return -EINVAL;
  619. /* external clock */
  620. if (xck) {
  621. clock->xck = devm_clk_get(dev, is_porta ? "xcka" : "xckb");
  622. if (IS_ERR(clock->xck)) {
  623. dev_err(dev, "can't get xck clock\n");
  624. return -EINVAL;
  625. }
  626. if (clock->xck == clock->own) {
  627. dev_err(dev, "cpu doesn't support xck clock\n");
  628. return -EINVAL;
  629. }
  630. }
  631. /* FSIACLK/FSIBCLK */
  632. if (ick) {
  633. clock->ick = devm_clk_get(dev, is_porta ? "icka" : "ickb");
  634. if (IS_ERR(clock->ick)) {
  635. dev_err(dev, "can't get ick clock\n");
  636. return -EINVAL;
  637. }
  638. if (clock->ick == clock->own) {
  639. dev_err(dev, "cpu doesn't support ick clock\n");
  640. return -EINVAL;
  641. }
  642. }
  643. /* FSI-DIV */
  644. if (div) {
  645. clock->div = devm_clk_get(dev, is_porta ? "diva" : "divb");
  646. if (IS_ERR(clock->div)) {
  647. dev_err(dev, "can't get div clock\n");
  648. return -EINVAL;
  649. }
  650. if (clock->div == clock->own) {
  651. dev_err(dev, "cpu doens't support div clock\n");
  652. return -EINVAL;
  653. }
  654. }
  655. return 0;
  656. }
  657. #define fsi_clk_invalid(fsi) fsi_clk_valid(fsi, 0)
  658. static void fsi_clk_valid(struct fsi_priv *fsi, unsigned long rate)
  659. {
  660. fsi->clock.rate = rate;
  661. }
  662. static int fsi_clk_is_valid(struct fsi_priv *fsi)
  663. {
  664. return fsi->clock.set_rate &&
  665. fsi->clock.rate;
  666. }
  667. static int fsi_clk_enable(struct device *dev,
  668. struct fsi_priv *fsi)
  669. {
  670. struct fsi_clk *clock = &fsi->clock;
  671. int ret = -EINVAL;
  672. if (!fsi_clk_is_valid(fsi))
  673. return ret;
  674. if (0 == clock->count) {
  675. ret = clock->set_rate(dev, fsi);
  676. if (ret < 0) {
  677. fsi_clk_invalid(fsi);
  678. return ret;
  679. }
  680. if (clock->xck)
  681. clk_enable(clock->xck);
  682. if (clock->ick)
  683. clk_enable(clock->ick);
  684. if (clock->div)
  685. clk_enable(clock->div);
  686. clock->count++;
  687. }
  688. return ret;
  689. }
  690. static int fsi_clk_disable(struct device *dev,
  691. struct fsi_priv *fsi)
  692. {
  693. struct fsi_clk *clock = &fsi->clock;
  694. if (!fsi_clk_is_valid(fsi))
  695. return -EINVAL;
  696. if (1 == clock->count--) {
  697. if (clock->xck)
  698. clk_disable(clock->xck);
  699. if (clock->ick)
  700. clk_disable(clock->ick);
  701. if (clock->div)
  702. clk_disable(clock->div);
  703. }
  704. return 0;
  705. }
  706. static int fsi_clk_set_ackbpf(struct device *dev,
  707. struct fsi_priv *fsi,
  708. int ackmd, int bpfmd)
  709. {
  710. u32 data = 0;
  711. /* check ackmd/bpfmd relationship */
  712. if (bpfmd > ackmd) {
  713. dev_err(dev, "unsupported rate (%d/%d)\n", ackmd, bpfmd);
  714. return -EINVAL;
  715. }
  716. /* ACKMD */
  717. switch (ackmd) {
  718. case 512:
  719. data |= (0x0 << 12);
  720. break;
  721. case 256:
  722. data |= (0x1 << 12);
  723. break;
  724. case 128:
  725. data |= (0x2 << 12);
  726. break;
  727. case 64:
  728. data |= (0x3 << 12);
  729. break;
  730. case 32:
  731. data |= (0x4 << 12);
  732. break;
  733. default:
  734. dev_err(dev, "unsupported ackmd (%d)\n", ackmd);
  735. return -EINVAL;
  736. }
  737. /* BPFMD */
  738. switch (bpfmd) {
  739. case 32:
  740. data |= (0x0 << 8);
  741. break;
  742. case 64:
  743. data |= (0x1 << 8);
  744. break;
  745. case 128:
  746. data |= (0x2 << 8);
  747. break;
  748. case 256:
  749. data |= (0x3 << 8);
  750. break;
  751. case 512:
  752. data |= (0x4 << 8);
  753. break;
  754. case 16:
  755. data |= (0x7 << 8);
  756. break;
  757. default:
  758. dev_err(dev, "unsupported bpfmd (%d)\n", bpfmd);
  759. return -EINVAL;
  760. }
  761. dev_dbg(dev, "ACKMD/BPFMD = %d/%d\n", ackmd, bpfmd);
  762. fsi_reg_mask_set(fsi, CKG1, (ACKMD_MASK | BPFMD_MASK) , data);
  763. udelay(10);
  764. return 0;
  765. }
  766. static int fsi_clk_set_rate_external(struct device *dev,
  767. struct fsi_priv *fsi)
  768. {
  769. struct clk *xck = fsi->clock.xck;
  770. struct clk *ick = fsi->clock.ick;
  771. unsigned long rate = fsi->clock.rate;
  772. unsigned long xrate;
  773. int ackmd, bpfmd;
  774. int ret = 0;
  775. /* check clock rate */
  776. xrate = clk_get_rate(xck);
  777. if (xrate % rate) {
  778. dev_err(dev, "unsupported clock rate\n");
  779. return -EINVAL;
  780. }
  781. clk_set_parent(ick, xck);
  782. clk_set_rate(ick, xrate);
  783. bpfmd = fsi->chan_num * 32;
  784. ackmd = xrate / rate;
  785. dev_dbg(dev, "external/rate = %ld/%ld\n", xrate, rate);
  786. ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
  787. if (ret < 0)
  788. dev_err(dev, "%s failed", __func__);
  789. return ret;
  790. }
  791. static int fsi_clk_set_rate_cpg(struct device *dev,
  792. struct fsi_priv *fsi)
  793. {
  794. struct clk *ick = fsi->clock.ick;
  795. struct clk *div = fsi->clock.div;
  796. unsigned long rate = fsi->clock.rate;
  797. unsigned long target = 0; /* 12288000 or 11289600 */
  798. unsigned long actual, cout;
  799. unsigned long diff, min;
  800. unsigned long best_cout, best_act;
  801. int adj;
  802. int ackmd, bpfmd;
  803. int ret = -EINVAL;
  804. if (!(12288000 % rate))
  805. target = 12288000;
  806. if (!(11289600 % rate))
  807. target = 11289600;
  808. if (!target) {
  809. dev_err(dev, "unsupported rate\n");
  810. return ret;
  811. }
  812. bpfmd = fsi->chan_num * 32;
  813. ackmd = target / rate;
  814. ret = fsi_clk_set_ackbpf(dev, fsi, ackmd, bpfmd);
  815. if (ret < 0) {
  816. dev_err(dev, "%s failed", __func__);
  817. return ret;
  818. }
  819. /*
  820. * The clock flow is
  821. *
  822. * [CPG] = cout => [FSI_DIV] = audio => [FSI] => [codec]
  823. *
  824. * But, it needs to find best match of CPG and FSI_DIV
  825. * combination, since it is difficult to generate correct
  826. * frequency of audio clock from ick clock only.
  827. * Because ick is created from its parent clock.
  828. *
  829. * target = rate x [512/256/128/64]fs
  830. * cout = round(target x adjustment)
  831. * actual = cout / adjustment (by FSI-DIV) ~= target
  832. * audio = actual
  833. */
  834. min = ~0;
  835. best_cout = 0;
  836. best_act = 0;
  837. for (adj = 1; adj < 0xffff; adj++) {
  838. cout = target * adj;
  839. if (cout > 100000000) /* max clock = 100MHz */
  840. break;
  841. /* cout/actual audio clock */
  842. cout = clk_round_rate(ick, cout);
  843. actual = cout / adj;
  844. /* find best frequency */
  845. diff = abs(actual - target);
  846. if (diff < min) {
  847. min = diff;
  848. best_cout = cout;
  849. best_act = actual;
  850. }
  851. }
  852. ret = clk_set_rate(ick, best_cout);
  853. if (ret < 0) {
  854. dev_err(dev, "ick clock failed\n");
  855. return -EIO;
  856. }
  857. ret = clk_set_rate(div, clk_round_rate(div, best_act));
  858. if (ret < 0) {
  859. dev_err(dev, "div clock failed\n");
  860. return -EIO;
  861. }
  862. dev_dbg(dev, "ick/div = %ld/%ld\n",
  863. clk_get_rate(ick), clk_get_rate(div));
  864. return ret;
  865. }
  866. /*
  867. * pio data transfer handler
  868. */
  869. static void fsi_pio_push16(struct fsi_priv *fsi, u8 *_buf, int samples)
  870. {
  871. int i;
  872. if (fsi_is_enable_stream(fsi)) {
  873. /*
  874. * stream mode
  875. * see
  876. * fsi_pio_push_init()
  877. */
  878. u32 *buf = (u32 *)_buf;
  879. for (i = 0; i < samples / 2; i++)
  880. fsi_reg_write(fsi, DODT, buf[i]);
  881. } else {
  882. /* normal mode */
  883. u16 *buf = (u16 *)_buf;
  884. for (i = 0; i < samples; i++)
  885. fsi_reg_write(fsi, DODT, ((u32)*(buf + i) << 8));
  886. }
  887. }
  888. static void fsi_pio_pop16(struct fsi_priv *fsi, u8 *_buf, int samples)
  889. {
  890. u16 *buf = (u16 *)_buf;
  891. int i;
  892. for (i = 0; i < samples; i++)
  893. *(buf + i) = (u16)(fsi_reg_read(fsi, DIDT) >> 8);
  894. }
  895. static void fsi_pio_push32(struct fsi_priv *fsi, u8 *_buf, int samples)
  896. {
  897. u32 *buf = (u32 *)_buf;
  898. int i;
  899. for (i = 0; i < samples; i++)
  900. fsi_reg_write(fsi, DODT, *(buf + i));
  901. }
  902. static void fsi_pio_pop32(struct fsi_priv *fsi, u8 *_buf, int samples)
  903. {
  904. u32 *buf = (u32 *)_buf;
  905. int i;
  906. for (i = 0; i < samples; i++)
  907. *(buf + i) = fsi_reg_read(fsi, DIDT);
  908. }
  909. static u8 *fsi_pio_get_area(struct fsi_priv *fsi, struct fsi_stream *io)
  910. {
  911. struct snd_pcm_runtime *runtime = io->substream->runtime;
  912. return runtime->dma_area +
  913. samples_to_bytes(runtime, io->buff_sample_pos);
  914. }
  915. static int fsi_pio_transfer(struct fsi_priv *fsi, struct fsi_stream *io,
  916. void (*run16)(struct fsi_priv *fsi, u8 *buf, int samples),
  917. void (*run32)(struct fsi_priv *fsi, u8 *buf, int samples),
  918. int samples)
  919. {
  920. struct snd_pcm_runtime *runtime;
  921. struct snd_pcm_substream *substream;
  922. u8 *buf;
  923. int over_period;
  924. if (!fsi_stream_is_working(fsi, io))
  925. return -EINVAL;
  926. over_period = 0;
  927. substream = io->substream;
  928. runtime = substream->runtime;
  929. /* FSI FIFO has limit.
  930. * So, this driver can not send periods data at a time
  931. */
  932. if (io->buff_sample_pos >=
  933. io->period_samples * (io->period_pos + 1)) {
  934. over_period = 1;
  935. io->period_pos = (io->period_pos + 1) % runtime->periods;
  936. if (0 == io->period_pos)
  937. io->buff_sample_pos = 0;
  938. }
  939. buf = fsi_pio_get_area(fsi, io);
  940. switch (io->sample_width) {
  941. case 2:
  942. run16(fsi, buf, samples);
  943. break;
  944. case 4:
  945. run32(fsi, buf, samples);
  946. break;
  947. default:
  948. return -EINVAL;
  949. }
  950. /* update buff_sample_pos */
  951. io->buff_sample_pos += samples;
  952. if (over_period)
  953. snd_pcm_period_elapsed(substream);
  954. return 0;
  955. }
  956. static int fsi_pio_pop(struct fsi_priv *fsi, struct fsi_stream *io)
  957. {
  958. int sample_residues; /* samples in FSI fifo */
  959. int sample_space; /* ALSA free samples space */
  960. int samples;
  961. sample_residues = fsi_get_current_fifo_samples(fsi, io);
  962. sample_space = io->buff_sample_capa - io->buff_sample_pos;
  963. samples = min(sample_residues, sample_space);
  964. return fsi_pio_transfer(fsi, io,
  965. fsi_pio_pop16,
  966. fsi_pio_pop32,
  967. samples);
  968. }
  969. static int fsi_pio_push(struct fsi_priv *fsi, struct fsi_stream *io)
  970. {
  971. int sample_residues; /* ALSA residue samples */
  972. int sample_space; /* FSI fifo free samples space */
  973. int samples;
  974. sample_residues = io->buff_sample_capa - io->buff_sample_pos;
  975. sample_space = io->fifo_sample_capa -
  976. fsi_get_current_fifo_samples(fsi, io);
  977. samples = min(sample_residues, sample_space);
  978. return fsi_pio_transfer(fsi, io,
  979. fsi_pio_push16,
  980. fsi_pio_push32,
  981. samples);
  982. }
  983. static int fsi_pio_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  984. int enable)
  985. {
  986. struct fsi_master *master = fsi_get_master(fsi);
  987. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  988. if (enable)
  989. fsi_irq_enable(fsi, io);
  990. else
  991. fsi_irq_disable(fsi, io);
  992. if (fsi_is_clk_master(fsi))
  993. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  994. return 0;
  995. }
  996. static int fsi_pio_push_init(struct fsi_priv *fsi, struct fsi_stream *io)
  997. {
  998. /*
  999. * we can use 16bit stream mode
  1000. * when "playback" and "16bit data"
  1001. * and platform allows "stream mode"
  1002. * see
  1003. * fsi_pio_push16()
  1004. */
  1005. if (fsi_is_enable_stream(fsi))
  1006. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1007. BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
  1008. else
  1009. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1010. BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
  1011. return 0;
  1012. }
  1013. static int fsi_pio_pop_init(struct fsi_priv *fsi, struct fsi_stream *io)
  1014. {
  1015. /*
  1016. * always 24bit bus, package back when "capture"
  1017. */
  1018. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1019. BUSOP_SET(16, PACKAGE_24BITBUS_BACK);
  1020. return 0;
  1021. }
  1022. static struct fsi_stream_handler fsi_pio_push_handler = {
  1023. .init = fsi_pio_push_init,
  1024. .transfer = fsi_pio_push,
  1025. .start_stop = fsi_pio_start_stop,
  1026. };
  1027. static struct fsi_stream_handler fsi_pio_pop_handler = {
  1028. .init = fsi_pio_pop_init,
  1029. .transfer = fsi_pio_pop,
  1030. .start_stop = fsi_pio_start_stop,
  1031. };
  1032. static irqreturn_t fsi_interrupt(int irq, void *data)
  1033. {
  1034. struct fsi_master *master = data;
  1035. u32 int_st = fsi_irq_get_status(master);
  1036. /* clear irq status */
  1037. fsi_master_mask_set(master, SOFT_RST, IR, 0);
  1038. fsi_master_mask_set(master, SOFT_RST, IR, IR);
  1039. if (int_st & AB_IO(1, AO_SHIFT))
  1040. fsi_stream_transfer(&master->fsia.playback);
  1041. if (int_st & AB_IO(1, BO_SHIFT))
  1042. fsi_stream_transfer(&master->fsib.playback);
  1043. if (int_st & AB_IO(1, AI_SHIFT))
  1044. fsi_stream_transfer(&master->fsia.capture);
  1045. if (int_st & AB_IO(1, BI_SHIFT))
  1046. fsi_stream_transfer(&master->fsib.capture);
  1047. fsi_count_fifo_err(&master->fsia);
  1048. fsi_count_fifo_err(&master->fsib);
  1049. fsi_irq_clear_status(&master->fsia);
  1050. fsi_irq_clear_status(&master->fsib);
  1051. return IRQ_HANDLED;
  1052. }
  1053. /*
  1054. * dma data transfer handler
  1055. */
  1056. static int fsi_dma_init(struct fsi_priv *fsi, struct fsi_stream *io)
  1057. {
  1058. struct snd_pcm_runtime *runtime = io->substream->runtime;
  1059. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  1060. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  1061. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  1062. /*
  1063. * 24bit data : 24bit bus / package in back
  1064. * 16bit data : 16bit bus / stream mode
  1065. */
  1066. io->bus_option = BUSOP_SET(24, PACKAGE_24BITBUS_BACK) |
  1067. BUSOP_SET(16, PACKAGE_16BITBUS_STREAM);
  1068. io->dma = dma_map_single(dai->dev, runtime->dma_area,
  1069. snd_pcm_lib_buffer_bytes(io->substream), dir);
  1070. return 0;
  1071. }
  1072. static int fsi_dma_quit(struct fsi_priv *fsi, struct fsi_stream *io)
  1073. {
  1074. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  1075. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  1076. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  1077. dma_unmap_single(dai->dev, io->dma,
  1078. snd_pcm_lib_buffer_bytes(io->substream), dir);
  1079. return 0;
  1080. }
  1081. static dma_addr_t fsi_dma_get_area(struct fsi_stream *io)
  1082. {
  1083. struct snd_pcm_runtime *runtime = io->substream->runtime;
  1084. return io->dma + samples_to_bytes(runtime, io->buff_sample_pos);
  1085. }
  1086. static void fsi_dma_complete(void *data)
  1087. {
  1088. struct fsi_stream *io = (struct fsi_stream *)data;
  1089. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  1090. struct snd_pcm_runtime *runtime = io->substream->runtime;
  1091. struct snd_soc_dai *dai = fsi_get_dai(io->substream);
  1092. enum dma_data_direction dir = fsi_stream_is_play(fsi, io) ?
  1093. DMA_TO_DEVICE : DMA_FROM_DEVICE;
  1094. dma_sync_single_for_cpu(dai->dev, fsi_dma_get_area(io),
  1095. samples_to_bytes(runtime, io->period_samples), dir);
  1096. io->buff_sample_pos += io->period_samples;
  1097. io->period_pos++;
  1098. if (io->period_pos >= runtime->periods) {
  1099. io->period_pos = 0;
  1100. io->buff_sample_pos = 0;
  1101. }
  1102. fsi_count_fifo_err(fsi);
  1103. fsi_stream_transfer(io);
  1104. snd_pcm_period_elapsed(io->substream);
  1105. }
  1106. static void fsi_dma_do_work(struct work_struct *work)
  1107. {
  1108. struct fsi_stream *io = container_of(work, struct fsi_stream, work);
  1109. struct fsi_priv *fsi = fsi_stream_to_priv(io);
  1110. struct snd_soc_dai *dai;
  1111. struct dma_async_tx_descriptor *desc;
  1112. struct snd_pcm_runtime *runtime;
  1113. enum dma_data_direction dir;
  1114. int is_play = fsi_stream_is_play(fsi, io);
  1115. int len;
  1116. dma_addr_t buf;
  1117. if (!fsi_stream_is_working(fsi, io))
  1118. return;
  1119. dai = fsi_get_dai(io->substream);
  1120. runtime = io->substream->runtime;
  1121. dir = is_play ? DMA_TO_DEVICE : DMA_FROM_DEVICE;
  1122. len = samples_to_bytes(runtime, io->period_samples);
  1123. buf = fsi_dma_get_area(io);
  1124. dma_sync_single_for_device(dai->dev, buf, len, dir);
  1125. desc = dmaengine_prep_slave_single(io->chan, buf, len, dir,
  1126. DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
  1127. if (!desc) {
  1128. dev_err(dai->dev, "dmaengine_prep_slave_sg() fail\n");
  1129. return;
  1130. }
  1131. desc->callback = fsi_dma_complete;
  1132. desc->callback_param = io;
  1133. if (dmaengine_submit(desc) < 0) {
  1134. dev_err(dai->dev, "tx_submit() fail\n");
  1135. return;
  1136. }
  1137. dma_async_issue_pending(io->chan);
  1138. /*
  1139. * FIXME
  1140. *
  1141. * In DMAEngine case, codec and FSI cannot be started simultaneously
  1142. * since FSI is using the scheduler work queue.
  1143. * Therefore, in capture case, probably FSI FIFO will have got
  1144. * overflow error in this point.
  1145. * in that case, DMA cannot start transfer until error was cleared.
  1146. */
  1147. if (!is_play) {
  1148. if (ERR_OVER & fsi_reg_read(fsi, DIFF_ST)) {
  1149. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  1150. fsi_reg_write(fsi, DIFF_ST, 0);
  1151. }
  1152. }
  1153. }
  1154. static bool fsi_dma_filter(struct dma_chan *chan, void *param)
  1155. {
  1156. struct sh_dmae_slave *slave = param;
  1157. chan->private = slave;
  1158. return true;
  1159. }
  1160. static int fsi_dma_transfer(struct fsi_priv *fsi, struct fsi_stream *io)
  1161. {
  1162. schedule_work(&io->work);
  1163. return 0;
  1164. }
  1165. static int fsi_dma_push_start_stop(struct fsi_priv *fsi, struct fsi_stream *io,
  1166. int start)
  1167. {
  1168. struct fsi_master *master = fsi_get_master(fsi);
  1169. u32 clk = fsi_is_port_a(fsi) ? CRA : CRB;
  1170. u32 enable = start ? DMA_ON : 0;
  1171. fsi_reg_mask_set(fsi, OUT_DMAC, DMA_ON, enable);
  1172. dmaengine_terminate_all(io->chan);
  1173. if (fsi_is_clk_master(fsi))
  1174. fsi_master_mask_set(master, CLK_RST, clk, (enable) ? clk : 0);
  1175. return 0;
  1176. }
  1177. static int fsi_dma_probe(struct fsi_priv *fsi, struct fsi_stream *io, struct device *dev)
  1178. {
  1179. dma_cap_mask_t mask;
  1180. dma_cap_zero(mask);
  1181. dma_cap_set(DMA_SLAVE, mask);
  1182. io->chan = dma_request_channel(mask, fsi_dma_filter, &io->slave);
  1183. if (!io->chan) {
  1184. /* switch to PIO handler */
  1185. if (fsi_stream_is_play(fsi, io))
  1186. fsi->playback.handler = &fsi_pio_push_handler;
  1187. else
  1188. fsi->capture.handler = &fsi_pio_pop_handler;
  1189. dev_info(dev, "switch handler (dma => pio)\n");
  1190. /* probe again */
  1191. return fsi_stream_probe(fsi, dev);
  1192. }
  1193. INIT_WORK(&io->work, fsi_dma_do_work);
  1194. return 0;
  1195. }
  1196. static int fsi_dma_remove(struct fsi_priv *fsi, struct fsi_stream *io)
  1197. {
  1198. cancel_work_sync(&io->work);
  1199. fsi_stream_stop(fsi, io);
  1200. if (io->chan)
  1201. dma_release_channel(io->chan);
  1202. io->chan = NULL;
  1203. return 0;
  1204. }
  1205. static struct fsi_stream_handler fsi_dma_push_handler = {
  1206. .init = fsi_dma_init,
  1207. .quit = fsi_dma_quit,
  1208. .probe = fsi_dma_probe,
  1209. .transfer = fsi_dma_transfer,
  1210. .remove = fsi_dma_remove,
  1211. .start_stop = fsi_dma_push_start_stop,
  1212. };
  1213. /*
  1214. * dai ops
  1215. */
  1216. static void fsi_fifo_init(struct fsi_priv *fsi,
  1217. struct fsi_stream *io,
  1218. struct device *dev)
  1219. {
  1220. struct fsi_master *master = fsi_get_master(fsi);
  1221. int is_play = fsi_stream_is_play(fsi, io);
  1222. u32 shift, i;
  1223. int frame_capa;
  1224. /* get on-chip RAM capacity */
  1225. shift = fsi_master_read(master, FIFO_SZ);
  1226. shift >>= fsi_get_port_shift(fsi, io);
  1227. shift &= FIFO_SZ_MASK;
  1228. frame_capa = 256 << shift;
  1229. dev_dbg(dev, "fifo = %d words\n", frame_capa);
  1230. /*
  1231. * The maximum number of sample data varies depending
  1232. * on the number of channels selected for the format.
  1233. *
  1234. * FIFOs are used in 4-channel units in 3-channel mode
  1235. * and in 8-channel units in 5- to 7-channel mode
  1236. * meaning that more FIFOs than the required size of DPRAM
  1237. * are used.
  1238. *
  1239. * ex) if 256 words of DP-RAM is connected
  1240. * 1 channel: 256 (256 x 1 = 256)
  1241. * 2 channels: 128 (128 x 2 = 256)
  1242. * 3 channels: 64 ( 64 x 3 = 192)
  1243. * 4 channels: 64 ( 64 x 4 = 256)
  1244. * 5 channels: 32 ( 32 x 5 = 160)
  1245. * 6 channels: 32 ( 32 x 6 = 192)
  1246. * 7 channels: 32 ( 32 x 7 = 224)
  1247. * 8 channels: 32 ( 32 x 8 = 256)
  1248. */
  1249. for (i = 1; i < fsi->chan_num; i <<= 1)
  1250. frame_capa >>= 1;
  1251. dev_dbg(dev, "%d channel %d store\n",
  1252. fsi->chan_num, frame_capa);
  1253. io->fifo_sample_capa = fsi_frame2sample(fsi, frame_capa);
  1254. /*
  1255. * set interrupt generation factor
  1256. * clear FIFO
  1257. */
  1258. if (is_play) {
  1259. fsi_reg_write(fsi, DOFF_CTL, IRQ_HALF);
  1260. fsi_reg_mask_set(fsi, DOFF_CTL, FIFO_CLR, FIFO_CLR);
  1261. } else {
  1262. fsi_reg_write(fsi, DIFF_CTL, IRQ_HALF);
  1263. fsi_reg_mask_set(fsi, DIFF_CTL, FIFO_CLR, FIFO_CLR);
  1264. }
  1265. }
  1266. static int fsi_hw_startup(struct fsi_priv *fsi,
  1267. struct fsi_stream *io,
  1268. struct device *dev)
  1269. {
  1270. u32 data = 0;
  1271. /* clock setting */
  1272. if (fsi_is_clk_master(fsi))
  1273. data = DIMD | DOMD;
  1274. fsi_reg_mask_set(fsi, CKG1, (DIMD | DOMD), data);
  1275. /* clock inversion (CKG2) */
  1276. data = 0;
  1277. if (fsi->bit_clk_inv)
  1278. data |= (1 << 0);
  1279. if (fsi->lr_clk_inv)
  1280. data |= (1 << 4);
  1281. if (fsi_is_clk_master(fsi))
  1282. data <<= 8;
  1283. fsi_reg_write(fsi, CKG2, data);
  1284. /* spdif ? */
  1285. if (fsi_is_spdif(fsi)) {
  1286. fsi_spdif_clk_ctrl(fsi, 1);
  1287. fsi_reg_mask_set(fsi, OUT_SEL, DMMD, DMMD);
  1288. }
  1289. /*
  1290. * get bus settings
  1291. */
  1292. data = 0;
  1293. switch (io->sample_width) {
  1294. case 2:
  1295. data = BUSOP_GET(16, io->bus_option);
  1296. break;
  1297. case 4:
  1298. data = BUSOP_GET(24, io->bus_option);
  1299. break;
  1300. }
  1301. fsi_format_bus_setup(fsi, io, data, dev);
  1302. /* irq clear */
  1303. fsi_irq_disable(fsi, io);
  1304. fsi_irq_clear_status(fsi);
  1305. /* fifo init */
  1306. fsi_fifo_init(fsi, io, dev);
  1307. /* start master clock */
  1308. if (fsi_is_clk_master(fsi))
  1309. return fsi_clk_enable(dev, fsi);
  1310. return 0;
  1311. }
  1312. static int fsi_hw_shutdown(struct fsi_priv *fsi,
  1313. struct device *dev)
  1314. {
  1315. /* stop master clock */
  1316. if (fsi_is_clk_master(fsi))
  1317. return fsi_clk_disable(dev, fsi);
  1318. return 0;
  1319. }
  1320. static int fsi_dai_startup(struct snd_pcm_substream *substream,
  1321. struct snd_soc_dai *dai)
  1322. {
  1323. struct fsi_priv *fsi = fsi_get_priv(substream);
  1324. fsi_clk_invalid(fsi);
  1325. return 0;
  1326. }
  1327. static void fsi_dai_shutdown(struct snd_pcm_substream *substream,
  1328. struct snd_soc_dai *dai)
  1329. {
  1330. struct fsi_priv *fsi = fsi_get_priv(substream);
  1331. fsi_clk_invalid(fsi);
  1332. }
  1333. static int fsi_dai_trigger(struct snd_pcm_substream *substream, int cmd,
  1334. struct snd_soc_dai *dai)
  1335. {
  1336. struct fsi_priv *fsi = fsi_get_priv(substream);
  1337. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1338. int ret = 0;
  1339. switch (cmd) {
  1340. case SNDRV_PCM_TRIGGER_START:
  1341. fsi_stream_init(fsi, io, substream);
  1342. if (!ret)
  1343. ret = fsi_hw_startup(fsi, io, dai->dev);
  1344. if (!ret)
  1345. ret = fsi_stream_transfer(io);
  1346. if (!ret)
  1347. fsi_stream_start(fsi, io);
  1348. break;
  1349. case SNDRV_PCM_TRIGGER_STOP:
  1350. if (!ret)
  1351. ret = fsi_hw_shutdown(fsi, dai->dev);
  1352. fsi_stream_stop(fsi, io);
  1353. fsi_stream_quit(fsi, io);
  1354. break;
  1355. }
  1356. return ret;
  1357. }
  1358. static int fsi_set_fmt_dai(struct fsi_priv *fsi, unsigned int fmt)
  1359. {
  1360. switch (fmt & SND_SOC_DAIFMT_FORMAT_MASK) {
  1361. case SND_SOC_DAIFMT_I2S:
  1362. fsi->fmt = CR_I2S;
  1363. fsi->chan_num = 2;
  1364. break;
  1365. case SND_SOC_DAIFMT_LEFT_J:
  1366. fsi->fmt = CR_PCM;
  1367. fsi->chan_num = 2;
  1368. break;
  1369. default:
  1370. return -EINVAL;
  1371. }
  1372. return 0;
  1373. }
  1374. static int fsi_set_fmt_spdif(struct fsi_priv *fsi)
  1375. {
  1376. struct fsi_master *master = fsi_get_master(fsi);
  1377. if (fsi_version(master) < 2)
  1378. return -EINVAL;
  1379. fsi->fmt = CR_DTMD_SPDIF_PCM | CR_PCM;
  1380. fsi->chan_num = 2;
  1381. return 0;
  1382. }
  1383. static int fsi_dai_set_fmt(struct snd_soc_dai *dai, unsigned int fmt)
  1384. {
  1385. struct fsi_priv *fsi = fsi_get_priv_frm_dai(dai);
  1386. int ret;
  1387. /* set master/slave audio interface */
  1388. switch (fmt & SND_SOC_DAIFMT_MASTER_MASK) {
  1389. case SND_SOC_DAIFMT_CBM_CFM:
  1390. fsi->clk_master = 1;
  1391. break;
  1392. case SND_SOC_DAIFMT_CBS_CFS:
  1393. break;
  1394. default:
  1395. return -EINVAL;
  1396. }
  1397. /* set clock inversion */
  1398. switch (fmt & SND_SOC_DAIFMT_INV_MASK) {
  1399. case SND_SOC_DAIFMT_NB_IF:
  1400. fsi->bit_clk_inv = 0;
  1401. fsi->lr_clk_inv = 1;
  1402. break;
  1403. case SND_SOC_DAIFMT_IB_NF:
  1404. fsi->bit_clk_inv = 1;
  1405. fsi->lr_clk_inv = 0;
  1406. break;
  1407. case SND_SOC_DAIFMT_IB_IF:
  1408. fsi->bit_clk_inv = 1;
  1409. fsi->lr_clk_inv = 1;
  1410. break;
  1411. case SND_SOC_DAIFMT_NB_NF:
  1412. default:
  1413. fsi->bit_clk_inv = 0;
  1414. fsi->lr_clk_inv = 0;
  1415. break;
  1416. }
  1417. if (fsi_is_clk_master(fsi)) {
  1418. if (fsi->clk_cpg)
  1419. fsi_clk_init(dai->dev, fsi, 0, 1, 1,
  1420. fsi_clk_set_rate_cpg);
  1421. else
  1422. fsi_clk_init(dai->dev, fsi, 1, 1, 0,
  1423. fsi_clk_set_rate_external);
  1424. }
  1425. /* set format */
  1426. if (fsi_is_spdif(fsi))
  1427. ret = fsi_set_fmt_spdif(fsi);
  1428. else
  1429. ret = fsi_set_fmt_dai(fsi, fmt & SND_SOC_DAIFMT_FORMAT_MASK);
  1430. return ret;
  1431. }
  1432. static int fsi_dai_hw_params(struct snd_pcm_substream *substream,
  1433. struct snd_pcm_hw_params *params,
  1434. struct snd_soc_dai *dai)
  1435. {
  1436. struct fsi_priv *fsi = fsi_get_priv(substream);
  1437. if (fsi_is_clk_master(fsi))
  1438. fsi_clk_valid(fsi, params_rate(params));
  1439. return 0;
  1440. }
  1441. static const struct snd_soc_dai_ops fsi_dai_ops = {
  1442. .startup = fsi_dai_startup,
  1443. .shutdown = fsi_dai_shutdown,
  1444. .trigger = fsi_dai_trigger,
  1445. .set_fmt = fsi_dai_set_fmt,
  1446. .hw_params = fsi_dai_hw_params,
  1447. };
  1448. /*
  1449. * pcm ops
  1450. */
  1451. static struct snd_pcm_hardware fsi_pcm_hardware = {
  1452. .info = SNDRV_PCM_INFO_INTERLEAVED |
  1453. SNDRV_PCM_INFO_MMAP |
  1454. SNDRV_PCM_INFO_MMAP_VALID |
  1455. SNDRV_PCM_INFO_PAUSE,
  1456. .formats = FSI_FMTS,
  1457. .rates = FSI_RATES,
  1458. .rate_min = 8000,
  1459. .rate_max = 192000,
  1460. .channels_min = 2,
  1461. .channels_max = 2,
  1462. .buffer_bytes_max = 64 * 1024,
  1463. .period_bytes_min = 32,
  1464. .period_bytes_max = 8192,
  1465. .periods_min = 1,
  1466. .periods_max = 32,
  1467. .fifo_size = 256,
  1468. };
  1469. static int fsi_pcm_open(struct snd_pcm_substream *substream)
  1470. {
  1471. struct snd_pcm_runtime *runtime = substream->runtime;
  1472. int ret = 0;
  1473. snd_soc_set_runtime_hwparams(substream, &fsi_pcm_hardware);
  1474. ret = snd_pcm_hw_constraint_integer(runtime,
  1475. SNDRV_PCM_HW_PARAM_PERIODS);
  1476. return ret;
  1477. }
  1478. static int fsi_hw_params(struct snd_pcm_substream *substream,
  1479. struct snd_pcm_hw_params *hw_params)
  1480. {
  1481. return snd_pcm_lib_malloc_pages(substream,
  1482. params_buffer_bytes(hw_params));
  1483. }
  1484. static int fsi_hw_free(struct snd_pcm_substream *substream)
  1485. {
  1486. return snd_pcm_lib_free_pages(substream);
  1487. }
  1488. static snd_pcm_uframes_t fsi_pointer(struct snd_pcm_substream *substream)
  1489. {
  1490. struct fsi_priv *fsi = fsi_get_priv(substream);
  1491. struct fsi_stream *io = fsi_stream_get(fsi, substream);
  1492. return fsi_sample2frame(fsi, io->buff_sample_pos);
  1493. }
  1494. static struct snd_pcm_ops fsi_pcm_ops = {
  1495. .open = fsi_pcm_open,
  1496. .ioctl = snd_pcm_lib_ioctl,
  1497. .hw_params = fsi_hw_params,
  1498. .hw_free = fsi_hw_free,
  1499. .pointer = fsi_pointer,
  1500. };
  1501. /*
  1502. * snd_soc_platform
  1503. */
  1504. #define PREALLOC_BUFFER (32 * 1024)
  1505. #define PREALLOC_BUFFER_MAX (32 * 1024)
  1506. static void fsi_pcm_free(struct snd_pcm *pcm)
  1507. {
  1508. snd_pcm_lib_preallocate_free_for_all(pcm);
  1509. }
  1510. static int fsi_pcm_new(struct snd_soc_pcm_runtime *rtd)
  1511. {
  1512. struct snd_pcm *pcm = rtd->pcm;
  1513. /*
  1514. * dont use SNDRV_DMA_TYPE_DEV, since it will oops the SH kernel
  1515. * in MMAP mode (i.e. aplay -M)
  1516. */
  1517. return snd_pcm_lib_preallocate_pages_for_all(
  1518. pcm,
  1519. SNDRV_DMA_TYPE_CONTINUOUS,
  1520. snd_dma_continuous_data(GFP_KERNEL),
  1521. PREALLOC_BUFFER, PREALLOC_BUFFER_MAX);
  1522. }
  1523. /*
  1524. * alsa struct
  1525. */
  1526. static struct snd_soc_dai_driver fsi_soc_dai[] = {
  1527. {
  1528. .name = "fsia-dai",
  1529. .playback = {
  1530. .rates = FSI_RATES,
  1531. .formats = FSI_FMTS,
  1532. .channels_min = 2,
  1533. .channels_max = 2,
  1534. },
  1535. .capture = {
  1536. .rates = FSI_RATES,
  1537. .formats = FSI_FMTS,
  1538. .channels_min = 2,
  1539. .channels_max = 2,
  1540. },
  1541. .ops = &fsi_dai_ops,
  1542. },
  1543. {
  1544. .name = "fsib-dai",
  1545. .playback = {
  1546. .rates = FSI_RATES,
  1547. .formats = FSI_FMTS,
  1548. .channels_min = 2,
  1549. .channels_max = 2,
  1550. },
  1551. .capture = {
  1552. .rates = FSI_RATES,
  1553. .formats = FSI_FMTS,
  1554. .channels_min = 2,
  1555. .channels_max = 2,
  1556. },
  1557. .ops = &fsi_dai_ops,
  1558. },
  1559. };
  1560. static struct snd_soc_platform_driver fsi_soc_platform = {
  1561. .ops = &fsi_pcm_ops,
  1562. .pcm_new = fsi_pcm_new,
  1563. .pcm_free = fsi_pcm_free,
  1564. };
  1565. static const struct snd_soc_component_driver fsi_soc_component = {
  1566. .name = "fsi",
  1567. };
  1568. /*
  1569. * platform function
  1570. */
  1571. static void fsi_of_parse(char *name,
  1572. struct device_node *np,
  1573. struct sh_fsi_port_info *info,
  1574. struct device *dev)
  1575. {
  1576. int i;
  1577. char prop[128];
  1578. unsigned long flags = 0;
  1579. struct {
  1580. char *name;
  1581. unsigned int val;
  1582. } of_parse_property[] = {
  1583. { "spdif-connection", SH_FSI_FMT_SPDIF },
  1584. { "stream-mode-support", SH_FSI_ENABLE_STREAM_MODE },
  1585. { "use-internal-clock", SH_FSI_CLK_CPG },
  1586. };
  1587. for (i = 0; i < ARRAY_SIZE(of_parse_property); i++) {
  1588. sprintf(prop, "%s,%s", name, of_parse_property[i].name);
  1589. if (of_get_property(np, prop, NULL))
  1590. flags |= of_parse_property[i].val;
  1591. }
  1592. info->flags = flags;
  1593. dev_dbg(dev, "%s flags : %lx\n", name, info->flags);
  1594. }
  1595. static void fsi_port_info_init(struct fsi_priv *fsi,
  1596. struct sh_fsi_port_info *info)
  1597. {
  1598. if (info->flags & SH_FSI_FMT_SPDIF)
  1599. fsi->spdif = 1;
  1600. if (info->flags & SH_FSI_CLK_CPG)
  1601. fsi->clk_cpg = 1;
  1602. if (info->flags & SH_FSI_ENABLE_STREAM_MODE)
  1603. fsi->enable_stream = 1;
  1604. }
  1605. static void fsi_handler_init(struct fsi_priv *fsi,
  1606. struct sh_fsi_port_info *info)
  1607. {
  1608. fsi->playback.handler = &fsi_pio_push_handler; /* default PIO */
  1609. fsi->playback.priv = fsi;
  1610. fsi->capture.handler = &fsi_pio_pop_handler; /* default PIO */
  1611. fsi->capture.priv = fsi;
  1612. if (info->tx_id) {
  1613. fsi->playback.slave.shdma_slave.slave_id = info->tx_id;
  1614. fsi->playback.handler = &fsi_dma_push_handler;
  1615. }
  1616. }
  1617. static struct of_device_id fsi_of_match[];
  1618. static int fsi_probe(struct platform_device *pdev)
  1619. {
  1620. struct fsi_master *master;
  1621. struct device_node *np = pdev->dev.of_node;
  1622. struct sh_fsi_platform_info info;
  1623. const struct fsi_core *core;
  1624. struct fsi_priv *fsi;
  1625. struct resource *res;
  1626. unsigned int irq;
  1627. int ret;
  1628. memset(&info, 0, sizeof(info));
  1629. core = NULL;
  1630. if (np) {
  1631. const struct of_device_id *of_id;
  1632. of_id = of_match_device(fsi_of_match, &pdev->dev);
  1633. if (of_id) {
  1634. core = of_id->data;
  1635. fsi_of_parse("fsia", np, &info.port_a, &pdev->dev);
  1636. fsi_of_parse("fsib", np, &info.port_b, &pdev->dev);
  1637. }
  1638. } else {
  1639. const struct platform_device_id *id_entry = pdev->id_entry;
  1640. if (id_entry)
  1641. core = (struct fsi_core *)id_entry->driver_data;
  1642. if (pdev->dev.platform_data)
  1643. memcpy(&info, pdev->dev.platform_data, sizeof(info));
  1644. }
  1645. if (!core) {
  1646. dev_err(&pdev->dev, "unknown fsi device\n");
  1647. return -ENODEV;
  1648. }
  1649. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1650. irq = platform_get_irq(pdev, 0);
  1651. if (!res || (int)irq <= 0) {
  1652. dev_err(&pdev->dev, "Not enough FSI platform resources.\n");
  1653. return -ENODEV;
  1654. }
  1655. master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
  1656. if (!master) {
  1657. dev_err(&pdev->dev, "Could not allocate master\n");
  1658. return -ENOMEM;
  1659. }
  1660. master->base = devm_ioremap_nocache(&pdev->dev,
  1661. res->start, resource_size(res));
  1662. if (!master->base) {
  1663. dev_err(&pdev->dev, "Unable to ioremap FSI registers.\n");
  1664. return -ENXIO;
  1665. }
  1666. /* master setting */
  1667. master->core = core;
  1668. spin_lock_init(&master->lock);
  1669. /* FSI A setting */
  1670. fsi = &master->fsia;
  1671. fsi->base = master->base;
  1672. fsi->master = master;
  1673. fsi_port_info_init(fsi, &info.port_a);
  1674. fsi_handler_init(fsi, &info.port_a);
  1675. ret = fsi_stream_probe(fsi, &pdev->dev);
  1676. if (ret < 0) {
  1677. dev_err(&pdev->dev, "FSIA stream probe failed\n");
  1678. return ret;
  1679. }
  1680. /* FSI B setting */
  1681. fsi = &master->fsib;
  1682. fsi->base = master->base + 0x40;
  1683. fsi->master = master;
  1684. fsi_port_info_init(fsi, &info.port_b);
  1685. fsi_handler_init(fsi, &info.port_b);
  1686. ret = fsi_stream_probe(fsi, &pdev->dev);
  1687. if (ret < 0) {
  1688. dev_err(&pdev->dev, "FSIB stream probe failed\n");
  1689. goto exit_fsia;
  1690. }
  1691. pm_runtime_enable(&pdev->dev);
  1692. dev_set_drvdata(&pdev->dev, master);
  1693. ret = devm_request_irq(&pdev->dev, irq, &fsi_interrupt, 0,
  1694. dev_name(&pdev->dev), master);
  1695. if (ret) {
  1696. dev_err(&pdev->dev, "irq request err\n");
  1697. goto exit_fsib;
  1698. }
  1699. ret = snd_soc_register_platform(&pdev->dev, &fsi_soc_platform);
  1700. if (ret < 0) {
  1701. dev_err(&pdev->dev, "cannot snd soc register\n");
  1702. goto exit_fsib;
  1703. }
  1704. ret = snd_soc_register_component(&pdev->dev, &fsi_soc_component,
  1705. fsi_soc_dai, ARRAY_SIZE(fsi_soc_dai));
  1706. if (ret < 0) {
  1707. dev_err(&pdev->dev, "cannot snd component register\n");
  1708. goto exit_snd_soc;
  1709. }
  1710. return ret;
  1711. exit_snd_soc:
  1712. snd_soc_unregister_platform(&pdev->dev);
  1713. exit_fsib:
  1714. pm_runtime_disable(&pdev->dev);
  1715. fsi_stream_remove(&master->fsib);
  1716. exit_fsia:
  1717. fsi_stream_remove(&master->fsia);
  1718. return ret;
  1719. }
  1720. static int fsi_remove(struct platform_device *pdev)
  1721. {
  1722. struct fsi_master *master;
  1723. master = dev_get_drvdata(&pdev->dev);
  1724. pm_runtime_disable(&pdev->dev);
  1725. snd_soc_unregister_component(&pdev->dev);
  1726. snd_soc_unregister_platform(&pdev->dev);
  1727. fsi_stream_remove(&master->fsia);
  1728. fsi_stream_remove(&master->fsib);
  1729. return 0;
  1730. }
  1731. static void __fsi_suspend(struct fsi_priv *fsi,
  1732. struct fsi_stream *io,
  1733. struct device *dev)
  1734. {
  1735. if (!fsi_stream_is_working(fsi, io))
  1736. return;
  1737. fsi_stream_stop(fsi, io);
  1738. fsi_hw_shutdown(fsi, dev);
  1739. }
  1740. static void __fsi_resume(struct fsi_priv *fsi,
  1741. struct fsi_stream *io,
  1742. struct device *dev)
  1743. {
  1744. if (!fsi_stream_is_working(fsi, io))
  1745. return;
  1746. fsi_hw_startup(fsi, io, dev);
  1747. fsi_stream_start(fsi, io);
  1748. }
  1749. static int fsi_suspend(struct device *dev)
  1750. {
  1751. struct fsi_master *master = dev_get_drvdata(dev);
  1752. struct fsi_priv *fsia = &master->fsia;
  1753. struct fsi_priv *fsib = &master->fsib;
  1754. __fsi_suspend(fsia, &fsia->playback, dev);
  1755. __fsi_suspend(fsia, &fsia->capture, dev);
  1756. __fsi_suspend(fsib, &fsib->playback, dev);
  1757. __fsi_suspend(fsib, &fsib->capture, dev);
  1758. return 0;
  1759. }
  1760. static int fsi_resume(struct device *dev)
  1761. {
  1762. struct fsi_master *master = dev_get_drvdata(dev);
  1763. struct fsi_priv *fsia = &master->fsia;
  1764. struct fsi_priv *fsib = &master->fsib;
  1765. __fsi_resume(fsia, &fsia->playback, dev);
  1766. __fsi_resume(fsia, &fsia->capture, dev);
  1767. __fsi_resume(fsib, &fsib->playback, dev);
  1768. __fsi_resume(fsib, &fsib->capture, dev);
  1769. return 0;
  1770. }
  1771. static struct dev_pm_ops fsi_pm_ops = {
  1772. .suspend = fsi_suspend,
  1773. .resume = fsi_resume,
  1774. };
  1775. static struct fsi_core fsi1_core = {
  1776. .ver = 1,
  1777. /* Interrupt */
  1778. .int_st = INT_ST,
  1779. .iemsk = IEMSK,
  1780. .imsk = IMSK,
  1781. };
  1782. static struct fsi_core fsi2_core = {
  1783. .ver = 2,
  1784. /* Interrupt */
  1785. .int_st = CPU_INT_ST,
  1786. .iemsk = CPU_IEMSK,
  1787. .imsk = CPU_IMSK,
  1788. .a_mclk = A_MST_CTLR,
  1789. .b_mclk = B_MST_CTLR,
  1790. };
  1791. static struct of_device_id fsi_of_match[] = {
  1792. { .compatible = "renesas,sh_fsi", .data = &fsi1_core},
  1793. { .compatible = "renesas,sh_fsi2", .data = &fsi2_core},
  1794. {},
  1795. };
  1796. MODULE_DEVICE_TABLE(of, fsi_of_match);
  1797. static struct platform_device_id fsi_id_table[] = {
  1798. { "sh_fsi", (kernel_ulong_t)&fsi1_core },
  1799. { "sh_fsi2", (kernel_ulong_t)&fsi2_core },
  1800. {},
  1801. };
  1802. MODULE_DEVICE_TABLE(platform, fsi_id_table);
  1803. static struct platform_driver fsi_driver = {
  1804. .driver = {
  1805. .name = "fsi-pcm-audio",
  1806. .pm = &fsi_pm_ops,
  1807. .of_match_table = fsi_of_match,
  1808. },
  1809. .probe = fsi_probe,
  1810. .remove = fsi_remove,
  1811. .id_table = fsi_id_table,
  1812. };
  1813. module_platform_driver(fsi_driver);
  1814. MODULE_LICENSE("GPL");
  1815. MODULE_DESCRIPTION("SuperH onchip FSI audio driver");
  1816. MODULE_AUTHOR("Kuninori Morimoto <morimoto.kuninori@renesas.com>");
  1817. MODULE_ALIAS("platform:fsi-pcm-audio");