mr.c 22 KB

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  1. /*
  2. * Copyright (c) 2013, Mellanox Technologies inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/kref.h>
  33. #include <linux/random.h>
  34. #include <linux/debugfs.h>
  35. #include <linux/export.h>
  36. #include <rdma/ib_umem.h>
  37. #include "mlx5_ib.h"
  38. enum {
  39. DEF_CACHE_SIZE = 10,
  40. };
  41. static __be64 *mr_align(__be64 *ptr, int align)
  42. {
  43. unsigned long mask = align - 1;
  44. return (__be64 *)(((unsigned long)ptr + mask) & ~mask);
  45. }
  46. static int order2idx(struct mlx5_ib_dev *dev, int order)
  47. {
  48. struct mlx5_mr_cache *cache = &dev->cache;
  49. if (order < cache->ent[0].order)
  50. return 0;
  51. else
  52. return order - cache->ent[0].order;
  53. }
  54. static int add_keys(struct mlx5_ib_dev *dev, int c, int num)
  55. {
  56. struct device *ddev = dev->ib_dev.dma_device;
  57. struct mlx5_mr_cache *cache = &dev->cache;
  58. struct mlx5_cache_ent *ent = &cache->ent[c];
  59. struct mlx5_create_mkey_mbox_in *in;
  60. struct mlx5_ib_mr *mr;
  61. int npages = 1 << ent->order;
  62. int size = sizeof(u64) * npages;
  63. int err = 0;
  64. int i;
  65. in = kzalloc(sizeof(*in), GFP_KERNEL);
  66. if (!in)
  67. return -ENOMEM;
  68. for (i = 0; i < num; i++) {
  69. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  70. if (!mr) {
  71. err = -ENOMEM;
  72. goto out;
  73. }
  74. mr->order = ent->order;
  75. mr->umred = 1;
  76. mr->pas = kmalloc(size + 0x3f, GFP_KERNEL);
  77. if (!mr->pas) {
  78. kfree(mr);
  79. err = -ENOMEM;
  80. goto out;
  81. }
  82. mr->dma = dma_map_single(ddev, mr_align(mr->pas, 0x40), size,
  83. DMA_TO_DEVICE);
  84. if (dma_mapping_error(ddev, mr->dma)) {
  85. kfree(mr->pas);
  86. kfree(mr);
  87. err = -ENOMEM;
  88. goto out;
  89. }
  90. in->seg.status = 1 << 6;
  91. in->seg.xlt_oct_size = cpu_to_be32((npages + 1) / 2);
  92. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  93. in->seg.flags = MLX5_ACCESS_MODE_MTT | MLX5_PERM_UMR_EN;
  94. in->seg.log2_page_size = 12;
  95. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in,
  96. sizeof(*in));
  97. if (err) {
  98. mlx5_ib_warn(dev, "create mkey failed %d\n", err);
  99. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  100. kfree(mr->pas);
  101. kfree(mr);
  102. goto out;
  103. }
  104. cache->last_add = jiffies;
  105. spin_lock(&ent->lock);
  106. list_add_tail(&mr->list, &ent->head);
  107. ent->cur++;
  108. ent->size++;
  109. spin_unlock(&ent->lock);
  110. }
  111. out:
  112. kfree(in);
  113. return err;
  114. }
  115. static void remove_keys(struct mlx5_ib_dev *dev, int c, int num)
  116. {
  117. struct device *ddev = dev->ib_dev.dma_device;
  118. struct mlx5_mr_cache *cache = &dev->cache;
  119. struct mlx5_cache_ent *ent = &cache->ent[c];
  120. struct mlx5_ib_mr *mr;
  121. int size;
  122. int err;
  123. int i;
  124. for (i = 0; i < num; i++) {
  125. spin_lock(&ent->lock);
  126. if (list_empty(&ent->head)) {
  127. spin_unlock(&ent->lock);
  128. return;
  129. }
  130. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  131. list_del(&mr->list);
  132. ent->cur--;
  133. ent->size--;
  134. spin_unlock(&ent->lock);
  135. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  136. if (err) {
  137. mlx5_ib_warn(dev, "failed destroy mkey\n");
  138. } else {
  139. size = ALIGN(sizeof(u64) * (1 << mr->order), 0x40);
  140. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  141. kfree(mr->pas);
  142. kfree(mr);
  143. }
  144. }
  145. }
  146. static ssize_t size_write(struct file *filp, const char __user *buf,
  147. size_t count, loff_t *pos)
  148. {
  149. struct mlx5_cache_ent *ent = filp->private_data;
  150. struct mlx5_ib_dev *dev = ent->dev;
  151. char lbuf[20];
  152. u32 var;
  153. int err;
  154. int c;
  155. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  156. return -EFAULT;
  157. c = order2idx(dev, ent->order);
  158. lbuf[sizeof(lbuf) - 1] = 0;
  159. if (sscanf(lbuf, "%u", &var) != 1)
  160. return -EINVAL;
  161. if (var < ent->limit)
  162. return -EINVAL;
  163. if (var > ent->size) {
  164. err = add_keys(dev, c, var - ent->size);
  165. if (err)
  166. return err;
  167. } else if (var < ent->size) {
  168. remove_keys(dev, c, ent->size - var);
  169. }
  170. return count;
  171. }
  172. static ssize_t size_read(struct file *filp, char __user *buf, size_t count,
  173. loff_t *pos)
  174. {
  175. struct mlx5_cache_ent *ent = filp->private_data;
  176. char lbuf[20];
  177. int err;
  178. if (*pos)
  179. return 0;
  180. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->size);
  181. if (err < 0)
  182. return err;
  183. if (copy_to_user(buf, lbuf, err))
  184. return -EFAULT;
  185. *pos += err;
  186. return err;
  187. }
  188. static const struct file_operations size_fops = {
  189. .owner = THIS_MODULE,
  190. .open = simple_open,
  191. .write = size_write,
  192. .read = size_read,
  193. };
  194. static ssize_t limit_write(struct file *filp, const char __user *buf,
  195. size_t count, loff_t *pos)
  196. {
  197. struct mlx5_cache_ent *ent = filp->private_data;
  198. struct mlx5_ib_dev *dev = ent->dev;
  199. char lbuf[20];
  200. u32 var;
  201. int err;
  202. int c;
  203. if (copy_from_user(lbuf, buf, sizeof(lbuf)))
  204. return -EFAULT;
  205. c = order2idx(dev, ent->order);
  206. lbuf[sizeof(lbuf) - 1] = 0;
  207. if (sscanf(lbuf, "%u", &var) != 1)
  208. return -EINVAL;
  209. if (var > ent->size)
  210. return -EINVAL;
  211. ent->limit = var;
  212. if (ent->cur < ent->limit) {
  213. err = add_keys(dev, c, 2 * ent->limit - ent->cur);
  214. if (err)
  215. return err;
  216. }
  217. return count;
  218. }
  219. static ssize_t limit_read(struct file *filp, char __user *buf, size_t count,
  220. loff_t *pos)
  221. {
  222. struct mlx5_cache_ent *ent = filp->private_data;
  223. char lbuf[20];
  224. int err;
  225. if (*pos)
  226. return 0;
  227. err = snprintf(lbuf, sizeof(lbuf), "%d\n", ent->limit);
  228. if (err < 0)
  229. return err;
  230. if (copy_to_user(buf, lbuf, err))
  231. return -EFAULT;
  232. *pos += err;
  233. return err;
  234. }
  235. static const struct file_operations limit_fops = {
  236. .owner = THIS_MODULE,
  237. .open = simple_open,
  238. .write = limit_write,
  239. .read = limit_read,
  240. };
  241. static int someone_adding(struct mlx5_mr_cache *cache)
  242. {
  243. int i;
  244. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  245. if (cache->ent[i].cur < cache->ent[i].limit)
  246. return 1;
  247. }
  248. return 0;
  249. }
  250. static void __cache_work_func(struct mlx5_cache_ent *ent)
  251. {
  252. struct mlx5_ib_dev *dev = ent->dev;
  253. struct mlx5_mr_cache *cache = &dev->cache;
  254. int i = order2idx(dev, ent->order);
  255. if (cache->stopped)
  256. return;
  257. ent = &dev->cache.ent[i];
  258. if (ent->cur < 2 * ent->limit) {
  259. add_keys(dev, i, 1);
  260. if (ent->cur < 2 * ent->limit)
  261. queue_work(cache->wq, &ent->work);
  262. } else if (ent->cur > 2 * ent->limit) {
  263. if (!someone_adding(cache) &&
  264. time_after(jiffies, cache->last_add + 60 * HZ)) {
  265. remove_keys(dev, i, 1);
  266. if (ent->cur > ent->limit)
  267. queue_work(cache->wq, &ent->work);
  268. } else {
  269. queue_delayed_work(cache->wq, &ent->dwork, 60 * HZ);
  270. }
  271. }
  272. }
  273. static void delayed_cache_work_func(struct work_struct *work)
  274. {
  275. struct mlx5_cache_ent *ent;
  276. ent = container_of(work, struct mlx5_cache_ent, dwork.work);
  277. __cache_work_func(ent);
  278. }
  279. static void cache_work_func(struct work_struct *work)
  280. {
  281. struct mlx5_cache_ent *ent;
  282. ent = container_of(work, struct mlx5_cache_ent, work);
  283. __cache_work_func(ent);
  284. }
  285. static struct mlx5_ib_mr *alloc_cached_mr(struct mlx5_ib_dev *dev, int order)
  286. {
  287. struct mlx5_mr_cache *cache = &dev->cache;
  288. struct mlx5_ib_mr *mr = NULL;
  289. struct mlx5_cache_ent *ent;
  290. int c;
  291. int i;
  292. c = order2idx(dev, order);
  293. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  294. mlx5_ib_warn(dev, "order %d, cache index %d\n", order, c);
  295. return NULL;
  296. }
  297. for (i = c; i < MAX_MR_CACHE_ENTRIES; i++) {
  298. ent = &cache->ent[i];
  299. mlx5_ib_dbg(dev, "order %d, cache index %d\n", ent->order, i);
  300. spin_lock(&ent->lock);
  301. if (!list_empty(&ent->head)) {
  302. mr = list_first_entry(&ent->head, struct mlx5_ib_mr,
  303. list);
  304. list_del(&mr->list);
  305. ent->cur--;
  306. spin_unlock(&ent->lock);
  307. if (ent->cur < ent->limit)
  308. queue_work(cache->wq, &ent->work);
  309. break;
  310. }
  311. spin_unlock(&ent->lock);
  312. queue_work(cache->wq, &ent->work);
  313. if (mr)
  314. break;
  315. }
  316. if (!mr)
  317. cache->ent[c].miss++;
  318. return mr;
  319. }
  320. static void free_cached_mr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  321. {
  322. struct mlx5_mr_cache *cache = &dev->cache;
  323. struct mlx5_cache_ent *ent;
  324. int shrink = 0;
  325. int c;
  326. c = order2idx(dev, mr->order);
  327. if (c < 0 || c >= MAX_MR_CACHE_ENTRIES) {
  328. mlx5_ib_warn(dev, "order %d, cache index %d\n", mr->order, c);
  329. return;
  330. }
  331. ent = &cache->ent[c];
  332. spin_lock(&ent->lock);
  333. list_add_tail(&mr->list, &ent->head);
  334. ent->cur++;
  335. if (ent->cur > 2 * ent->limit)
  336. shrink = 1;
  337. spin_unlock(&ent->lock);
  338. if (shrink)
  339. queue_work(cache->wq, &ent->work);
  340. }
  341. static void clean_keys(struct mlx5_ib_dev *dev, int c)
  342. {
  343. struct device *ddev = dev->ib_dev.dma_device;
  344. struct mlx5_mr_cache *cache = &dev->cache;
  345. struct mlx5_cache_ent *ent = &cache->ent[c];
  346. struct mlx5_ib_mr *mr;
  347. int size;
  348. int err;
  349. while (1) {
  350. spin_lock(&ent->lock);
  351. if (list_empty(&ent->head)) {
  352. spin_unlock(&ent->lock);
  353. return;
  354. }
  355. mr = list_first_entry(&ent->head, struct mlx5_ib_mr, list);
  356. list_del(&mr->list);
  357. ent->cur--;
  358. ent->size--;
  359. spin_unlock(&ent->lock);
  360. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  361. if (err) {
  362. mlx5_ib_warn(dev, "failed destroy mkey\n");
  363. } else {
  364. size = ALIGN(sizeof(u64) * (1 << mr->order), 0x40);
  365. dma_unmap_single(ddev, mr->dma, size, DMA_TO_DEVICE);
  366. kfree(mr->pas);
  367. kfree(mr);
  368. }
  369. }
  370. }
  371. static int mlx5_mr_cache_debugfs_init(struct mlx5_ib_dev *dev)
  372. {
  373. struct mlx5_mr_cache *cache = &dev->cache;
  374. struct mlx5_cache_ent *ent;
  375. int i;
  376. if (!mlx5_debugfs_root)
  377. return 0;
  378. cache->root = debugfs_create_dir("mr_cache", dev->mdev.priv.dbg_root);
  379. if (!cache->root)
  380. return -ENOMEM;
  381. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  382. ent = &cache->ent[i];
  383. sprintf(ent->name, "%d", ent->order);
  384. ent->dir = debugfs_create_dir(ent->name, cache->root);
  385. if (!ent->dir)
  386. return -ENOMEM;
  387. ent->fsize = debugfs_create_file("size", 0600, ent->dir, ent,
  388. &size_fops);
  389. if (!ent->fsize)
  390. return -ENOMEM;
  391. ent->flimit = debugfs_create_file("limit", 0600, ent->dir, ent,
  392. &limit_fops);
  393. if (!ent->flimit)
  394. return -ENOMEM;
  395. ent->fcur = debugfs_create_u32("cur", 0400, ent->dir,
  396. &ent->cur);
  397. if (!ent->fcur)
  398. return -ENOMEM;
  399. ent->fmiss = debugfs_create_u32("miss", 0600, ent->dir,
  400. &ent->miss);
  401. if (!ent->fmiss)
  402. return -ENOMEM;
  403. }
  404. return 0;
  405. }
  406. static void mlx5_mr_cache_debugfs_cleanup(struct mlx5_ib_dev *dev)
  407. {
  408. if (!mlx5_debugfs_root)
  409. return;
  410. debugfs_remove_recursive(dev->cache.root);
  411. }
  412. int mlx5_mr_cache_init(struct mlx5_ib_dev *dev)
  413. {
  414. struct mlx5_mr_cache *cache = &dev->cache;
  415. struct mlx5_cache_ent *ent;
  416. int limit;
  417. int size;
  418. int err;
  419. int i;
  420. cache->wq = create_singlethread_workqueue("mkey_cache");
  421. if (!cache->wq) {
  422. mlx5_ib_warn(dev, "failed to create work queue\n");
  423. return -ENOMEM;
  424. }
  425. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++) {
  426. INIT_LIST_HEAD(&cache->ent[i].head);
  427. spin_lock_init(&cache->ent[i].lock);
  428. ent = &cache->ent[i];
  429. INIT_LIST_HEAD(&ent->head);
  430. spin_lock_init(&ent->lock);
  431. ent->order = i + 2;
  432. ent->dev = dev;
  433. if (dev->mdev.profile->mask & MLX5_PROF_MASK_MR_CACHE) {
  434. size = dev->mdev.profile->mr_cache[i].size;
  435. limit = dev->mdev.profile->mr_cache[i].limit;
  436. } else {
  437. size = DEF_CACHE_SIZE;
  438. limit = 0;
  439. }
  440. INIT_WORK(&ent->work, cache_work_func);
  441. INIT_DELAYED_WORK(&ent->dwork, delayed_cache_work_func);
  442. ent->limit = limit;
  443. queue_work(cache->wq, &ent->work);
  444. }
  445. err = mlx5_mr_cache_debugfs_init(dev);
  446. if (err)
  447. mlx5_ib_warn(dev, "cache debugfs failure\n");
  448. return 0;
  449. }
  450. int mlx5_mr_cache_cleanup(struct mlx5_ib_dev *dev)
  451. {
  452. int i;
  453. dev->cache.stopped = 1;
  454. destroy_workqueue(dev->cache.wq);
  455. mlx5_mr_cache_debugfs_cleanup(dev);
  456. for (i = 0; i < MAX_MR_CACHE_ENTRIES; i++)
  457. clean_keys(dev, i);
  458. return 0;
  459. }
  460. struct ib_mr *mlx5_ib_get_dma_mr(struct ib_pd *pd, int acc)
  461. {
  462. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  463. struct mlx5_core_dev *mdev = &dev->mdev;
  464. struct mlx5_create_mkey_mbox_in *in;
  465. struct mlx5_mkey_seg *seg;
  466. struct mlx5_ib_mr *mr;
  467. int err;
  468. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  469. if (!mr)
  470. return ERR_PTR(-ENOMEM);
  471. in = kzalloc(sizeof(*in), GFP_KERNEL);
  472. if (!in) {
  473. err = -ENOMEM;
  474. goto err_free;
  475. }
  476. seg = &in->seg;
  477. seg->flags = convert_access(acc) | MLX5_ACCESS_MODE_PA;
  478. seg->flags_pd = cpu_to_be32(to_mpd(pd)->pdn | MLX5_MKEY_LEN64);
  479. seg->qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  480. seg->start_addr = 0;
  481. err = mlx5_core_create_mkey(mdev, &mr->mmr, in, sizeof(*in));
  482. if (err)
  483. goto err_in;
  484. kfree(in);
  485. mr->ibmr.lkey = mr->mmr.key;
  486. mr->ibmr.rkey = mr->mmr.key;
  487. mr->umem = NULL;
  488. return &mr->ibmr;
  489. err_in:
  490. kfree(in);
  491. err_free:
  492. kfree(mr);
  493. return ERR_PTR(err);
  494. }
  495. static int get_octo_len(u64 addr, u64 len, int page_size)
  496. {
  497. u64 offset;
  498. int npages;
  499. offset = addr & (page_size - 1);
  500. npages = ALIGN(len + offset, page_size) >> ilog2(page_size);
  501. return (npages + 1) / 2;
  502. }
  503. static int use_umr(int order)
  504. {
  505. return order <= 17;
  506. }
  507. static void prep_umr_reg_wqe(struct ib_pd *pd, struct ib_send_wr *wr,
  508. struct ib_sge *sg, u64 dma, int n, u32 key,
  509. int page_shift, u64 virt_addr, u64 len,
  510. int access_flags)
  511. {
  512. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  513. struct ib_mr *mr = dev->umrc.mr;
  514. sg->addr = dma;
  515. sg->length = ALIGN(sizeof(u64) * n, 64);
  516. sg->lkey = mr->lkey;
  517. wr->next = NULL;
  518. wr->send_flags = 0;
  519. wr->sg_list = sg;
  520. if (n)
  521. wr->num_sge = 1;
  522. else
  523. wr->num_sge = 0;
  524. wr->opcode = MLX5_IB_WR_UMR;
  525. wr->wr.fast_reg.page_list_len = n;
  526. wr->wr.fast_reg.page_shift = page_shift;
  527. wr->wr.fast_reg.rkey = key;
  528. wr->wr.fast_reg.iova_start = virt_addr;
  529. wr->wr.fast_reg.length = len;
  530. wr->wr.fast_reg.access_flags = access_flags;
  531. wr->wr.fast_reg.page_list = (struct ib_fast_reg_page_list *)pd;
  532. }
  533. static void prep_umr_unreg_wqe(struct mlx5_ib_dev *dev,
  534. struct ib_send_wr *wr, u32 key)
  535. {
  536. wr->send_flags = MLX5_IB_SEND_UMR_UNREG;
  537. wr->opcode = MLX5_IB_WR_UMR;
  538. wr->wr.fast_reg.rkey = key;
  539. }
  540. void mlx5_umr_cq_handler(struct ib_cq *cq, void *cq_context)
  541. {
  542. struct mlx5_ib_mr *mr;
  543. struct ib_wc wc;
  544. int err;
  545. while (1) {
  546. err = ib_poll_cq(cq, 1, &wc);
  547. if (err < 0) {
  548. pr_warn("poll cq error %d\n", err);
  549. return;
  550. }
  551. if (err == 0)
  552. break;
  553. mr = (struct mlx5_ib_mr *)(unsigned long)wc.wr_id;
  554. mr->status = wc.status;
  555. complete(&mr->done);
  556. }
  557. ib_req_notify_cq(cq, IB_CQ_NEXT_COMP);
  558. }
  559. static struct mlx5_ib_mr *reg_umr(struct ib_pd *pd, struct ib_umem *umem,
  560. u64 virt_addr, u64 len, int npages,
  561. int page_shift, int order, int access_flags)
  562. {
  563. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  564. struct umr_common *umrc = &dev->umrc;
  565. struct ib_send_wr wr, *bad;
  566. struct mlx5_ib_mr *mr;
  567. struct ib_sge sg;
  568. int err;
  569. int i;
  570. for (i = 0; i < 10; i++) {
  571. mr = alloc_cached_mr(dev, order);
  572. if (mr)
  573. break;
  574. err = add_keys(dev, order2idx(dev, order), 1);
  575. if (err) {
  576. mlx5_ib_warn(dev, "add_keys failed\n");
  577. break;
  578. }
  579. }
  580. if (!mr)
  581. return ERR_PTR(-EAGAIN);
  582. mlx5_ib_populate_pas(dev, umem, page_shift, mr_align(mr->pas, 0x40), 1);
  583. memset(&wr, 0, sizeof(wr));
  584. wr.wr_id = (u64)(unsigned long)mr;
  585. prep_umr_reg_wqe(pd, &wr, &sg, mr->dma, npages, mr->mmr.key, page_shift, virt_addr, len, access_flags);
  586. /* We serialize polls so one process does not kidnap another's
  587. * completion. This is not a problem since wr is completed in
  588. * around 1 usec
  589. */
  590. down(&umrc->sem);
  591. init_completion(&mr->done);
  592. err = ib_post_send(umrc->qp, &wr, &bad);
  593. if (err) {
  594. mlx5_ib_warn(dev, "post send failed, err %d\n", err);
  595. up(&umrc->sem);
  596. goto error;
  597. }
  598. wait_for_completion(&mr->done);
  599. up(&umrc->sem);
  600. if (mr->status != IB_WC_SUCCESS) {
  601. mlx5_ib_warn(dev, "reg umr failed\n");
  602. err = -EFAULT;
  603. goto error;
  604. }
  605. return mr;
  606. error:
  607. free_cached_mr(dev, mr);
  608. return ERR_PTR(err);
  609. }
  610. static struct mlx5_ib_mr *reg_create(struct ib_pd *pd, u64 virt_addr,
  611. u64 length, struct ib_umem *umem,
  612. int npages, int page_shift,
  613. int access_flags)
  614. {
  615. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  616. struct mlx5_create_mkey_mbox_in *in;
  617. struct mlx5_ib_mr *mr;
  618. int inlen;
  619. int err;
  620. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  621. if (!mr)
  622. return ERR_PTR(-ENOMEM);
  623. inlen = sizeof(*in) + sizeof(*in->pas) * ((npages + 1) / 2) * 2;
  624. in = mlx5_vzalloc(inlen);
  625. if (!in) {
  626. err = -ENOMEM;
  627. goto err_1;
  628. }
  629. mlx5_ib_populate_pas(dev, umem, page_shift, in->pas, 0);
  630. in->seg.flags = convert_access(access_flags) |
  631. MLX5_ACCESS_MODE_MTT;
  632. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  633. in->seg.start_addr = cpu_to_be64(virt_addr);
  634. in->seg.len = cpu_to_be64(length);
  635. in->seg.bsfs_octo_size = 0;
  636. in->seg.xlt_oct_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  637. in->seg.log2_page_size = page_shift;
  638. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  639. in->xlat_oct_act_size = cpu_to_be32(get_octo_len(virt_addr, length, 1 << page_shift));
  640. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, inlen);
  641. if (err) {
  642. mlx5_ib_warn(dev, "create mkey failed\n");
  643. goto err_2;
  644. }
  645. mr->umem = umem;
  646. mlx5_vfree(in);
  647. mlx5_ib_dbg(dev, "mkey = 0x%x\n", mr->mmr.key);
  648. return mr;
  649. err_2:
  650. mlx5_vfree(in);
  651. err_1:
  652. kfree(mr);
  653. return ERR_PTR(err);
  654. }
  655. struct ib_mr *mlx5_ib_reg_user_mr(struct ib_pd *pd, u64 start, u64 length,
  656. u64 virt_addr, int access_flags,
  657. struct ib_udata *udata)
  658. {
  659. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  660. struct mlx5_ib_mr *mr = NULL;
  661. struct ib_umem *umem;
  662. int page_shift;
  663. int npages;
  664. int ncont;
  665. int order;
  666. int err;
  667. mlx5_ib_dbg(dev, "start 0x%llx, virt_addr 0x%llx, length 0x%llx\n",
  668. start, virt_addr, length);
  669. umem = ib_umem_get(pd->uobject->context, start, length, access_flags,
  670. 0);
  671. if (IS_ERR(umem)) {
  672. mlx5_ib_dbg(dev, "umem get failed\n");
  673. return (void *)umem;
  674. }
  675. mlx5_ib_cont_pages(umem, start, &npages, &page_shift, &ncont, &order);
  676. if (!npages) {
  677. mlx5_ib_warn(dev, "avoid zero region\n");
  678. err = -EINVAL;
  679. goto error;
  680. }
  681. mlx5_ib_dbg(dev, "npages %d, ncont %d, order %d, page_shift %d\n",
  682. npages, ncont, order, page_shift);
  683. if (use_umr(order)) {
  684. mr = reg_umr(pd, umem, virt_addr, length, ncont, page_shift,
  685. order, access_flags);
  686. if (PTR_ERR(mr) == -EAGAIN) {
  687. mlx5_ib_dbg(dev, "cache empty for order %d", order);
  688. mr = NULL;
  689. }
  690. }
  691. if (!mr)
  692. mr = reg_create(pd, virt_addr, length, umem, ncont, page_shift,
  693. access_flags);
  694. if (IS_ERR(mr)) {
  695. err = PTR_ERR(mr);
  696. goto error;
  697. }
  698. mlx5_ib_dbg(dev, "mkey 0x%x\n", mr->mmr.key);
  699. mr->umem = umem;
  700. mr->npages = npages;
  701. spin_lock(&dev->mr_lock);
  702. dev->mdev.priv.reg_pages += npages;
  703. spin_unlock(&dev->mr_lock);
  704. mr->ibmr.lkey = mr->mmr.key;
  705. mr->ibmr.rkey = mr->mmr.key;
  706. return &mr->ibmr;
  707. error:
  708. ib_umem_release(umem);
  709. return ERR_PTR(err);
  710. }
  711. static int unreg_umr(struct mlx5_ib_dev *dev, struct mlx5_ib_mr *mr)
  712. {
  713. struct umr_common *umrc = &dev->umrc;
  714. struct ib_send_wr wr, *bad;
  715. int err;
  716. memset(&wr, 0, sizeof(wr));
  717. wr.wr_id = (u64)(unsigned long)mr;
  718. prep_umr_unreg_wqe(dev, &wr, mr->mmr.key);
  719. down(&umrc->sem);
  720. init_completion(&mr->done);
  721. err = ib_post_send(umrc->qp, &wr, &bad);
  722. if (err) {
  723. up(&umrc->sem);
  724. mlx5_ib_dbg(dev, "err %d\n", err);
  725. goto error;
  726. }
  727. wait_for_completion(&mr->done);
  728. up(&umrc->sem);
  729. if (mr->status != IB_WC_SUCCESS) {
  730. mlx5_ib_warn(dev, "unreg umr failed\n");
  731. err = -EFAULT;
  732. goto error;
  733. }
  734. return 0;
  735. error:
  736. return err;
  737. }
  738. int mlx5_ib_dereg_mr(struct ib_mr *ibmr)
  739. {
  740. struct mlx5_ib_dev *dev = to_mdev(ibmr->device);
  741. struct mlx5_ib_mr *mr = to_mmr(ibmr);
  742. struct ib_umem *umem = mr->umem;
  743. int npages = mr->npages;
  744. int umred = mr->umred;
  745. int err;
  746. if (!umred) {
  747. err = mlx5_core_destroy_mkey(&dev->mdev, &mr->mmr);
  748. if (err) {
  749. mlx5_ib_warn(dev, "failed to destroy mkey 0x%x (%d)\n",
  750. mr->mmr.key, err);
  751. return err;
  752. }
  753. } else {
  754. err = unreg_umr(dev, mr);
  755. if (err) {
  756. mlx5_ib_warn(dev, "failed unregister\n");
  757. return err;
  758. }
  759. free_cached_mr(dev, mr);
  760. }
  761. if (umem) {
  762. ib_umem_release(umem);
  763. spin_lock(&dev->mr_lock);
  764. dev->mdev.priv.reg_pages -= npages;
  765. spin_unlock(&dev->mr_lock);
  766. }
  767. if (!umred)
  768. kfree(mr);
  769. return 0;
  770. }
  771. struct ib_mr *mlx5_ib_alloc_fast_reg_mr(struct ib_pd *pd,
  772. int max_page_list_len)
  773. {
  774. struct mlx5_ib_dev *dev = to_mdev(pd->device);
  775. struct mlx5_create_mkey_mbox_in *in;
  776. struct mlx5_ib_mr *mr;
  777. int err;
  778. mr = kzalloc(sizeof(*mr), GFP_KERNEL);
  779. if (!mr)
  780. return ERR_PTR(-ENOMEM);
  781. in = kzalloc(sizeof(*in), GFP_KERNEL);
  782. if (!in) {
  783. err = -ENOMEM;
  784. goto err_free;
  785. }
  786. in->seg.status = 1 << 6; /* free */
  787. in->seg.xlt_oct_size = cpu_to_be32((max_page_list_len + 1) / 2);
  788. in->seg.qpn_mkey7_0 = cpu_to_be32(0xffffff << 8);
  789. in->seg.flags = MLX5_PERM_UMR_EN | MLX5_ACCESS_MODE_MTT;
  790. in->seg.flags_pd = cpu_to_be32(to_mpd(pd)->pdn);
  791. /*
  792. * TBD not needed - issue 197292 */
  793. in->seg.log2_page_size = PAGE_SHIFT;
  794. err = mlx5_core_create_mkey(&dev->mdev, &mr->mmr, in, sizeof(*in));
  795. kfree(in);
  796. if (err)
  797. goto err_free;
  798. mr->ibmr.lkey = mr->mmr.key;
  799. mr->ibmr.rkey = mr->mmr.key;
  800. mr->umem = NULL;
  801. return &mr->ibmr;
  802. err_free:
  803. kfree(mr);
  804. return ERR_PTR(err);
  805. }
  806. struct ib_fast_reg_page_list *mlx5_ib_alloc_fast_reg_page_list(struct ib_device *ibdev,
  807. int page_list_len)
  808. {
  809. struct mlx5_ib_fast_reg_page_list *mfrpl;
  810. int size = page_list_len * sizeof(u64);
  811. mfrpl = kmalloc(sizeof(*mfrpl), GFP_KERNEL);
  812. if (!mfrpl)
  813. return ERR_PTR(-ENOMEM);
  814. mfrpl->ibfrpl.page_list = kmalloc(size, GFP_KERNEL);
  815. if (!mfrpl->ibfrpl.page_list)
  816. goto err_free;
  817. mfrpl->mapped_page_list = dma_alloc_coherent(ibdev->dma_device,
  818. size, &mfrpl->map,
  819. GFP_KERNEL);
  820. if (!mfrpl->mapped_page_list)
  821. goto err_free;
  822. WARN_ON(mfrpl->map & 0x3f);
  823. return &mfrpl->ibfrpl;
  824. err_free:
  825. kfree(mfrpl->ibfrpl.page_list);
  826. kfree(mfrpl);
  827. return ERR_PTR(-ENOMEM);
  828. }
  829. void mlx5_ib_free_fast_reg_page_list(struct ib_fast_reg_page_list *page_list)
  830. {
  831. struct mlx5_ib_fast_reg_page_list *mfrpl = to_mfrpl(page_list);
  832. struct mlx5_ib_dev *dev = to_mdev(page_list->device);
  833. int size = page_list->max_page_list_len * sizeof(u64);
  834. dma_free_coherent(&dev->mdev.pdev->dev, size, mfrpl->mapped_page_list,
  835. mfrpl->map);
  836. kfree(mfrpl->ibfrpl.page_list);
  837. kfree(mfrpl);
  838. }