qp.c 48 KB

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  1. /*
  2. * Copyright (c) 2009-2010 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include <linux/module.h>
  33. #include "iw_cxgb4.h"
  34. static int db_delay_usecs = 1;
  35. module_param(db_delay_usecs, int, 0644);
  36. MODULE_PARM_DESC(db_delay_usecs, "Usecs to delay awaiting db fifo to drain");
  37. static int ocqp_support = 1;
  38. module_param(ocqp_support, int, 0644);
  39. MODULE_PARM_DESC(ocqp_support, "Support on-chip SQs (default=1)");
  40. int db_fc_threshold = 1000;
  41. module_param(db_fc_threshold, int, 0644);
  42. MODULE_PARM_DESC(db_fc_threshold,
  43. "QP count/threshold that triggers"
  44. " automatic db flow control mode (default = 1000)");
  45. int db_coalescing_threshold;
  46. module_param(db_coalescing_threshold, int, 0644);
  47. MODULE_PARM_DESC(db_coalescing_threshold,
  48. "QP count/threshold that triggers"
  49. " disabling db coalescing (default = 0)");
  50. static int max_fr_immd = T4_MAX_FR_IMMD;
  51. module_param(max_fr_immd, int, 0644);
  52. MODULE_PARM_DESC(max_fr_immd, "fastreg threshold for using DSGL instead of immedate");
  53. static void set_state(struct c4iw_qp *qhp, enum c4iw_qp_state state)
  54. {
  55. unsigned long flag;
  56. spin_lock_irqsave(&qhp->lock, flag);
  57. qhp->attr.state = state;
  58. spin_unlock_irqrestore(&qhp->lock, flag);
  59. }
  60. static void dealloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  61. {
  62. c4iw_ocqp_pool_free(rdev, sq->dma_addr, sq->memsize);
  63. }
  64. static void dealloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  65. {
  66. dma_free_coherent(&(rdev->lldi.pdev->dev), sq->memsize, sq->queue,
  67. pci_unmap_addr(sq, mapping));
  68. }
  69. static void dealloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  70. {
  71. if (t4_sq_onchip(sq))
  72. dealloc_oc_sq(rdev, sq);
  73. else
  74. dealloc_host_sq(rdev, sq);
  75. }
  76. static int alloc_oc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  77. {
  78. if (!ocqp_support || !ocqp_supported(&rdev->lldi))
  79. return -ENOSYS;
  80. sq->dma_addr = c4iw_ocqp_pool_alloc(rdev, sq->memsize);
  81. if (!sq->dma_addr)
  82. return -ENOMEM;
  83. sq->phys_addr = rdev->oc_mw_pa + sq->dma_addr -
  84. rdev->lldi.vr->ocq.start;
  85. sq->queue = (__force union t4_wr *)(rdev->oc_mw_kva + sq->dma_addr -
  86. rdev->lldi.vr->ocq.start);
  87. sq->flags |= T4_SQ_ONCHIP;
  88. return 0;
  89. }
  90. static int alloc_host_sq(struct c4iw_rdev *rdev, struct t4_sq *sq)
  91. {
  92. sq->queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev), sq->memsize,
  93. &(sq->dma_addr), GFP_KERNEL);
  94. if (!sq->queue)
  95. return -ENOMEM;
  96. sq->phys_addr = virt_to_phys(sq->queue);
  97. pci_unmap_addr_set(sq, mapping, sq->dma_addr);
  98. return 0;
  99. }
  100. static int alloc_sq(struct c4iw_rdev *rdev, struct t4_sq *sq, int user)
  101. {
  102. int ret = -ENOSYS;
  103. if (user)
  104. ret = alloc_oc_sq(rdev, sq);
  105. if (ret)
  106. ret = alloc_host_sq(rdev, sq);
  107. return ret;
  108. }
  109. static int destroy_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
  110. struct c4iw_dev_ucontext *uctx)
  111. {
  112. /*
  113. * uP clears EQ contexts when the connection exits rdma mode,
  114. * so no need to post a RESET WR for these EQs.
  115. */
  116. dma_free_coherent(&(rdev->lldi.pdev->dev),
  117. wq->rq.memsize, wq->rq.queue,
  118. dma_unmap_addr(&wq->rq, mapping));
  119. dealloc_sq(rdev, &wq->sq);
  120. c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
  121. kfree(wq->rq.sw_rq);
  122. kfree(wq->sq.sw_sq);
  123. c4iw_put_qpid(rdev, wq->rq.qid, uctx);
  124. c4iw_put_qpid(rdev, wq->sq.qid, uctx);
  125. return 0;
  126. }
  127. static int create_qp(struct c4iw_rdev *rdev, struct t4_wq *wq,
  128. struct t4_cq *rcq, struct t4_cq *scq,
  129. struct c4iw_dev_ucontext *uctx)
  130. {
  131. int user = (uctx != &rdev->uctx);
  132. struct fw_ri_res_wr *res_wr;
  133. struct fw_ri_res *res;
  134. int wr_len;
  135. struct c4iw_wr_wait wr_wait;
  136. struct sk_buff *skb;
  137. int ret = 0;
  138. int eqsize;
  139. wq->sq.qid = c4iw_get_qpid(rdev, uctx);
  140. if (!wq->sq.qid)
  141. return -ENOMEM;
  142. wq->rq.qid = c4iw_get_qpid(rdev, uctx);
  143. if (!wq->rq.qid) {
  144. ret = -ENOMEM;
  145. goto free_sq_qid;
  146. }
  147. if (!user) {
  148. wq->sq.sw_sq = kzalloc(wq->sq.size * sizeof *wq->sq.sw_sq,
  149. GFP_KERNEL);
  150. if (!wq->sq.sw_sq) {
  151. ret = -ENOMEM;
  152. goto free_rq_qid;
  153. }
  154. wq->rq.sw_rq = kzalloc(wq->rq.size * sizeof *wq->rq.sw_rq,
  155. GFP_KERNEL);
  156. if (!wq->rq.sw_rq) {
  157. ret = -ENOMEM;
  158. goto free_sw_sq;
  159. }
  160. }
  161. /*
  162. * RQT must be a power of 2.
  163. */
  164. wq->rq.rqt_size = roundup_pow_of_two(wq->rq.size);
  165. wq->rq.rqt_hwaddr = c4iw_rqtpool_alloc(rdev, wq->rq.rqt_size);
  166. if (!wq->rq.rqt_hwaddr) {
  167. ret = -ENOMEM;
  168. goto free_sw_rq;
  169. }
  170. ret = alloc_sq(rdev, &wq->sq, user);
  171. if (ret)
  172. goto free_hwaddr;
  173. memset(wq->sq.queue, 0, wq->sq.memsize);
  174. dma_unmap_addr_set(&wq->sq, mapping, wq->sq.dma_addr);
  175. wq->rq.queue = dma_alloc_coherent(&(rdev->lldi.pdev->dev),
  176. wq->rq.memsize, &(wq->rq.dma_addr),
  177. GFP_KERNEL);
  178. if (!wq->rq.queue) {
  179. ret = -ENOMEM;
  180. goto free_sq;
  181. }
  182. PDBG("%s sq base va 0x%p pa 0x%llx rq base va 0x%p pa 0x%llx\n",
  183. __func__, wq->sq.queue,
  184. (unsigned long long)virt_to_phys(wq->sq.queue),
  185. wq->rq.queue,
  186. (unsigned long long)virt_to_phys(wq->rq.queue));
  187. memset(wq->rq.queue, 0, wq->rq.memsize);
  188. dma_unmap_addr_set(&wq->rq, mapping, wq->rq.dma_addr);
  189. wq->db = rdev->lldi.db_reg;
  190. wq->gts = rdev->lldi.gts_reg;
  191. if (user) {
  192. wq->sq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
  193. (wq->sq.qid << rdev->qpshift);
  194. wq->sq.udb &= PAGE_MASK;
  195. wq->rq.udb = (u64)pci_resource_start(rdev->lldi.pdev, 2) +
  196. (wq->rq.qid << rdev->qpshift);
  197. wq->rq.udb &= PAGE_MASK;
  198. }
  199. wq->rdev = rdev;
  200. wq->rq.msn = 1;
  201. /* build fw_ri_res_wr */
  202. wr_len = sizeof *res_wr + 2 * sizeof *res;
  203. skb = alloc_skb(wr_len, GFP_KERNEL);
  204. if (!skb) {
  205. ret = -ENOMEM;
  206. goto free_dma;
  207. }
  208. set_wr_txq(skb, CPL_PRIORITY_CONTROL, 0);
  209. res_wr = (struct fw_ri_res_wr *)__skb_put(skb, wr_len);
  210. memset(res_wr, 0, wr_len);
  211. res_wr->op_nres = cpu_to_be32(
  212. FW_WR_OP(FW_RI_RES_WR) |
  213. V_FW_RI_RES_WR_NRES(2) |
  214. FW_WR_COMPL(1));
  215. res_wr->len16_pkd = cpu_to_be32(DIV_ROUND_UP(wr_len, 16));
  216. res_wr->cookie = (unsigned long) &wr_wait;
  217. res = res_wr->res;
  218. res->u.sqrq.restype = FW_RI_RES_TYPE_SQ;
  219. res->u.sqrq.op = FW_RI_RES_OP_WRITE;
  220. /*
  221. * eqsize is the number of 64B entries plus the status page size.
  222. */
  223. eqsize = wq->sq.size * T4_SQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
  224. res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
  225. V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
  226. V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
  227. V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
  228. (t4_sq_onchip(&wq->sq) ? F_FW_RI_RES_WR_ONCHIP : 0) |
  229. V_FW_RI_RES_WR_IQID(scq->cqid));
  230. res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
  231. V_FW_RI_RES_WR_DCAEN(0) |
  232. V_FW_RI_RES_WR_DCACPU(0) |
  233. V_FW_RI_RES_WR_FBMIN(2) |
  234. V_FW_RI_RES_WR_FBMAX(2) |
  235. V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
  236. V_FW_RI_RES_WR_CIDXFTHRESH(0) |
  237. V_FW_RI_RES_WR_EQSIZE(eqsize));
  238. res->u.sqrq.eqid = cpu_to_be32(wq->sq.qid);
  239. res->u.sqrq.eqaddr = cpu_to_be64(wq->sq.dma_addr);
  240. res++;
  241. res->u.sqrq.restype = FW_RI_RES_TYPE_RQ;
  242. res->u.sqrq.op = FW_RI_RES_OP_WRITE;
  243. /*
  244. * eqsize is the number of 64B entries plus the status page size.
  245. */
  246. eqsize = wq->rq.size * T4_RQ_NUM_SLOTS + T4_EQ_STATUS_ENTRIES;
  247. res->u.sqrq.fetchszm_to_iqid = cpu_to_be32(
  248. V_FW_RI_RES_WR_HOSTFCMODE(0) | /* no host cidx updates */
  249. V_FW_RI_RES_WR_CPRIO(0) | /* don't keep in chip cache */
  250. V_FW_RI_RES_WR_PCIECHN(0) | /* set by uP at ri_init time */
  251. V_FW_RI_RES_WR_IQID(rcq->cqid));
  252. res->u.sqrq.dcaen_to_eqsize = cpu_to_be32(
  253. V_FW_RI_RES_WR_DCAEN(0) |
  254. V_FW_RI_RES_WR_DCACPU(0) |
  255. V_FW_RI_RES_WR_FBMIN(2) |
  256. V_FW_RI_RES_WR_FBMAX(2) |
  257. V_FW_RI_RES_WR_CIDXFTHRESHO(0) |
  258. V_FW_RI_RES_WR_CIDXFTHRESH(0) |
  259. V_FW_RI_RES_WR_EQSIZE(eqsize));
  260. res->u.sqrq.eqid = cpu_to_be32(wq->rq.qid);
  261. res->u.sqrq.eqaddr = cpu_to_be64(wq->rq.dma_addr);
  262. c4iw_init_wr_wait(&wr_wait);
  263. ret = c4iw_ofld_send(rdev, skb);
  264. if (ret)
  265. goto free_dma;
  266. ret = c4iw_wait_for_reply(rdev, &wr_wait, 0, wq->sq.qid, __func__);
  267. if (ret)
  268. goto free_dma;
  269. PDBG("%s sqid 0x%x rqid 0x%x kdb 0x%p squdb 0x%llx rqudb 0x%llx\n",
  270. __func__, wq->sq.qid, wq->rq.qid, wq->db,
  271. (unsigned long long)wq->sq.udb, (unsigned long long)wq->rq.udb);
  272. return 0;
  273. free_dma:
  274. dma_free_coherent(&(rdev->lldi.pdev->dev),
  275. wq->rq.memsize, wq->rq.queue,
  276. dma_unmap_addr(&wq->rq, mapping));
  277. free_sq:
  278. dealloc_sq(rdev, &wq->sq);
  279. free_hwaddr:
  280. c4iw_rqtpool_free(rdev, wq->rq.rqt_hwaddr, wq->rq.rqt_size);
  281. free_sw_rq:
  282. kfree(wq->rq.sw_rq);
  283. free_sw_sq:
  284. kfree(wq->sq.sw_sq);
  285. free_rq_qid:
  286. c4iw_put_qpid(rdev, wq->rq.qid, uctx);
  287. free_sq_qid:
  288. c4iw_put_qpid(rdev, wq->sq.qid, uctx);
  289. return ret;
  290. }
  291. static int build_immd(struct t4_sq *sq, struct fw_ri_immd *immdp,
  292. struct ib_send_wr *wr, int max, u32 *plenp)
  293. {
  294. u8 *dstp, *srcp;
  295. u32 plen = 0;
  296. int i;
  297. int rem, len;
  298. dstp = (u8 *)immdp->data;
  299. for (i = 0; i < wr->num_sge; i++) {
  300. if ((plen + wr->sg_list[i].length) > max)
  301. return -EMSGSIZE;
  302. srcp = (u8 *)(unsigned long)wr->sg_list[i].addr;
  303. plen += wr->sg_list[i].length;
  304. rem = wr->sg_list[i].length;
  305. while (rem) {
  306. if (dstp == (u8 *)&sq->queue[sq->size])
  307. dstp = (u8 *)sq->queue;
  308. if (rem <= (u8 *)&sq->queue[sq->size] - dstp)
  309. len = rem;
  310. else
  311. len = (u8 *)&sq->queue[sq->size] - dstp;
  312. memcpy(dstp, srcp, len);
  313. dstp += len;
  314. srcp += len;
  315. rem -= len;
  316. }
  317. }
  318. len = roundup(plen + sizeof *immdp, 16) - (plen + sizeof *immdp);
  319. if (len)
  320. memset(dstp, 0, len);
  321. immdp->op = FW_RI_DATA_IMMD;
  322. immdp->r1 = 0;
  323. immdp->r2 = 0;
  324. immdp->immdlen = cpu_to_be32(plen);
  325. *plenp = plen;
  326. return 0;
  327. }
  328. static int build_isgl(__be64 *queue_start, __be64 *queue_end,
  329. struct fw_ri_isgl *isglp, struct ib_sge *sg_list,
  330. int num_sge, u32 *plenp)
  331. {
  332. int i;
  333. u32 plen = 0;
  334. __be64 *flitp = (__be64 *)isglp->sge;
  335. for (i = 0; i < num_sge; i++) {
  336. if ((plen + sg_list[i].length) < plen)
  337. return -EMSGSIZE;
  338. plen += sg_list[i].length;
  339. *flitp = cpu_to_be64(((u64)sg_list[i].lkey << 32) |
  340. sg_list[i].length);
  341. if (++flitp == queue_end)
  342. flitp = queue_start;
  343. *flitp = cpu_to_be64(sg_list[i].addr);
  344. if (++flitp == queue_end)
  345. flitp = queue_start;
  346. }
  347. *flitp = (__force __be64)0;
  348. isglp->op = FW_RI_DATA_ISGL;
  349. isglp->r1 = 0;
  350. isglp->nsge = cpu_to_be16(num_sge);
  351. isglp->r2 = 0;
  352. if (plenp)
  353. *plenp = plen;
  354. return 0;
  355. }
  356. static int build_rdma_send(struct t4_sq *sq, union t4_wr *wqe,
  357. struct ib_send_wr *wr, u8 *len16)
  358. {
  359. u32 plen;
  360. int size;
  361. int ret;
  362. if (wr->num_sge > T4_MAX_SEND_SGE)
  363. return -EINVAL;
  364. switch (wr->opcode) {
  365. case IB_WR_SEND:
  366. if (wr->send_flags & IB_SEND_SOLICITED)
  367. wqe->send.sendop_pkd = cpu_to_be32(
  368. V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE));
  369. else
  370. wqe->send.sendop_pkd = cpu_to_be32(
  371. V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND));
  372. wqe->send.stag_inv = 0;
  373. break;
  374. case IB_WR_SEND_WITH_INV:
  375. if (wr->send_flags & IB_SEND_SOLICITED)
  376. wqe->send.sendop_pkd = cpu_to_be32(
  377. V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_SE_INV));
  378. else
  379. wqe->send.sendop_pkd = cpu_to_be32(
  380. V_FW_RI_SEND_WR_SENDOP(FW_RI_SEND_WITH_INV));
  381. wqe->send.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
  382. break;
  383. default:
  384. return -EINVAL;
  385. }
  386. plen = 0;
  387. if (wr->num_sge) {
  388. if (wr->send_flags & IB_SEND_INLINE) {
  389. ret = build_immd(sq, wqe->send.u.immd_src, wr,
  390. T4_MAX_SEND_INLINE, &plen);
  391. if (ret)
  392. return ret;
  393. size = sizeof wqe->send + sizeof(struct fw_ri_immd) +
  394. plen;
  395. } else {
  396. ret = build_isgl((__be64 *)sq->queue,
  397. (__be64 *)&sq->queue[sq->size],
  398. wqe->send.u.isgl_src,
  399. wr->sg_list, wr->num_sge, &plen);
  400. if (ret)
  401. return ret;
  402. size = sizeof wqe->send + sizeof(struct fw_ri_isgl) +
  403. wr->num_sge * sizeof(struct fw_ri_sge);
  404. }
  405. } else {
  406. wqe->send.u.immd_src[0].op = FW_RI_DATA_IMMD;
  407. wqe->send.u.immd_src[0].r1 = 0;
  408. wqe->send.u.immd_src[0].r2 = 0;
  409. wqe->send.u.immd_src[0].immdlen = 0;
  410. size = sizeof wqe->send + sizeof(struct fw_ri_immd);
  411. plen = 0;
  412. }
  413. *len16 = DIV_ROUND_UP(size, 16);
  414. wqe->send.plen = cpu_to_be32(plen);
  415. return 0;
  416. }
  417. static int build_rdma_write(struct t4_sq *sq, union t4_wr *wqe,
  418. struct ib_send_wr *wr, u8 *len16)
  419. {
  420. u32 plen;
  421. int size;
  422. int ret;
  423. if (wr->num_sge > T4_MAX_SEND_SGE)
  424. return -EINVAL;
  425. wqe->write.r2 = 0;
  426. wqe->write.stag_sink = cpu_to_be32(wr->wr.rdma.rkey);
  427. wqe->write.to_sink = cpu_to_be64(wr->wr.rdma.remote_addr);
  428. if (wr->num_sge) {
  429. if (wr->send_flags & IB_SEND_INLINE) {
  430. ret = build_immd(sq, wqe->write.u.immd_src, wr,
  431. T4_MAX_WRITE_INLINE, &plen);
  432. if (ret)
  433. return ret;
  434. size = sizeof wqe->write + sizeof(struct fw_ri_immd) +
  435. plen;
  436. } else {
  437. ret = build_isgl((__be64 *)sq->queue,
  438. (__be64 *)&sq->queue[sq->size],
  439. wqe->write.u.isgl_src,
  440. wr->sg_list, wr->num_sge, &plen);
  441. if (ret)
  442. return ret;
  443. size = sizeof wqe->write + sizeof(struct fw_ri_isgl) +
  444. wr->num_sge * sizeof(struct fw_ri_sge);
  445. }
  446. } else {
  447. wqe->write.u.immd_src[0].op = FW_RI_DATA_IMMD;
  448. wqe->write.u.immd_src[0].r1 = 0;
  449. wqe->write.u.immd_src[0].r2 = 0;
  450. wqe->write.u.immd_src[0].immdlen = 0;
  451. size = sizeof wqe->write + sizeof(struct fw_ri_immd);
  452. plen = 0;
  453. }
  454. *len16 = DIV_ROUND_UP(size, 16);
  455. wqe->write.plen = cpu_to_be32(plen);
  456. return 0;
  457. }
  458. static int build_rdma_read(union t4_wr *wqe, struct ib_send_wr *wr, u8 *len16)
  459. {
  460. if (wr->num_sge > 1)
  461. return -EINVAL;
  462. if (wr->num_sge) {
  463. wqe->read.stag_src = cpu_to_be32(wr->wr.rdma.rkey);
  464. wqe->read.to_src_hi = cpu_to_be32((u32)(wr->wr.rdma.remote_addr
  465. >> 32));
  466. wqe->read.to_src_lo = cpu_to_be32((u32)wr->wr.rdma.remote_addr);
  467. wqe->read.stag_sink = cpu_to_be32(wr->sg_list[0].lkey);
  468. wqe->read.plen = cpu_to_be32(wr->sg_list[0].length);
  469. wqe->read.to_sink_hi = cpu_to_be32((u32)(wr->sg_list[0].addr
  470. >> 32));
  471. wqe->read.to_sink_lo = cpu_to_be32((u32)(wr->sg_list[0].addr));
  472. } else {
  473. wqe->read.stag_src = cpu_to_be32(2);
  474. wqe->read.to_src_hi = 0;
  475. wqe->read.to_src_lo = 0;
  476. wqe->read.stag_sink = cpu_to_be32(2);
  477. wqe->read.plen = 0;
  478. wqe->read.to_sink_hi = 0;
  479. wqe->read.to_sink_lo = 0;
  480. }
  481. wqe->read.r2 = 0;
  482. wqe->read.r5 = 0;
  483. *len16 = DIV_ROUND_UP(sizeof wqe->read, 16);
  484. return 0;
  485. }
  486. static int build_rdma_recv(struct c4iw_qp *qhp, union t4_recv_wr *wqe,
  487. struct ib_recv_wr *wr, u8 *len16)
  488. {
  489. int ret;
  490. ret = build_isgl((__be64 *)qhp->wq.rq.queue,
  491. (__be64 *)&qhp->wq.rq.queue[qhp->wq.rq.size],
  492. &wqe->recv.isgl, wr->sg_list, wr->num_sge, NULL);
  493. if (ret)
  494. return ret;
  495. *len16 = DIV_ROUND_UP(sizeof wqe->recv +
  496. wr->num_sge * sizeof(struct fw_ri_sge), 16);
  497. return 0;
  498. }
  499. static int build_fastreg(struct t4_sq *sq, union t4_wr *wqe,
  500. struct ib_send_wr *wr, u8 *len16, u8 t5dev)
  501. {
  502. struct fw_ri_immd *imdp;
  503. __be64 *p;
  504. int i;
  505. int pbllen = roundup(wr->wr.fast_reg.page_list_len * sizeof(u64), 32);
  506. int rem;
  507. if (wr->wr.fast_reg.page_list_len > T4_MAX_FR_DEPTH)
  508. return -EINVAL;
  509. wqe->fr.qpbinde_to_dcacpu = 0;
  510. wqe->fr.pgsz_shift = wr->wr.fast_reg.page_shift - 12;
  511. wqe->fr.addr_type = FW_RI_VA_BASED_TO;
  512. wqe->fr.mem_perms = c4iw_ib_to_tpt_access(wr->wr.fast_reg.access_flags);
  513. wqe->fr.len_hi = 0;
  514. wqe->fr.len_lo = cpu_to_be32(wr->wr.fast_reg.length);
  515. wqe->fr.stag = cpu_to_be32(wr->wr.fast_reg.rkey);
  516. wqe->fr.va_hi = cpu_to_be32(wr->wr.fast_reg.iova_start >> 32);
  517. wqe->fr.va_lo_fbo = cpu_to_be32(wr->wr.fast_reg.iova_start &
  518. 0xffffffff);
  519. if (t5dev && use_dsgl && (pbllen > max_fr_immd)) {
  520. struct c4iw_fr_page_list *c4pl =
  521. to_c4iw_fr_page_list(wr->wr.fast_reg.page_list);
  522. struct fw_ri_dsgl *sglp;
  523. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  524. wr->wr.fast_reg.page_list->page_list[i] = (__force u64)
  525. cpu_to_be64((u64)
  526. wr->wr.fast_reg.page_list->page_list[i]);
  527. }
  528. sglp = (struct fw_ri_dsgl *)(&wqe->fr + 1);
  529. sglp->op = FW_RI_DATA_DSGL;
  530. sglp->r1 = 0;
  531. sglp->nsge = cpu_to_be16(1);
  532. sglp->addr0 = cpu_to_be64(c4pl->dma_addr);
  533. sglp->len0 = cpu_to_be32(pbllen);
  534. *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*sglp), 16);
  535. } else {
  536. imdp = (struct fw_ri_immd *)(&wqe->fr + 1);
  537. imdp->op = FW_RI_DATA_IMMD;
  538. imdp->r1 = 0;
  539. imdp->r2 = 0;
  540. imdp->immdlen = cpu_to_be32(pbllen);
  541. p = (__be64 *)(imdp + 1);
  542. rem = pbllen;
  543. for (i = 0; i < wr->wr.fast_reg.page_list_len; i++) {
  544. *p = cpu_to_be64(
  545. (u64)wr->wr.fast_reg.page_list->page_list[i]);
  546. rem -= sizeof(*p);
  547. if (++p == (__be64 *)&sq->queue[sq->size])
  548. p = (__be64 *)sq->queue;
  549. }
  550. BUG_ON(rem < 0);
  551. while (rem) {
  552. *p = 0;
  553. rem -= sizeof(*p);
  554. if (++p == (__be64 *)&sq->queue[sq->size])
  555. p = (__be64 *)sq->queue;
  556. }
  557. *len16 = DIV_ROUND_UP(sizeof(wqe->fr) + sizeof(*imdp)
  558. + pbllen, 16);
  559. }
  560. return 0;
  561. }
  562. static int build_inv_stag(union t4_wr *wqe, struct ib_send_wr *wr,
  563. u8 *len16)
  564. {
  565. wqe->inv.stag_inv = cpu_to_be32(wr->ex.invalidate_rkey);
  566. wqe->inv.r2 = 0;
  567. *len16 = DIV_ROUND_UP(sizeof wqe->inv, 16);
  568. return 0;
  569. }
  570. void c4iw_qp_add_ref(struct ib_qp *qp)
  571. {
  572. PDBG("%s ib_qp %p\n", __func__, qp);
  573. atomic_inc(&(to_c4iw_qp(qp)->refcnt));
  574. }
  575. void c4iw_qp_rem_ref(struct ib_qp *qp)
  576. {
  577. PDBG("%s ib_qp %p\n", __func__, qp);
  578. if (atomic_dec_and_test(&(to_c4iw_qp(qp)->refcnt)))
  579. wake_up(&(to_c4iw_qp(qp)->wait));
  580. }
  581. int c4iw_post_send(struct ib_qp *ibqp, struct ib_send_wr *wr,
  582. struct ib_send_wr **bad_wr)
  583. {
  584. int err = 0;
  585. u8 len16 = 0;
  586. enum fw_wr_opcodes fw_opcode = 0;
  587. enum fw_ri_wr_flags fw_flags;
  588. struct c4iw_qp *qhp;
  589. union t4_wr *wqe;
  590. u32 num_wrs;
  591. struct t4_swsqe *swsqe;
  592. unsigned long flag;
  593. u16 idx = 0;
  594. qhp = to_c4iw_qp(ibqp);
  595. spin_lock_irqsave(&qhp->lock, flag);
  596. if (t4_wq_in_error(&qhp->wq)) {
  597. spin_unlock_irqrestore(&qhp->lock, flag);
  598. return -EINVAL;
  599. }
  600. num_wrs = t4_sq_avail(&qhp->wq);
  601. if (num_wrs == 0) {
  602. spin_unlock_irqrestore(&qhp->lock, flag);
  603. return -ENOMEM;
  604. }
  605. while (wr) {
  606. if (num_wrs == 0) {
  607. err = -ENOMEM;
  608. *bad_wr = wr;
  609. break;
  610. }
  611. wqe = (union t4_wr *)((u8 *)qhp->wq.sq.queue +
  612. qhp->wq.sq.wq_pidx * T4_EQ_ENTRY_SIZE);
  613. fw_flags = 0;
  614. if (wr->send_flags & IB_SEND_SOLICITED)
  615. fw_flags |= FW_RI_SOLICITED_EVENT_FLAG;
  616. if (wr->send_flags & IB_SEND_SIGNALED)
  617. fw_flags |= FW_RI_COMPLETION_FLAG;
  618. swsqe = &qhp->wq.sq.sw_sq[qhp->wq.sq.pidx];
  619. switch (wr->opcode) {
  620. case IB_WR_SEND_WITH_INV:
  621. case IB_WR_SEND:
  622. if (wr->send_flags & IB_SEND_FENCE)
  623. fw_flags |= FW_RI_READ_FENCE_FLAG;
  624. fw_opcode = FW_RI_SEND_WR;
  625. if (wr->opcode == IB_WR_SEND)
  626. swsqe->opcode = FW_RI_SEND;
  627. else
  628. swsqe->opcode = FW_RI_SEND_WITH_INV;
  629. err = build_rdma_send(&qhp->wq.sq, wqe, wr, &len16);
  630. break;
  631. case IB_WR_RDMA_WRITE:
  632. fw_opcode = FW_RI_RDMA_WRITE_WR;
  633. swsqe->opcode = FW_RI_RDMA_WRITE;
  634. err = build_rdma_write(&qhp->wq.sq, wqe, wr, &len16);
  635. break;
  636. case IB_WR_RDMA_READ:
  637. case IB_WR_RDMA_READ_WITH_INV:
  638. fw_opcode = FW_RI_RDMA_READ_WR;
  639. swsqe->opcode = FW_RI_READ_REQ;
  640. if (wr->opcode == IB_WR_RDMA_READ_WITH_INV)
  641. fw_flags = FW_RI_RDMA_READ_INVALIDATE;
  642. else
  643. fw_flags = 0;
  644. err = build_rdma_read(wqe, wr, &len16);
  645. if (err)
  646. break;
  647. swsqe->read_len = wr->sg_list[0].length;
  648. if (!qhp->wq.sq.oldest_read)
  649. qhp->wq.sq.oldest_read = swsqe;
  650. break;
  651. case IB_WR_FAST_REG_MR:
  652. fw_opcode = FW_RI_FR_NSMR_WR;
  653. swsqe->opcode = FW_RI_FAST_REGISTER;
  654. err = build_fastreg(&qhp->wq.sq, wqe, wr, &len16,
  655. is_t5(
  656. qhp->rhp->rdev.lldi.adapter_type) ?
  657. 1 : 0);
  658. break;
  659. case IB_WR_LOCAL_INV:
  660. if (wr->send_flags & IB_SEND_FENCE)
  661. fw_flags |= FW_RI_LOCAL_FENCE_FLAG;
  662. fw_opcode = FW_RI_INV_LSTAG_WR;
  663. swsqe->opcode = FW_RI_LOCAL_INV;
  664. err = build_inv_stag(wqe, wr, &len16);
  665. break;
  666. default:
  667. PDBG("%s post of type=%d TBD!\n", __func__,
  668. wr->opcode);
  669. err = -EINVAL;
  670. }
  671. if (err) {
  672. *bad_wr = wr;
  673. break;
  674. }
  675. swsqe->idx = qhp->wq.sq.pidx;
  676. swsqe->complete = 0;
  677. swsqe->signaled = (wr->send_flags & IB_SEND_SIGNALED);
  678. swsqe->wr_id = wr->wr_id;
  679. init_wr_hdr(wqe, qhp->wq.sq.pidx, fw_opcode, fw_flags, len16);
  680. PDBG("%s cookie 0x%llx pidx 0x%x opcode 0x%x read_len %u\n",
  681. __func__, (unsigned long long)wr->wr_id, qhp->wq.sq.pidx,
  682. swsqe->opcode, swsqe->read_len);
  683. wr = wr->next;
  684. num_wrs--;
  685. t4_sq_produce(&qhp->wq, len16);
  686. idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
  687. }
  688. if (t4_wq_db_enabled(&qhp->wq))
  689. t4_ring_sq_db(&qhp->wq, idx);
  690. spin_unlock_irqrestore(&qhp->lock, flag);
  691. return err;
  692. }
  693. int c4iw_post_receive(struct ib_qp *ibqp, struct ib_recv_wr *wr,
  694. struct ib_recv_wr **bad_wr)
  695. {
  696. int err = 0;
  697. struct c4iw_qp *qhp;
  698. union t4_recv_wr *wqe;
  699. u32 num_wrs;
  700. u8 len16 = 0;
  701. unsigned long flag;
  702. u16 idx = 0;
  703. qhp = to_c4iw_qp(ibqp);
  704. spin_lock_irqsave(&qhp->lock, flag);
  705. if (t4_wq_in_error(&qhp->wq)) {
  706. spin_unlock_irqrestore(&qhp->lock, flag);
  707. return -EINVAL;
  708. }
  709. num_wrs = t4_rq_avail(&qhp->wq);
  710. if (num_wrs == 0) {
  711. spin_unlock_irqrestore(&qhp->lock, flag);
  712. return -ENOMEM;
  713. }
  714. while (wr) {
  715. if (wr->num_sge > T4_MAX_RECV_SGE) {
  716. err = -EINVAL;
  717. *bad_wr = wr;
  718. break;
  719. }
  720. wqe = (union t4_recv_wr *)((u8 *)qhp->wq.rq.queue +
  721. qhp->wq.rq.wq_pidx *
  722. T4_EQ_ENTRY_SIZE);
  723. if (num_wrs)
  724. err = build_rdma_recv(qhp, wqe, wr, &len16);
  725. else
  726. err = -ENOMEM;
  727. if (err) {
  728. *bad_wr = wr;
  729. break;
  730. }
  731. qhp->wq.rq.sw_rq[qhp->wq.rq.pidx].wr_id = wr->wr_id;
  732. wqe->recv.opcode = FW_RI_RECV_WR;
  733. wqe->recv.r1 = 0;
  734. wqe->recv.wrid = qhp->wq.rq.pidx;
  735. wqe->recv.r2[0] = 0;
  736. wqe->recv.r2[1] = 0;
  737. wqe->recv.r2[2] = 0;
  738. wqe->recv.len16 = len16;
  739. PDBG("%s cookie 0x%llx pidx %u\n", __func__,
  740. (unsigned long long) wr->wr_id, qhp->wq.rq.pidx);
  741. t4_rq_produce(&qhp->wq, len16);
  742. idx += DIV_ROUND_UP(len16*16, T4_EQ_ENTRY_SIZE);
  743. wr = wr->next;
  744. num_wrs--;
  745. }
  746. if (t4_wq_db_enabled(&qhp->wq))
  747. t4_ring_rq_db(&qhp->wq, idx);
  748. spin_unlock_irqrestore(&qhp->lock, flag);
  749. return err;
  750. }
  751. int c4iw_bind_mw(struct ib_qp *qp, struct ib_mw *mw, struct ib_mw_bind *mw_bind)
  752. {
  753. return -ENOSYS;
  754. }
  755. static inline void build_term_codes(struct t4_cqe *err_cqe, u8 *layer_type,
  756. u8 *ecode)
  757. {
  758. int status;
  759. int tagged;
  760. int opcode;
  761. int rqtype;
  762. int send_inv;
  763. if (!err_cqe) {
  764. *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
  765. *ecode = 0;
  766. return;
  767. }
  768. status = CQE_STATUS(err_cqe);
  769. opcode = CQE_OPCODE(err_cqe);
  770. rqtype = RQ_TYPE(err_cqe);
  771. send_inv = (opcode == FW_RI_SEND_WITH_INV) ||
  772. (opcode == FW_RI_SEND_WITH_SE_INV);
  773. tagged = (opcode == FW_RI_RDMA_WRITE) ||
  774. (rqtype && (opcode == FW_RI_READ_RESP));
  775. switch (status) {
  776. case T4_ERR_STAG:
  777. if (send_inv) {
  778. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
  779. *ecode = RDMAP_CANT_INV_STAG;
  780. } else {
  781. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  782. *ecode = RDMAP_INV_STAG;
  783. }
  784. break;
  785. case T4_ERR_PDID:
  786. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  787. if ((opcode == FW_RI_SEND_WITH_INV) ||
  788. (opcode == FW_RI_SEND_WITH_SE_INV))
  789. *ecode = RDMAP_CANT_INV_STAG;
  790. else
  791. *ecode = RDMAP_STAG_NOT_ASSOC;
  792. break;
  793. case T4_ERR_QPID:
  794. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  795. *ecode = RDMAP_STAG_NOT_ASSOC;
  796. break;
  797. case T4_ERR_ACCESS:
  798. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  799. *ecode = RDMAP_ACC_VIOL;
  800. break;
  801. case T4_ERR_WRAP:
  802. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  803. *ecode = RDMAP_TO_WRAP;
  804. break;
  805. case T4_ERR_BOUND:
  806. if (tagged) {
  807. *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
  808. *ecode = DDPT_BASE_BOUNDS;
  809. } else {
  810. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_PROT;
  811. *ecode = RDMAP_BASE_BOUNDS;
  812. }
  813. break;
  814. case T4_ERR_INVALIDATE_SHARED_MR:
  815. case T4_ERR_INVALIDATE_MR_WITH_MW_BOUND:
  816. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
  817. *ecode = RDMAP_CANT_INV_STAG;
  818. break;
  819. case T4_ERR_ECC:
  820. case T4_ERR_ECC_PSTAG:
  821. case T4_ERR_INTERNAL_ERR:
  822. *layer_type = LAYER_RDMAP|RDMAP_LOCAL_CATA;
  823. *ecode = 0;
  824. break;
  825. case T4_ERR_OUT_OF_RQE:
  826. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  827. *ecode = DDPU_INV_MSN_NOBUF;
  828. break;
  829. case T4_ERR_PBL_ADDR_BOUND:
  830. *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
  831. *ecode = DDPT_BASE_BOUNDS;
  832. break;
  833. case T4_ERR_CRC:
  834. *layer_type = LAYER_MPA|DDP_LLP;
  835. *ecode = MPA_CRC_ERR;
  836. break;
  837. case T4_ERR_MARKER:
  838. *layer_type = LAYER_MPA|DDP_LLP;
  839. *ecode = MPA_MARKER_ERR;
  840. break;
  841. case T4_ERR_PDU_LEN_ERR:
  842. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  843. *ecode = DDPU_MSG_TOOBIG;
  844. break;
  845. case T4_ERR_DDP_VERSION:
  846. if (tagged) {
  847. *layer_type = LAYER_DDP|DDP_TAGGED_ERR;
  848. *ecode = DDPT_INV_VERS;
  849. } else {
  850. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  851. *ecode = DDPU_INV_VERS;
  852. }
  853. break;
  854. case T4_ERR_RDMA_VERSION:
  855. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
  856. *ecode = RDMAP_INV_VERS;
  857. break;
  858. case T4_ERR_OPCODE:
  859. *layer_type = LAYER_RDMAP|RDMAP_REMOTE_OP;
  860. *ecode = RDMAP_INV_OPCODE;
  861. break;
  862. case T4_ERR_DDP_QUEUE_NUM:
  863. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  864. *ecode = DDPU_INV_QN;
  865. break;
  866. case T4_ERR_MSN:
  867. case T4_ERR_MSN_GAP:
  868. case T4_ERR_MSN_RANGE:
  869. case T4_ERR_IRD_OVERFLOW:
  870. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  871. *ecode = DDPU_INV_MSN_RANGE;
  872. break;
  873. case T4_ERR_TBIT:
  874. *layer_type = LAYER_DDP|DDP_LOCAL_CATA;
  875. *ecode = 0;
  876. break;
  877. case T4_ERR_MO:
  878. *layer_type = LAYER_DDP|DDP_UNTAGGED_ERR;
  879. *ecode = DDPU_INV_MO;
  880. break;
  881. default:
  882. *layer_type = LAYER_RDMAP|DDP_LOCAL_CATA;
  883. *ecode = 0;
  884. break;
  885. }
  886. }
  887. static void post_terminate(struct c4iw_qp *qhp, struct t4_cqe *err_cqe,
  888. gfp_t gfp)
  889. {
  890. struct fw_ri_wr *wqe;
  891. struct sk_buff *skb;
  892. struct terminate_message *term;
  893. PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
  894. qhp->ep->hwtid);
  895. skb = alloc_skb(sizeof *wqe, gfp);
  896. if (!skb)
  897. return;
  898. set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
  899. wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
  900. memset(wqe, 0, sizeof *wqe);
  901. wqe->op_compl = cpu_to_be32(FW_WR_OP(FW_RI_INIT_WR));
  902. wqe->flowid_len16 = cpu_to_be32(
  903. FW_WR_FLOWID(qhp->ep->hwtid) |
  904. FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
  905. wqe->u.terminate.type = FW_RI_TYPE_TERMINATE;
  906. wqe->u.terminate.immdlen = cpu_to_be32(sizeof *term);
  907. term = (struct terminate_message *)wqe->u.terminate.termmsg;
  908. if (qhp->attr.layer_etype == (LAYER_MPA|DDP_LLP)) {
  909. term->layer_etype = qhp->attr.layer_etype;
  910. term->ecode = qhp->attr.ecode;
  911. } else
  912. build_term_codes(err_cqe, &term->layer_etype, &term->ecode);
  913. c4iw_ofld_send(&qhp->rhp->rdev, skb);
  914. }
  915. /*
  916. * Assumes qhp lock is held.
  917. */
  918. static void __flush_qp(struct c4iw_qp *qhp, struct c4iw_cq *rchp,
  919. struct c4iw_cq *schp)
  920. {
  921. int count;
  922. int flushed;
  923. unsigned long flag;
  924. PDBG("%s qhp %p rchp %p schp %p\n", __func__, qhp, rchp, schp);
  925. /* locking hierarchy: cq lock first, then qp lock. */
  926. spin_lock_irqsave(&rchp->lock, flag);
  927. spin_lock(&qhp->lock);
  928. c4iw_flush_hw_cq(&rchp->cq);
  929. c4iw_count_rcqes(&rchp->cq, &qhp->wq, &count);
  930. flushed = c4iw_flush_rq(&qhp->wq, &rchp->cq, count);
  931. spin_unlock(&qhp->lock);
  932. spin_unlock_irqrestore(&rchp->lock, flag);
  933. if (flushed) {
  934. spin_lock_irqsave(&rchp->comp_handler_lock, flag);
  935. (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
  936. spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
  937. }
  938. /* locking hierarchy: cq lock first, then qp lock. */
  939. spin_lock_irqsave(&schp->lock, flag);
  940. spin_lock(&qhp->lock);
  941. c4iw_flush_hw_cq(&schp->cq);
  942. c4iw_count_scqes(&schp->cq, &qhp->wq, &count);
  943. flushed = c4iw_flush_sq(&qhp->wq, &schp->cq, count);
  944. spin_unlock(&qhp->lock);
  945. spin_unlock_irqrestore(&schp->lock, flag);
  946. if (flushed) {
  947. spin_lock_irqsave(&schp->comp_handler_lock, flag);
  948. (*schp->ibcq.comp_handler)(&schp->ibcq, schp->ibcq.cq_context);
  949. spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
  950. }
  951. }
  952. static void flush_qp(struct c4iw_qp *qhp)
  953. {
  954. struct c4iw_cq *rchp, *schp;
  955. unsigned long flag;
  956. rchp = get_chp(qhp->rhp, qhp->attr.rcq);
  957. schp = get_chp(qhp->rhp, qhp->attr.scq);
  958. if (qhp->ibqp.uobject) {
  959. t4_set_wq_in_error(&qhp->wq);
  960. t4_set_cq_in_error(&rchp->cq);
  961. spin_lock_irqsave(&rchp->comp_handler_lock, flag);
  962. (*rchp->ibcq.comp_handler)(&rchp->ibcq, rchp->ibcq.cq_context);
  963. spin_unlock_irqrestore(&rchp->comp_handler_lock, flag);
  964. if (schp != rchp) {
  965. t4_set_cq_in_error(&schp->cq);
  966. spin_lock_irqsave(&schp->comp_handler_lock, flag);
  967. (*schp->ibcq.comp_handler)(&schp->ibcq,
  968. schp->ibcq.cq_context);
  969. spin_unlock_irqrestore(&schp->comp_handler_lock, flag);
  970. }
  971. return;
  972. }
  973. __flush_qp(qhp, rchp, schp);
  974. }
  975. static int rdma_fini(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
  976. struct c4iw_ep *ep)
  977. {
  978. struct fw_ri_wr *wqe;
  979. int ret;
  980. struct sk_buff *skb;
  981. PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
  982. ep->hwtid);
  983. skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
  984. if (!skb)
  985. return -ENOMEM;
  986. set_wr_txq(skb, CPL_PRIORITY_DATA, ep->txq_idx);
  987. wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
  988. memset(wqe, 0, sizeof *wqe);
  989. wqe->op_compl = cpu_to_be32(
  990. FW_WR_OP(FW_RI_INIT_WR) |
  991. FW_WR_COMPL(1));
  992. wqe->flowid_len16 = cpu_to_be32(
  993. FW_WR_FLOWID(ep->hwtid) |
  994. FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
  995. wqe->cookie = (unsigned long) &ep->com.wr_wait;
  996. wqe->u.fini.type = FW_RI_TYPE_FINI;
  997. ret = c4iw_ofld_send(&rhp->rdev, skb);
  998. if (ret)
  999. goto out;
  1000. ret = c4iw_wait_for_reply(&rhp->rdev, &ep->com.wr_wait, qhp->ep->hwtid,
  1001. qhp->wq.sq.qid, __func__);
  1002. out:
  1003. PDBG("%s ret %d\n", __func__, ret);
  1004. return ret;
  1005. }
  1006. static void build_rtr_msg(u8 p2p_type, struct fw_ri_init *init)
  1007. {
  1008. PDBG("%s p2p_type = %d\n", __func__, p2p_type);
  1009. memset(&init->u, 0, sizeof init->u);
  1010. switch (p2p_type) {
  1011. case FW_RI_INIT_P2PTYPE_RDMA_WRITE:
  1012. init->u.write.opcode = FW_RI_RDMA_WRITE_WR;
  1013. init->u.write.stag_sink = cpu_to_be32(1);
  1014. init->u.write.to_sink = cpu_to_be64(1);
  1015. init->u.write.u.immd_src[0].op = FW_RI_DATA_IMMD;
  1016. init->u.write.len16 = DIV_ROUND_UP(sizeof init->u.write +
  1017. sizeof(struct fw_ri_immd),
  1018. 16);
  1019. break;
  1020. case FW_RI_INIT_P2PTYPE_READ_REQ:
  1021. init->u.write.opcode = FW_RI_RDMA_READ_WR;
  1022. init->u.read.stag_src = cpu_to_be32(1);
  1023. init->u.read.to_src_lo = cpu_to_be32(1);
  1024. init->u.read.stag_sink = cpu_to_be32(1);
  1025. init->u.read.to_sink_lo = cpu_to_be32(1);
  1026. init->u.read.len16 = DIV_ROUND_UP(sizeof init->u.read, 16);
  1027. break;
  1028. }
  1029. }
  1030. static int rdma_init(struct c4iw_dev *rhp, struct c4iw_qp *qhp)
  1031. {
  1032. struct fw_ri_wr *wqe;
  1033. int ret;
  1034. struct sk_buff *skb;
  1035. PDBG("%s qhp %p qid 0x%x tid %u\n", __func__, qhp, qhp->wq.sq.qid,
  1036. qhp->ep->hwtid);
  1037. skb = alloc_skb(sizeof *wqe, GFP_KERNEL);
  1038. if (!skb)
  1039. return -ENOMEM;
  1040. set_wr_txq(skb, CPL_PRIORITY_DATA, qhp->ep->txq_idx);
  1041. wqe = (struct fw_ri_wr *)__skb_put(skb, sizeof(*wqe));
  1042. memset(wqe, 0, sizeof *wqe);
  1043. wqe->op_compl = cpu_to_be32(
  1044. FW_WR_OP(FW_RI_INIT_WR) |
  1045. FW_WR_COMPL(1));
  1046. wqe->flowid_len16 = cpu_to_be32(
  1047. FW_WR_FLOWID(qhp->ep->hwtid) |
  1048. FW_WR_LEN16(DIV_ROUND_UP(sizeof *wqe, 16)));
  1049. wqe->cookie = (unsigned long) &qhp->ep->com.wr_wait;
  1050. wqe->u.init.type = FW_RI_TYPE_INIT;
  1051. wqe->u.init.mpareqbit_p2ptype =
  1052. V_FW_RI_WR_MPAREQBIT(qhp->attr.mpa_attr.initiator) |
  1053. V_FW_RI_WR_P2PTYPE(qhp->attr.mpa_attr.p2p_type);
  1054. wqe->u.init.mpa_attrs = FW_RI_MPA_IETF_ENABLE;
  1055. if (qhp->attr.mpa_attr.recv_marker_enabled)
  1056. wqe->u.init.mpa_attrs |= FW_RI_MPA_RX_MARKER_ENABLE;
  1057. if (qhp->attr.mpa_attr.xmit_marker_enabled)
  1058. wqe->u.init.mpa_attrs |= FW_RI_MPA_TX_MARKER_ENABLE;
  1059. if (qhp->attr.mpa_attr.crc_enabled)
  1060. wqe->u.init.mpa_attrs |= FW_RI_MPA_CRC_ENABLE;
  1061. wqe->u.init.qp_caps = FW_RI_QP_RDMA_READ_ENABLE |
  1062. FW_RI_QP_RDMA_WRITE_ENABLE |
  1063. FW_RI_QP_BIND_ENABLE;
  1064. if (!qhp->ibqp.uobject)
  1065. wqe->u.init.qp_caps |= FW_RI_QP_FAST_REGISTER_ENABLE |
  1066. FW_RI_QP_STAG0_ENABLE;
  1067. wqe->u.init.nrqe = cpu_to_be16(t4_rqes_posted(&qhp->wq));
  1068. wqe->u.init.pdid = cpu_to_be32(qhp->attr.pd);
  1069. wqe->u.init.qpid = cpu_to_be32(qhp->wq.sq.qid);
  1070. wqe->u.init.sq_eqid = cpu_to_be32(qhp->wq.sq.qid);
  1071. wqe->u.init.rq_eqid = cpu_to_be32(qhp->wq.rq.qid);
  1072. wqe->u.init.scqid = cpu_to_be32(qhp->attr.scq);
  1073. wqe->u.init.rcqid = cpu_to_be32(qhp->attr.rcq);
  1074. wqe->u.init.ord_max = cpu_to_be32(qhp->attr.max_ord);
  1075. wqe->u.init.ird_max = cpu_to_be32(qhp->attr.max_ird);
  1076. wqe->u.init.iss = cpu_to_be32(qhp->ep->snd_seq);
  1077. wqe->u.init.irs = cpu_to_be32(qhp->ep->rcv_seq);
  1078. wqe->u.init.hwrqsize = cpu_to_be32(qhp->wq.rq.rqt_size);
  1079. wqe->u.init.hwrqaddr = cpu_to_be32(qhp->wq.rq.rqt_hwaddr -
  1080. rhp->rdev.lldi.vr->rq.start);
  1081. if (qhp->attr.mpa_attr.initiator)
  1082. build_rtr_msg(qhp->attr.mpa_attr.p2p_type, &wqe->u.init);
  1083. ret = c4iw_ofld_send(&rhp->rdev, skb);
  1084. if (ret)
  1085. goto out;
  1086. ret = c4iw_wait_for_reply(&rhp->rdev, &qhp->ep->com.wr_wait,
  1087. qhp->ep->hwtid, qhp->wq.sq.qid, __func__);
  1088. out:
  1089. PDBG("%s ret %d\n", __func__, ret);
  1090. return ret;
  1091. }
  1092. /*
  1093. * Called by the library when the qp has user dbs disabled due to
  1094. * a DB_FULL condition. This function will single-thread all user
  1095. * DB rings to avoid overflowing the hw db-fifo.
  1096. */
  1097. static int ring_kernel_db(struct c4iw_qp *qhp, u32 qid, u16 inc)
  1098. {
  1099. int delay = db_delay_usecs;
  1100. mutex_lock(&qhp->rhp->db_mutex);
  1101. do {
  1102. /*
  1103. * The interrupt threshold is dbfifo_int_thresh << 6. So
  1104. * make sure we don't cross that and generate an interrupt.
  1105. */
  1106. if (cxgb4_dbfifo_count(qhp->rhp->rdev.lldi.ports[0], 1) <
  1107. (qhp->rhp->rdev.lldi.dbfifo_int_thresh << 5)) {
  1108. writel(QID(qid) | PIDX(inc), qhp->wq.db);
  1109. break;
  1110. }
  1111. set_current_state(TASK_UNINTERRUPTIBLE);
  1112. schedule_timeout(usecs_to_jiffies(delay));
  1113. delay = min(delay << 1, 2000);
  1114. } while (1);
  1115. mutex_unlock(&qhp->rhp->db_mutex);
  1116. return 0;
  1117. }
  1118. int c4iw_modify_qp(struct c4iw_dev *rhp, struct c4iw_qp *qhp,
  1119. enum c4iw_qp_attr_mask mask,
  1120. struct c4iw_qp_attributes *attrs,
  1121. int internal)
  1122. {
  1123. int ret = 0;
  1124. struct c4iw_qp_attributes newattr = qhp->attr;
  1125. int disconnect = 0;
  1126. int terminate = 0;
  1127. int abort = 0;
  1128. int free = 0;
  1129. struct c4iw_ep *ep = NULL;
  1130. PDBG("%s qhp %p sqid 0x%x rqid 0x%x ep %p state %d -> %d\n", __func__,
  1131. qhp, qhp->wq.sq.qid, qhp->wq.rq.qid, qhp->ep, qhp->attr.state,
  1132. (mask & C4IW_QP_ATTR_NEXT_STATE) ? attrs->next_state : -1);
  1133. mutex_lock(&qhp->mutex);
  1134. /* Process attr changes if in IDLE */
  1135. if (mask & C4IW_QP_ATTR_VALID_MODIFY) {
  1136. if (qhp->attr.state != C4IW_QP_STATE_IDLE) {
  1137. ret = -EIO;
  1138. goto out;
  1139. }
  1140. if (mask & C4IW_QP_ATTR_ENABLE_RDMA_READ)
  1141. newattr.enable_rdma_read = attrs->enable_rdma_read;
  1142. if (mask & C4IW_QP_ATTR_ENABLE_RDMA_WRITE)
  1143. newattr.enable_rdma_write = attrs->enable_rdma_write;
  1144. if (mask & C4IW_QP_ATTR_ENABLE_RDMA_BIND)
  1145. newattr.enable_bind = attrs->enable_bind;
  1146. if (mask & C4IW_QP_ATTR_MAX_ORD) {
  1147. if (attrs->max_ord > c4iw_max_read_depth) {
  1148. ret = -EINVAL;
  1149. goto out;
  1150. }
  1151. newattr.max_ord = attrs->max_ord;
  1152. }
  1153. if (mask & C4IW_QP_ATTR_MAX_IRD) {
  1154. if (attrs->max_ird > c4iw_max_read_depth) {
  1155. ret = -EINVAL;
  1156. goto out;
  1157. }
  1158. newattr.max_ird = attrs->max_ird;
  1159. }
  1160. qhp->attr = newattr;
  1161. }
  1162. if (mask & C4IW_QP_ATTR_SQ_DB) {
  1163. ret = ring_kernel_db(qhp, qhp->wq.sq.qid, attrs->sq_db_inc);
  1164. goto out;
  1165. }
  1166. if (mask & C4IW_QP_ATTR_RQ_DB) {
  1167. ret = ring_kernel_db(qhp, qhp->wq.rq.qid, attrs->rq_db_inc);
  1168. goto out;
  1169. }
  1170. if (!(mask & C4IW_QP_ATTR_NEXT_STATE))
  1171. goto out;
  1172. if (qhp->attr.state == attrs->next_state)
  1173. goto out;
  1174. switch (qhp->attr.state) {
  1175. case C4IW_QP_STATE_IDLE:
  1176. switch (attrs->next_state) {
  1177. case C4IW_QP_STATE_RTS:
  1178. if (!(mask & C4IW_QP_ATTR_LLP_STREAM_HANDLE)) {
  1179. ret = -EINVAL;
  1180. goto out;
  1181. }
  1182. if (!(mask & C4IW_QP_ATTR_MPA_ATTR)) {
  1183. ret = -EINVAL;
  1184. goto out;
  1185. }
  1186. qhp->attr.mpa_attr = attrs->mpa_attr;
  1187. qhp->attr.llp_stream_handle = attrs->llp_stream_handle;
  1188. qhp->ep = qhp->attr.llp_stream_handle;
  1189. set_state(qhp, C4IW_QP_STATE_RTS);
  1190. /*
  1191. * Ref the endpoint here and deref when we
  1192. * disassociate the endpoint from the QP. This
  1193. * happens in CLOSING->IDLE transition or *->ERROR
  1194. * transition.
  1195. */
  1196. c4iw_get_ep(&qhp->ep->com);
  1197. ret = rdma_init(rhp, qhp);
  1198. if (ret)
  1199. goto err;
  1200. break;
  1201. case C4IW_QP_STATE_ERROR:
  1202. set_state(qhp, C4IW_QP_STATE_ERROR);
  1203. flush_qp(qhp);
  1204. break;
  1205. default:
  1206. ret = -EINVAL;
  1207. goto out;
  1208. }
  1209. break;
  1210. case C4IW_QP_STATE_RTS:
  1211. switch (attrs->next_state) {
  1212. case C4IW_QP_STATE_CLOSING:
  1213. BUG_ON(atomic_read(&qhp->ep->com.kref.refcount) < 2);
  1214. set_state(qhp, C4IW_QP_STATE_CLOSING);
  1215. ep = qhp->ep;
  1216. if (!internal) {
  1217. abort = 0;
  1218. disconnect = 1;
  1219. c4iw_get_ep(&qhp->ep->com);
  1220. }
  1221. if (qhp->ibqp.uobject)
  1222. t4_set_wq_in_error(&qhp->wq);
  1223. ret = rdma_fini(rhp, qhp, ep);
  1224. if (ret)
  1225. goto err;
  1226. break;
  1227. case C4IW_QP_STATE_TERMINATE:
  1228. set_state(qhp, C4IW_QP_STATE_TERMINATE);
  1229. qhp->attr.layer_etype = attrs->layer_etype;
  1230. qhp->attr.ecode = attrs->ecode;
  1231. if (qhp->ibqp.uobject)
  1232. t4_set_wq_in_error(&qhp->wq);
  1233. ep = qhp->ep;
  1234. if (!internal)
  1235. terminate = 1;
  1236. disconnect = 1;
  1237. c4iw_get_ep(&qhp->ep->com);
  1238. break;
  1239. case C4IW_QP_STATE_ERROR:
  1240. set_state(qhp, C4IW_QP_STATE_ERROR);
  1241. if (qhp->ibqp.uobject)
  1242. t4_set_wq_in_error(&qhp->wq);
  1243. if (!internal) {
  1244. abort = 1;
  1245. disconnect = 1;
  1246. ep = qhp->ep;
  1247. c4iw_get_ep(&qhp->ep->com);
  1248. }
  1249. goto err;
  1250. break;
  1251. default:
  1252. ret = -EINVAL;
  1253. goto out;
  1254. }
  1255. break;
  1256. case C4IW_QP_STATE_CLOSING:
  1257. if (!internal) {
  1258. ret = -EINVAL;
  1259. goto out;
  1260. }
  1261. switch (attrs->next_state) {
  1262. case C4IW_QP_STATE_IDLE:
  1263. flush_qp(qhp);
  1264. set_state(qhp, C4IW_QP_STATE_IDLE);
  1265. qhp->attr.llp_stream_handle = NULL;
  1266. c4iw_put_ep(&qhp->ep->com);
  1267. qhp->ep = NULL;
  1268. wake_up(&qhp->wait);
  1269. break;
  1270. case C4IW_QP_STATE_ERROR:
  1271. goto err;
  1272. default:
  1273. ret = -EINVAL;
  1274. goto err;
  1275. }
  1276. break;
  1277. case C4IW_QP_STATE_ERROR:
  1278. if (attrs->next_state != C4IW_QP_STATE_IDLE) {
  1279. ret = -EINVAL;
  1280. goto out;
  1281. }
  1282. if (!t4_sq_empty(&qhp->wq) || !t4_rq_empty(&qhp->wq)) {
  1283. ret = -EINVAL;
  1284. goto out;
  1285. }
  1286. set_state(qhp, C4IW_QP_STATE_IDLE);
  1287. break;
  1288. case C4IW_QP_STATE_TERMINATE:
  1289. if (!internal) {
  1290. ret = -EINVAL;
  1291. goto out;
  1292. }
  1293. goto err;
  1294. break;
  1295. default:
  1296. printk(KERN_ERR "%s in a bad state %d\n",
  1297. __func__, qhp->attr.state);
  1298. ret = -EINVAL;
  1299. goto err;
  1300. break;
  1301. }
  1302. goto out;
  1303. err:
  1304. PDBG("%s disassociating ep %p qpid 0x%x\n", __func__, qhp->ep,
  1305. qhp->wq.sq.qid);
  1306. /* disassociate the LLP connection */
  1307. qhp->attr.llp_stream_handle = NULL;
  1308. if (!ep)
  1309. ep = qhp->ep;
  1310. qhp->ep = NULL;
  1311. set_state(qhp, C4IW_QP_STATE_ERROR);
  1312. free = 1;
  1313. abort = 1;
  1314. wake_up(&qhp->wait);
  1315. BUG_ON(!ep);
  1316. flush_qp(qhp);
  1317. out:
  1318. mutex_unlock(&qhp->mutex);
  1319. if (terminate)
  1320. post_terminate(qhp, NULL, internal ? GFP_ATOMIC : GFP_KERNEL);
  1321. /*
  1322. * If disconnect is 1, then we need to initiate a disconnect
  1323. * on the EP. This can be a normal close (RTS->CLOSING) or
  1324. * an abnormal close (RTS/CLOSING->ERROR).
  1325. */
  1326. if (disconnect) {
  1327. c4iw_ep_disconnect(ep, abort, internal ? GFP_ATOMIC :
  1328. GFP_KERNEL);
  1329. c4iw_put_ep(&ep->com);
  1330. }
  1331. /*
  1332. * If free is 1, then we've disassociated the EP from the QP
  1333. * and we need to dereference the EP.
  1334. */
  1335. if (free)
  1336. c4iw_put_ep(&ep->com);
  1337. PDBG("%s exit state %d\n", __func__, qhp->attr.state);
  1338. return ret;
  1339. }
  1340. static int enable_qp_db(int id, void *p, void *data)
  1341. {
  1342. struct c4iw_qp *qp = p;
  1343. t4_enable_wq_db(&qp->wq);
  1344. return 0;
  1345. }
  1346. int c4iw_destroy_qp(struct ib_qp *ib_qp)
  1347. {
  1348. struct c4iw_dev *rhp;
  1349. struct c4iw_qp *qhp;
  1350. struct c4iw_qp_attributes attrs;
  1351. struct c4iw_ucontext *ucontext;
  1352. qhp = to_c4iw_qp(ib_qp);
  1353. rhp = qhp->rhp;
  1354. attrs.next_state = C4IW_QP_STATE_ERROR;
  1355. if (qhp->attr.state == C4IW_QP_STATE_TERMINATE)
  1356. c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 1);
  1357. else
  1358. c4iw_modify_qp(rhp, qhp, C4IW_QP_ATTR_NEXT_STATE, &attrs, 0);
  1359. wait_event(qhp->wait, !qhp->ep);
  1360. spin_lock_irq(&rhp->lock);
  1361. remove_handle_nolock(rhp, &rhp->qpidr, qhp->wq.sq.qid);
  1362. rhp->qpcnt--;
  1363. BUG_ON(rhp->qpcnt < 0);
  1364. if (rhp->qpcnt <= db_fc_threshold && rhp->db_state == FLOW_CONTROL) {
  1365. rhp->rdev.stats.db_state_transitions++;
  1366. rhp->db_state = NORMAL;
  1367. idr_for_each(&rhp->qpidr, enable_qp_db, NULL);
  1368. }
  1369. if (db_coalescing_threshold >= 0)
  1370. if (rhp->qpcnt <= db_coalescing_threshold)
  1371. cxgb4_enable_db_coalescing(rhp->rdev.lldi.ports[0]);
  1372. spin_unlock_irq(&rhp->lock);
  1373. atomic_dec(&qhp->refcnt);
  1374. wait_event(qhp->wait, !atomic_read(&qhp->refcnt));
  1375. ucontext = ib_qp->uobject ?
  1376. to_c4iw_ucontext(ib_qp->uobject->context) : NULL;
  1377. destroy_qp(&rhp->rdev, &qhp->wq,
  1378. ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
  1379. PDBG("%s ib_qp %p qpid 0x%0x\n", __func__, ib_qp, qhp->wq.sq.qid);
  1380. kfree(qhp);
  1381. return 0;
  1382. }
  1383. static int disable_qp_db(int id, void *p, void *data)
  1384. {
  1385. struct c4iw_qp *qp = p;
  1386. t4_disable_wq_db(&qp->wq);
  1387. return 0;
  1388. }
  1389. struct ib_qp *c4iw_create_qp(struct ib_pd *pd, struct ib_qp_init_attr *attrs,
  1390. struct ib_udata *udata)
  1391. {
  1392. struct c4iw_dev *rhp;
  1393. struct c4iw_qp *qhp;
  1394. struct c4iw_pd *php;
  1395. struct c4iw_cq *schp;
  1396. struct c4iw_cq *rchp;
  1397. struct c4iw_create_qp_resp uresp;
  1398. int sqsize, rqsize;
  1399. struct c4iw_ucontext *ucontext;
  1400. int ret;
  1401. struct c4iw_mm_entry *mm1, *mm2, *mm3, *mm4, *mm5 = NULL;
  1402. PDBG("%s ib_pd %p\n", __func__, pd);
  1403. if (attrs->qp_type != IB_QPT_RC)
  1404. return ERR_PTR(-EINVAL);
  1405. php = to_c4iw_pd(pd);
  1406. rhp = php->rhp;
  1407. schp = get_chp(rhp, ((struct c4iw_cq *)attrs->send_cq)->cq.cqid);
  1408. rchp = get_chp(rhp, ((struct c4iw_cq *)attrs->recv_cq)->cq.cqid);
  1409. if (!schp || !rchp)
  1410. return ERR_PTR(-EINVAL);
  1411. if (attrs->cap.max_inline_data > T4_MAX_SEND_INLINE)
  1412. return ERR_PTR(-EINVAL);
  1413. rqsize = roundup(attrs->cap.max_recv_wr + 1, 16);
  1414. if (rqsize > T4_MAX_RQ_SIZE)
  1415. return ERR_PTR(-E2BIG);
  1416. sqsize = roundup(attrs->cap.max_send_wr + 1, 16);
  1417. if (sqsize > T4_MAX_SQ_SIZE)
  1418. return ERR_PTR(-E2BIG);
  1419. ucontext = pd->uobject ? to_c4iw_ucontext(pd->uobject->context) : NULL;
  1420. qhp = kzalloc(sizeof(*qhp), GFP_KERNEL);
  1421. if (!qhp)
  1422. return ERR_PTR(-ENOMEM);
  1423. qhp->wq.sq.size = sqsize;
  1424. qhp->wq.sq.memsize = (sqsize + 1) * sizeof *qhp->wq.sq.queue;
  1425. qhp->wq.rq.size = rqsize;
  1426. qhp->wq.rq.memsize = (rqsize + 1) * sizeof *qhp->wq.rq.queue;
  1427. if (ucontext) {
  1428. qhp->wq.sq.memsize = roundup(qhp->wq.sq.memsize, PAGE_SIZE);
  1429. qhp->wq.rq.memsize = roundup(qhp->wq.rq.memsize, PAGE_SIZE);
  1430. }
  1431. PDBG("%s sqsize %u sqmemsize %zu rqsize %u rqmemsize %zu\n",
  1432. __func__, sqsize, qhp->wq.sq.memsize, rqsize, qhp->wq.rq.memsize);
  1433. ret = create_qp(&rhp->rdev, &qhp->wq, &schp->cq, &rchp->cq,
  1434. ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
  1435. if (ret)
  1436. goto err1;
  1437. attrs->cap.max_recv_wr = rqsize - 1;
  1438. attrs->cap.max_send_wr = sqsize - 1;
  1439. attrs->cap.max_inline_data = T4_MAX_SEND_INLINE;
  1440. qhp->rhp = rhp;
  1441. qhp->attr.pd = php->pdid;
  1442. qhp->attr.scq = ((struct c4iw_cq *) attrs->send_cq)->cq.cqid;
  1443. qhp->attr.rcq = ((struct c4iw_cq *) attrs->recv_cq)->cq.cqid;
  1444. qhp->attr.sq_num_entries = attrs->cap.max_send_wr;
  1445. qhp->attr.rq_num_entries = attrs->cap.max_recv_wr;
  1446. qhp->attr.sq_max_sges = attrs->cap.max_send_sge;
  1447. qhp->attr.sq_max_sges_rdma_write = attrs->cap.max_send_sge;
  1448. qhp->attr.rq_max_sges = attrs->cap.max_recv_sge;
  1449. qhp->attr.state = C4IW_QP_STATE_IDLE;
  1450. qhp->attr.next_state = C4IW_QP_STATE_IDLE;
  1451. qhp->attr.enable_rdma_read = 1;
  1452. qhp->attr.enable_rdma_write = 1;
  1453. qhp->attr.enable_bind = 1;
  1454. qhp->attr.max_ord = 1;
  1455. qhp->attr.max_ird = 1;
  1456. spin_lock_init(&qhp->lock);
  1457. mutex_init(&qhp->mutex);
  1458. init_waitqueue_head(&qhp->wait);
  1459. atomic_set(&qhp->refcnt, 1);
  1460. spin_lock_irq(&rhp->lock);
  1461. if (rhp->db_state != NORMAL)
  1462. t4_disable_wq_db(&qhp->wq);
  1463. rhp->qpcnt++;
  1464. if (rhp->qpcnt > db_fc_threshold && rhp->db_state == NORMAL) {
  1465. rhp->rdev.stats.db_state_transitions++;
  1466. rhp->db_state = FLOW_CONTROL;
  1467. idr_for_each(&rhp->qpidr, disable_qp_db, NULL);
  1468. }
  1469. if (db_coalescing_threshold >= 0)
  1470. if (rhp->qpcnt > db_coalescing_threshold)
  1471. cxgb4_disable_db_coalescing(rhp->rdev.lldi.ports[0]);
  1472. ret = insert_handle_nolock(rhp, &rhp->qpidr, qhp, qhp->wq.sq.qid);
  1473. spin_unlock_irq(&rhp->lock);
  1474. if (ret)
  1475. goto err2;
  1476. if (udata) {
  1477. mm1 = kmalloc(sizeof *mm1, GFP_KERNEL);
  1478. if (!mm1) {
  1479. ret = -ENOMEM;
  1480. goto err3;
  1481. }
  1482. mm2 = kmalloc(sizeof *mm2, GFP_KERNEL);
  1483. if (!mm2) {
  1484. ret = -ENOMEM;
  1485. goto err4;
  1486. }
  1487. mm3 = kmalloc(sizeof *mm3, GFP_KERNEL);
  1488. if (!mm3) {
  1489. ret = -ENOMEM;
  1490. goto err5;
  1491. }
  1492. mm4 = kmalloc(sizeof *mm4, GFP_KERNEL);
  1493. if (!mm4) {
  1494. ret = -ENOMEM;
  1495. goto err6;
  1496. }
  1497. if (t4_sq_onchip(&qhp->wq.sq)) {
  1498. mm5 = kmalloc(sizeof *mm5, GFP_KERNEL);
  1499. if (!mm5) {
  1500. ret = -ENOMEM;
  1501. goto err7;
  1502. }
  1503. uresp.flags = C4IW_QPF_ONCHIP;
  1504. } else
  1505. uresp.flags = 0;
  1506. uresp.qid_mask = rhp->rdev.qpmask;
  1507. uresp.sqid = qhp->wq.sq.qid;
  1508. uresp.sq_size = qhp->wq.sq.size;
  1509. uresp.sq_memsize = qhp->wq.sq.memsize;
  1510. uresp.rqid = qhp->wq.rq.qid;
  1511. uresp.rq_size = qhp->wq.rq.size;
  1512. uresp.rq_memsize = qhp->wq.rq.memsize;
  1513. spin_lock(&ucontext->mmap_lock);
  1514. if (mm5) {
  1515. uresp.ma_sync_key = ucontext->key;
  1516. ucontext->key += PAGE_SIZE;
  1517. } else {
  1518. uresp.ma_sync_key = 0;
  1519. }
  1520. uresp.sq_key = ucontext->key;
  1521. ucontext->key += PAGE_SIZE;
  1522. uresp.rq_key = ucontext->key;
  1523. ucontext->key += PAGE_SIZE;
  1524. uresp.sq_db_gts_key = ucontext->key;
  1525. ucontext->key += PAGE_SIZE;
  1526. uresp.rq_db_gts_key = ucontext->key;
  1527. ucontext->key += PAGE_SIZE;
  1528. spin_unlock(&ucontext->mmap_lock);
  1529. ret = ib_copy_to_udata(udata, &uresp, sizeof uresp);
  1530. if (ret)
  1531. goto err8;
  1532. mm1->key = uresp.sq_key;
  1533. mm1->addr = qhp->wq.sq.phys_addr;
  1534. mm1->len = PAGE_ALIGN(qhp->wq.sq.memsize);
  1535. insert_mmap(ucontext, mm1);
  1536. mm2->key = uresp.rq_key;
  1537. mm2->addr = virt_to_phys(qhp->wq.rq.queue);
  1538. mm2->len = PAGE_ALIGN(qhp->wq.rq.memsize);
  1539. insert_mmap(ucontext, mm2);
  1540. mm3->key = uresp.sq_db_gts_key;
  1541. mm3->addr = qhp->wq.sq.udb;
  1542. mm3->len = PAGE_SIZE;
  1543. insert_mmap(ucontext, mm3);
  1544. mm4->key = uresp.rq_db_gts_key;
  1545. mm4->addr = qhp->wq.rq.udb;
  1546. mm4->len = PAGE_SIZE;
  1547. insert_mmap(ucontext, mm4);
  1548. if (mm5) {
  1549. mm5->key = uresp.ma_sync_key;
  1550. mm5->addr = (pci_resource_start(rhp->rdev.lldi.pdev, 0)
  1551. + A_PCIE_MA_SYNC) & PAGE_MASK;
  1552. mm5->len = PAGE_SIZE;
  1553. insert_mmap(ucontext, mm5);
  1554. }
  1555. }
  1556. qhp->ibqp.qp_num = qhp->wq.sq.qid;
  1557. init_timer(&(qhp->timer));
  1558. PDBG("%s qhp %p sq_num_entries %d, rq_num_entries %d qpid 0x%0x\n",
  1559. __func__, qhp, qhp->attr.sq_num_entries, qhp->attr.rq_num_entries,
  1560. qhp->wq.sq.qid);
  1561. return &qhp->ibqp;
  1562. err8:
  1563. kfree(mm5);
  1564. err7:
  1565. kfree(mm4);
  1566. err6:
  1567. kfree(mm3);
  1568. err5:
  1569. kfree(mm2);
  1570. err4:
  1571. kfree(mm1);
  1572. err3:
  1573. remove_handle(rhp, &rhp->qpidr, qhp->wq.sq.qid);
  1574. err2:
  1575. destroy_qp(&rhp->rdev, &qhp->wq,
  1576. ucontext ? &ucontext->uctx : &rhp->rdev.uctx);
  1577. err1:
  1578. kfree(qhp);
  1579. return ERR_PTR(ret);
  1580. }
  1581. int c4iw_ib_modify_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1582. int attr_mask, struct ib_udata *udata)
  1583. {
  1584. struct c4iw_dev *rhp;
  1585. struct c4iw_qp *qhp;
  1586. enum c4iw_qp_attr_mask mask = 0;
  1587. struct c4iw_qp_attributes attrs;
  1588. PDBG("%s ib_qp %p\n", __func__, ibqp);
  1589. /* iwarp does not support the RTR state */
  1590. if ((attr_mask & IB_QP_STATE) && (attr->qp_state == IB_QPS_RTR))
  1591. attr_mask &= ~IB_QP_STATE;
  1592. /* Make sure we still have something left to do */
  1593. if (!attr_mask)
  1594. return 0;
  1595. memset(&attrs, 0, sizeof attrs);
  1596. qhp = to_c4iw_qp(ibqp);
  1597. rhp = qhp->rhp;
  1598. attrs.next_state = c4iw_convert_state(attr->qp_state);
  1599. attrs.enable_rdma_read = (attr->qp_access_flags &
  1600. IB_ACCESS_REMOTE_READ) ? 1 : 0;
  1601. attrs.enable_rdma_write = (attr->qp_access_flags &
  1602. IB_ACCESS_REMOTE_WRITE) ? 1 : 0;
  1603. attrs.enable_bind = (attr->qp_access_flags & IB_ACCESS_MW_BIND) ? 1 : 0;
  1604. mask |= (attr_mask & IB_QP_STATE) ? C4IW_QP_ATTR_NEXT_STATE : 0;
  1605. mask |= (attr_mask & IB_QP_ACCESS_FLAGS) ?
  1606. (C4IW_QP_ATTR_ENABLE_RDMA_READ |
  1607. C4IW_QP_ATTR_ENABLE_RDMA_WRITE |
  1608. C4IW_QP_ATTR_ENABLE_RDMA_BIND) : 0;
  1609. /*
  1610. * Use SQ_PSN and RQ_PSN to pass in IDX_INC values for
  1611. * ringing the queue db when we're in DB_FULL mode.
  1612. */
  1613. attrs.sq_db_inc = attr->sq_psn;
  1614. attrs.rq_db_inc = attr->rq_psn;
  1615. mask |= (attr_mask & IB_QP_SQ_PSN) ? C4IW_QP_ATTR_SQ_DB : 0;
  1616. mask |= (attr_mask & IB_QP_RQ_PSN) ? C4IW_QP_ATTR_RQ_DB : 0;
  1617. return c4iw_modify_qp(rhp, qhp, mask, &attrs, 0);
  1618. }
  1619. struct ib_qp *c4iw_get_qp(struct ib_device *dev, int qpn)
  1620. {
  1621. PDBG("%s ib_dev %p qpn 0x%x\n", __func__, dev, qpn);
  1622. return (struct ib_qp *)get_qhp(to_c4iw_dev(dev), qpn);
  1623. }
  1624. int c4iw_ib_query_qp(struct ib_qp *ibqp, struct ib_qp_attr *attr,
  1625. int attr_mask, struct ib_qp_init_attr *init_attr)
  1626. {
  1627. struct c4iw_qp *qhp = to_c4iw_qp(ibqp);
  1628. memset(attr, 0, sizeof *attr);
  1629. memset(init_attr, 0, sizeof *init_attr);
  1630. attr->qp_state = to_ib_qp_state(qhp->attr.state);
  1631. return 0;
  1632. }