perf_event.h 18 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717
  1. /*
  2. * Performance events x86 architecture header
  3. *
  4. * Copyright (C) 2008 Thomas Gleixner <tglx@linutronix.de>
  5. * Copyright (C) 2008-2009 Red Hat, Inc., Ingo Molnar
  6. * Copyright (C) 2009 Jaswinder Singh Rajput
  7. * Copyright (C) 2009 Advanced Micro Devices, Inc., Robert Richter
  8. * Copyright (C) 2008-2009 Red Hat, Inc., Peter Zijlstra <pzijlstr@redhat.com>
  9. * Copyright (C) 2009 Intel Corporation, <markus.t.metzger@intel.com>
  10. * Copyright (C) 2009 Google, Inc., Stephane Eranian
  11. *
  12. * For licencing details see kernel-base/COPYING
  13. */
  14. #include <linux/perf_event.h>
  15. #if 0
  16. #undef wrmsrl
  17. #define wrmsrl(msr, val) \
  18. do { \
  19. unsigned int _msr = (msr); \
  20. u64 _val = (val); \
  21. trace_printk("wrmsrl(%x, %Lx)\n", (unsigned int)(_msr), \
  22. (unsigned long long)(_val)); \
  23. native_write_msr((_msr), (u32)(_val), (u32)(_val >> 32)); \
  24. } while (0)
  25. #endif
  26. /*
  27. * | NHM/WSM | SNB |
  28. * register -------------------------------
  29. * | HT | no HT | HT | no HT |
  30. *-----------------------------------------
  31. * offcore | core | core | cpu | core |
  32. * lbr_sel | core | core | cpu | core |
  33. * ld_lat | cpu | core | cpu | core |
  34. *-----------------------------------------
  35. *
  36. * Given that there is a small number of shared regs,
  37. * we can pre-allocate their slot in the per-cpu
  38. * per-core reg tables.
  39. */
  40. enum extra_reg_type {
  41. EXTRA_REG_NONE = -1, /* not used */
  42. EXTRA_REG_RSP_0 = 0, /* offcore_response_0 */
  43. EXTRA_REG_RSP_1 = 1, /* offcore_response_1 */
  44. EXTRA_REG_LBR = 2, /* lbr_select */
  45. EXTRA_REG_LDLAT = 3, /* ld_lat_threshold */
  46. EXTRA_REG_MAX /* number of entries needed */
  47. };
  48. struct event_constraint {
  49. union {
  50. unsigned long idxmsk[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  51. u64 idxmsk64;
  52. };
  53. u64 code;
  54. u64 cmask;
  55. int weight;
  56. int overlap;
  57. int flags;
  58. };
  59. /*
  60. * struct hw_perf_event.flags flags
  61. */
  62. #define PERF_X86_EVENT_PEBS_LDLAT 0x1 /* ld+ldlat data address sampling */
  63. #define PERF_X86_EVENT_PEBS_ST 0x2 /* st data address sampling */
  64. #define PERF_X86_EVENT_PEBS_ST_HSW 0x4 /* haswell style st data sampling */
  65. #define PERF_X86_EVENT_COMMITTED 0x8 /* event passed commit_txn */
  66. struct amd_nb {
  67. int nb_id; /* NorthBridge id */
  68. int refcnt; /* reference count */
  69. struct perf_event *owners[X86_PMC_IDX_MAX];
  70. struct event_constraint event_constraints[X86_PMC_IDX_MAX];
  71. };
  72. /* The maximal number of PEBS events: */
  73. #define MAX_PEBS_EVENTS 8
  74. /*
  75. * A debug store configuration.
  76. *
  77. * We only support architectures that use 64bit fields.
  78. */
  79. struct debug_store {
  80. u64 bts_buffer_base;
  81. u64 bts_index;
  82. u64 bts_absolute_maximum;
  83. u64 bts_interrupt_threshold;
  84. u64 pebs_buffer_base;
  85. u64 pebs_index;
  86. u64 pebs_absolute_maximum;
  87. u64 pebs_interrupt_threshold;
  88. u64 pebs_event_reset[MAX_PEBS_EVENTS];
  89. };
  90. /*
  91. * Per register state.
  92. */
  93. struct er_account {
  94. raw_spinlock_t lock; /* per-core: protect structure */
  95. u64 config; /* extra MSR config */
  96. u64 reg; /* extra MSR number */
  97. atomic_t ref; /* reference count */
  98. };
  99. /*
  100. * Per core/cpu state
  101. *
  102. * Used to coordinate shared registers between HT threads or
  103. * among events on a single PMU.
  104. */
  105. struct intel_shared_regs {
  106. struct er_account regs[EXTRA_REG_MAX];
  107. int refcnt; /* per-core: #HT threads */
  108. unsigned core_id; /* per-core: core id */
  109. };
  110. #define MAX_LBR_ENTRIES 16
  111. struct cpu_hw_events {
  112. /*
  113. * Generic x86 PMC bits
  114. */
  115. struct perf_event *events[X86_PMC_IDX_MAX]; /* in counter order */
  116. unsigned long active_mask[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  117. unsigned long running[BITS_TO_LONGS(X86_PMC_IDX_MAX)];
  118. int enabled;
  119. int n_events;
  120. int n_added;
  121. int n_txn;
  122. int assign[X86_PMC_IDX_MAX]; /* event to counter assignment */
  123. u64 tags[X86_PMC_IDX_MAX];
  124. struct perf_event *event_list[X86_PMC_IDX_MAX]; /* in enabled order */
  125. unsigned int group_flag;
  126. int is_fake;
  127. /*
  128. * Intel DebugStore bits
  129. */
  130. struct debug_store *ds;
  131. u64 pebs_enabled;
  132. /*
  133. * Intel LBR bits
  134. */
  135. int lbr_users;
  136. void *lbr_context;
  137. struct perf_branch_stack lbr_stack;
  138. struct perf_branch_entry lbr_entries[MAX_LBR_ENTRIES];
  139. struct er_account *lbr_sel;
  140. u64 br_sel;
  141. /*
  142. * Intel host/guest exclude bits
  143. */
  144. u64 intel_ctrl_guest_mask;
  145. u64 intel_ctrl_host_mask;
  146. struct perf_guest_switch_msr guest_switch_msrs[X86_PMC_IDX_MAX];
  147. /*
  148. * manage shared (per-core, per-cpu) registers
  149. * used on Intel NHM/WSM/SNB
  150. */
  151. struct intel_shared_regs *shared_regs;
  152. /*
  153. * AMD specific bits
  154. */
  155. struct amd_nb *amd_nb;
  156. /* Inverted mask of bits to clear in the perf_ctr ctrl registers */
  157. u64 perf_ctr_virt_mask;
  158. void *kfree_on_online;
  159. };
  160. #define __EVENT_CONSTRAINT(c, n, m, w, o, f) {\
  161. { .idxmsk64 = (n) }, \
  162. .code = (c), \
  163. .cmask = (m), \
  164. .weight = (w), \
  165. .overlap = (o), \
  166. .flags = f, \
  167. }
  168. #define EVENT_CONSTRAINT(c, n, m) \
  169. __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 0, 0)
  170. /*
  171. * The overlap flag marks event constraints with overlapping counter
  172. * masks. This is the case if the counter mask of such an event is not
  173. * a subset of any other counter mask of a constraint with an equal or
  174. * higher weight, e.g.:
  175. *
  176. * c_overlaps = EVENT_CONSTRAINT_OVERLAP(0, 0x09, 0);
  177. * c_another1 = EVENT_CONSTRAINT(0, 0x07, 0);
  178. * c_another2 = EVENT_CONSTRAINT(0, 0x38, 0);
  179. *
  180. * The event scheduler may not select the correct counter in the first
  181. * cycle because it needs to know which subsequent events will be
  182. * scheduled. It may fail to schedule the events then. So we set the
  183. * overlap flag for such constraints to give the scheduler a hint which
  184. * events to select for counter rescheduling.
  185. *
  186. * Care must be taken as the rescheduling algorithm is O(n!) which
  187. * will increase scheduling cycles for an over-commited system
  188. * dramatically. The number of such EVENT_CONSTRAINT_OVERLAP() macros
  189. * and its counter masks must be kept at a minimum.
  190. */
  191. #define EVENT_CONSTRAINT_OVERLAP(c, n, m) \
  192. __EVENT_CONSTRAINT(c, n, m, HWEIGHT(n), 1, 0)
  193. /*
  194. * Constraint on the Event code.
  195. */
  196. #define INTEL_EVENT_CONSTRAINT(c, n) \
  197. EVENT_CONSTRAINT(c, n, ARCH_PERFMON_EVENTSEL_EVENT)
  198. /*
  199. * Constraint on the Event code + UMask + fixed-mask
  200. *
  201. * filter mask to validate fixed counter events.
  202. * the following filters disqualify for fixed counters:
  203. * - inv
  204. * - edge
  205. * - cnt-mask
  206. * - in_tx
  207. * - in_tx_checkpointed
  208. * The other filters are supported by fixed counters.
  209. * The any-thread option is supported starting with v3.
  210. */
  211. #define FIXED_EVENT_FLAGS (X86_RAW_EVENT_MASK|HSW_IN_TX|HSW_IN_TX_CHECKPOINTED)
  212. #define FIXED_EVENT_CONSTRAINT(c, n) \
  213. EVENT_CONSTRAINT(c, (1ULL << (32+n)), FIXED_EVENT_FLAGS)
  214. /*
  215. * Constraint on the Event code + UMask
  216. */
  217. #define INTEL_UEVENT_CONSTRAINT(c, n) \
  218. EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK)
  219. #define INTEL_PLD_CONSTRAINT(c, n) \
  220. __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
  221. HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_LDLAT)
  222. #define INTEL_PST_CONSTRAINT(c, n) \
  223. __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
  224. HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST)
  225. /* DataLA version of store sampling without extra enable bit. */
  226. #define INTEL_PST_HSW_CONSTRAINT(c, n) \
  227. __EVENT_CONSTRAINT(c, n, INTEL_ARCH_EVENT_MASK, \
  228. HWEIGHT(n), 0, PERF_X86_EVENT_PEBS_ST_HSW)
  229. #define EVENT_CONSTRAINT_END \
  230. EVENT_CONSTRAINT(0, 0, 0)
  231. #define for_each_event_constraint(e, c) \
  232. for ((e) = (c); (e)->weight; (e)++)
  233. /*
  234. * Extra registers for specific events.
  235. *
  236. * Some events need large masks and require external MSRs.
  237. * Those extra MSRs end up being shared for all events on
  238. * a PMU and sometimes between PMU of sibling HT threads.
  239. * In either case, the kernel needs to handle conflicting
  240. * accesses to those extra, shared, regs. The data structure
  241. * to manage those registers is stored in cpu_hw_event.
  242. */
  243. struct extra_reg {
  244. unsigned int event;
  245. unsigned int msr;
  246. u64 config_mask;
  247. u64 valid_mask;
  248. int idx; /* per_xxx->regs[] reg index */
  249. };
  250. #define EVENT_EXTRA_REG(e, ms, m, vm, i) { \
  251. .event = (e), \
  252. .msr = (ms), \
  253. .config_mask = (m), \
  254. .valid_mask = (vm), \
  255. .idx = EXTRA_REG_##i, \
  256. }
  257. #define INTEL_EVENT_EXTRA_REG(event, msr, vm, idx) \
  258. EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT, vm, idx)
  259. #define INTEL_UEVENT_EXTRA_REG(event, msr, vm, idx) \
  260. EVENT_EXTRA_REG(event, msr, ARCH_PERFMON_EVENTSEL_EVENT | \
  261. ARCH_PERFMON_EVENTSEL_UMASK, vm, idx)
  262. #define INTEL_UEVENT_PEBS_LDLAT_EXTRA_REG(c) \
  263. INTEL_UEVENT_EXTRA_REG(c, \
  264. MSR_PEBS_LD_LAT_THRESHOLD, \
  265. 0xffff, \
  266. LDLAT)
  267. #define EVENT_EXTRA_END EVENT_EXTRA_REG(0, 0, 0, 0, RSP_0)
  268. union perf_capabilities {
  269. struct {
  270. u64 lbr_format:6;
  271. u64 pebs_trap:1;
  272. u64 pebs_arch_reg:1;
  273. u64 pebs_format:4;
  274. u64 smm_freeze:1;
  275. /*
  276. * PMU supports separate counter range for writing
  277. * values > 32bit.
  278. */
  279. u64 full_width_write:1;
  280. };
  281. u64 capabilities;
  282. };
  283. struct x86_pmu_quirk {
  284. struct x86_pmu_quirk *next;
  285. void (*func)(void);
  286. };
  287. union x86_pmu_config {
  288. struct {
  289. u64 event:8,
  290. umask:8,
  291. usr:1,
  292. os:1,
  293. edge:1,
  294. pc:1,
  295. interrupt:1,
  296. __reserved1:1,
  297. en:1,
  298. inv:1,
  299. cmask:8,
  300. event2:4,
  301. __reserved2:4,
  302. go:1,
  303. ho:1;
  304. } bits;
  305. u64 value;
  306. };
  307. #define X86_CONFIG(args...) ((union x86_pmu_config){.bits = {args}}).value
  308. /*
  309. * struct x86_pmu - generic x86 pmu
  310. */
  311. struct x86_pmu {
  312. /*
  313. * Generic x86 PMC bits
  314. */
  315. const char *name;
  316. int version;
  317. int (*handle_irq)(struct pt_regs *);
  318. void (*disable_all)(void);
  319. void (*enable_all)(int added);
  320. void (*enable)(struct perf_event *);
  321. void (*disable)(struct perf_event *);
  322. int (*hw_config)(struct perf_event *event);
  323. int (*schedule_events)(struct cpu_hw_events *cpuc, int n, int *assign);
  324. unsigned eventsel;
  325. unsigned perfctr;
  326. int (*addr_offset)(int index, bool eventsel);
  327. int (*rdpmc_index)(int index);
  328. u64 (*event_map)(int);
  329. int max_events;
  330. int num_counters;
  331. int num_counters_fixed;
  332. int cntval_bits;
  333. u64 cntval_mask;
  334. union {
  335. unsigned long events_maskl;
  336. unsigned long events_mask[BITS_TO_LONGS(ARCH_PERFMON_EVENTS_COUNT)];
  337. };
  338. int events_mask_len;
  339. int apic;
  340. u64 max_period;
  341. struct event_constraint *
  342. (*get_event_constraints)(struct cpu_hw_events *cpuc,
  343. struct perf_event *event);
  344. void (*put_event_constraints)(struct cpu_hw_events *cpuc,
  345. struct perf_event *event);
  346. struct event_constraint *event_constraints;
  347. struct x86_pmu_quirk *quirks;
  348. int perfctr_second_write;
  349. bool late_ack;
  350. /*
  351. * sysfs attrs
  352. */
  353. int attr_rdpmc;
  354. struct attribute **format_attrs;
  355. struct attribute **event_attrs;
  356. ssize_t (*events_sysfs_show)(char *page, u64 config);
  357. struct attribute **cpu_events;
  358. /*
  359. * CPU Hotplug hooks
  360. */
  361. int (*cpu_prepare)(int cpu);
  362. void (*cpu_starting)(int cpu);
  363. void (*cpu_dying)(int cpu);
  364. void (*cpu_dead)(int cpu);
  365. void (*check_microcode)(void);
  366. void (*flush_branch_stack)(void);
  367. /*
  368. * Intel Arch Perfmon v2+
  369. */
  370. u64 intel_ctrl;
  371. union perf_capabilities intel_cap;
  372. /*
  373. * Intel DebugStore bits
  374. */
  375. unsigned int bts :1,
  376. bts_active :1,
  377. pebs :1,
  378. pebs_active :1,
  379. pebs_broken :1;
  380. int pebs_record_size;
  381. void (*drain_pebs)(struct pt_regs *regs);
  382. struct event_constraint *pebs_constraints;
  383. void (*pebs_aliases)(struct perf_event *event);
  384. int max_pebs_events;
  385. /*
  386. * Intel LBR
  387. */
  388. unsigned long lbr_tos, lbr_from, lbr_to; /* MSR base regs */
  389. int lbr_nr; /* hardware stack size */
  390. u64 lbr_sel_mask; /* LBR_SELECT valid bits */
  391. const int *lbr_sel_map; /* lbr_select mappings */
  392. /*
  393. * Extra registers for events
  394. */
  395. struct extra_reg *extra_regs;
  396. unsigned int er_flags;
  397. /*
  398. * Intel host/guest support (KVM)
  399. */
  400. struct perf_guest_switch_msr *(*guest_get_msrs)(int *nr);
  401. };
  402. #define x86_add_quirk(func_) \
  403. do { \
  404. static struct x86_pmu_quirk __quirk __initdata = { \
  405. .func = func_, \
  406. }; \
  407. __quirk.next = x86_pmu.quirks; \
  408. x86_pmu.quirks = &__quirk; \
  409. } while (0)
  410. #define ERF_NO_HT_SHARING 1
  411. #define ERF_HAS_RSP_1 2
  412. #define EVENT_VAR(_id) event_attr_##_id
  413. #define EVENT_PTR(_id) &event_attr_##_id.attr.attr
  414. #define EVENT_ATTR(_name, _id) \
  415. static struct perf_pmu_events_attr EVENT_VAR(_id) = { \
  416. .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
  417. .id = PERF_COUNT_HW_##_id, \
  418. .event_str = NULL, \
  419. };
  420. #define EVENT_ATTR_STR(_name, v, str) \
  421. static struct perf_pmu_events_attr event_attr_##v = { \
  422. .attr = __ATTR(_name, 0444, events_sysfs_show, NULL), \
  423. .id = 0, \
  424. .event_str = str, \
  425. };
  426. extern struct x86_pmu x86_pmu __read_mostly;
  427. DECLARE_PER_CPU(struct cpu_hw_events, cpu_hw_events);
  428. int x86_perf_event_set_period(struct perf_event *event);
  429. /*
  430. * Generalized hw caching related hw_event table, filled
  431. * in on a per model basis. A value of 0 means
  432. * 'not supported', -1 means 'hw_event makes no sense on
  433. * this CPU', any other value means the raw hw_event
  434. * ID.
  435. */
  436. #define C(x) PERF_COUNT_HW_CACHE_##x
  437. extern u64 __read_mostly hw_cache_event_ids
  438. [PERF_COUNT_HW_CACHE_MAX]
  439. [PERF_COUNT_HW_CACHE_OP_MAX]
  440. [PERF_COUNT_HW_CACHE_RESULT_MAX];
  441. extern u64 __read_mostly hw_cache_extra_regs
  442. [PERF_COUNT_HW_CACHE_MAX]
  443. [PERF_COUNT_HW_CACHE_OP_MAX]
  444. [PERF_COUNT_HW_CACHE_RESULT_MAX];
  445. u64 x86_perf_event_update(struct perf_event *event);
  446. static inline unsigned int x86_pmu_config_addr(int index)
  447. {
  448. return x86_pmu.eventsel + (x86_pmu.addr_offset ?
  449. x86_pmu.addr_offset(index, true) : index);
  450. }
  451. static inline unsigned int x86_pmu_event_addr(int index)
  452. {
  453. return x86_pmu.perfctr + (x86_pmu.addr_offset ?
  454. x86_pmu.addr_offset(index, false) : index);
  455. }
  456. static inline int x86_pmu_rdpmc_index(int index)
  457. {
  458. return x86_pmu.rdpmc_index ? x86_pmu.rdpmc_index(index) : index;
  459. }
  460. int x86_setup_perfctr(struct perf_event *event);
  461. int x86_pmu_hw_config(struct perf_event *event);
  462. void x86_pmu_disable_all(void);
  463. static inline void __x86_pmu_enable_event(struct hw_perf_event *hwc,
  464. u64 enable_mask)
  465. {
  466. u64 disable_mask = __this_cpu_read(cpu_hw_events.perf_ctr_virt_mask);
  467. if (hwc->extra_reg.reg)
  468. wrmsrl(hwc->extra_reg.reg, hwc->extra_reg.config);
  469. wrmsrl(hwc->config_base, (hwc->config | enable_mask) & ~disable_mask);
  470. }
  471. void x86_pmu_enable_all(int added);
  472. int perf_assign_events(struct perf_event **events, int n,
  473. int wmin, int wmax, int *assign);
  474. int x86_schedule_events(struct cpu_hw_events *cpuc, int n, int *assign);
  475. void x86_pmu_stop(struct perf_event *event, int flags);
  476. static inline void x86_pmu_disable_event(struct perf_event *event)
  477. {
  478. struct hw_perf_event *hwc = &event->hw;
  479. wrmsrl(hwc->config_base, hwc->config);
  480. }
  481. void x86_pmu_enable_event(struct perf_event *event);
  482. int x86_pmu_handle_irq(struct pt_regs *regs);
  483. extern struct event_constraint emptyconstraint;
  484. extern struct event_constraint unconstrained;
  485. static inline bool kernel_ip(unsigned long ip)
  486. {
  487. #ifdef CONFIG_X86_32
  488. return ip > PAGE_OFFSET;
  489. #else
  490. return (long)ip < 0;
  491. #endif
  492. }
  493. /*
  494. * Not all PMUs provide the right context information to place the reported IP
  495. * into full context. Specifically segment registers are typically not
  496. * supplied.
  497. *
  498. * Assuming the address is a linear address (it is for IBS), we fake the CS and
  499. * vm86 mode using the known zero-based code segment and 'fix up' the registers
  500. * to reflect this.
  501. *
  502. * Intel PEBS/LBR appear to typically provide the effective address, nothing
  503. * much we can do about that but pray and treat it like a linear address.
  504. */
  505. static inline void set_linear_ip(struct pt_regs *regs, unsigned long ip)
  506. {
  507. regs->cs = kernel_ip(ip) ? __KERNEL_CS : __USER_CS;
  508. if (regs->flags & X86_VM_MASK)
  509. regs->flags ^= (PERF_EFLAGS_VM | X86_VM_MASK);
  510. regs->ip = ip;
  511. }
  512. ssize_t x86_event_sysfs_show(char *page, u64 config, u64 event);
  513. ssize_t intel_event_sysfs_show(char *page, u64 config);
  514. #ifdef CONFIG_CPU_SUP_AMD
  515. int amd_pmu_init(void);
  516. #else /* CONFIG_CPU_SUP_AMD */
  517. static inline int amd_pmu_init(void)
  518. {
  519. return 0;
  520. }
  521. #endif /* CONFIG_CPU_SUP_AMD */
  522. #ifdef CONFIG_CPU_SUP_INTEL
  523. int intel_pmu_save_and_restart(struct perf_event *event);
  524. struct event_constraint *
  525. x86_get_event_constraints(struct cpu_hw_events *cpuc, struct perf_event *event);
  526. struct intel_shared_regs *allocate_shared_regs(int cpu);
  527. int intel_pmu_init(void);
  528. void init_debug_store_on_cpu(int cpu);
  529. void fini_debug_store_on_cpu(int cpu);
  530. void release_ds_buffers(void);
  531. void reserve_ds_buffers(void);
  532. extern struct event_constraint bts_constraint;
  533. void intel_pmu_enable_bts(u64 config);
  534. void intel_pmu_disable_bts(void);
  535. int intel_pmu_drain_bts_buffer(void);
  536. extern struct event_constraint intel_core2_pebs_event_constraints[];
  537. extern struct event_constraint intel_atom_pebs_event_constraints[];
  538. extern struct event_constraint intel_nehalem_pebs_event_constraints[];
  539. extern struct event_constraint intel_westmere_pebs_event_constraints[];
  540. extern struct event_constraint intel_snb_pebs_event_constraints[];
  541. extern struct event_constraint intel_ivb_pebs_event_constraints[];
  542. extern struct event_constraint intel_hsw_pebs_event_constraints[];
  543. struct event_constraint *intel_pebs_constraints(struct perf_event *event);
  544. void intel_pmu_pebs_enable(struct perf_event *event);
  545. void intel_pmu_pebs_disable(struct perf_event *event);
  546. void intel_pmu_pebs_enable_all(void);
  547. void intel_pmu_pebs_disable_all(void);
  548. void intel_ds_init(void);
  549. void intel_pmu_lbr_reset(void);
  550. void intel_pmu_lbr_enable(struct perf_event *event);
  551. void intel_pmu_lbr_disable(struct perf_event *event);
  552. void intel_pmu_lbr_enable_all(void);
  553. void intel_pmu_lbr_disable_all(void);
  554. void intel_pmu_lbr_read(void);
  555. void intel_pmu_lbr_init_core(void);
  556. void intel_pmu_lbr_init_nhm(void);
  557. void intel_pmu_lbr_init_atom(void);
  558. void intel_pmu_lbr_init_snb(void);
  559. int intel_pmu_setup_lbr_filter(struct perf_event *event);
  560. int p4_pmu_init(void);
  561. int p6_pmu_init(void);
  562. int knc_pmu_init(void);
  563. ssize_t events_sysfs_show(struct device *dev, struct device_attribute *attr,
  564. char *page);
  565. #else /* CONFIG_CPU_SUP_INTEL */
  566. static inline void reserve_ds_buffers(void)
  567. {
  568. }
  569. static inline void release_ds_buffers(void)
  570. {
  571. }
  572. static inline int intel_pmu_init(void)
  573. {
  574. return 0;
  575. }
  576. static inline struct intel_shared_regs *allocate_shared_regs(int cpu)
  577. {
  578. return NULL;
  579. }
  580. #endif /* CONFIG_CPU_SUP_INTEL */