therm_throt.c 16 KB

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  1. /*
  2. * Thermal throttle event support code (such as syslog messaging and rate
  3. * limiting) that was factored out from x86_64 (mce_intel.c) and i386 (p4.c).
  4. *
  5. * This allows consistent reporting of CPU thermal throttle events.
  6. *
  7. * Maintains a counter in /sys that keeps track of the number of thermal
  8. * events, such that the user knows how bad the thermal problem might be
  9. * (since the logging to syslog and mcelog is rate limited).
  10. *
  11. * Author: Dmitriy Zavin (dmitriyz@google.com)
  12. *
  13. * Credits: Adapted from Zwane Mwaikambo's original code in mce_intel.c.
  14. * Inspired by Ross Biro's and Al Borchers' counter code.
  15. */
  16. #include <linux/interrupt.h>
  17. #include <linux/notifier.h>
  18. #include <linux/jiffies.h>
  19. #include <linux/kernel.h>
  20. #include <linux/percpu.h>
  21. #include <linux/export.h>
  22. #include <linux/types.h>
  23. #include <linux/init.h>
  24. #include <linux/smp.h>
  25. #include <linux/cpu.h>
  26. #include <asm/processor.h>
  27. #include <asm/apic.h>
  28. #include <asm/idle.h>
  29. #include <asm/mce.h>
  30. #include <asm/msr.h>
  31. #include <asm/trace/irq_vectors.h>
  32. /* How long to wait between reporting thermal events */
  33. #define CHECK_INTERVAL (300 * HZ)
  34. #define THERMAL_THROTTLING_EVENT 0
  35. #define POWER_LIMIT_EVENT 1
  36. /*
  37. * Current thermal event state:
  38. */
  39. struct _thermal_state {
  40. bool new_event;
  41. int event;
  42. u64 next_check;
  43. unsigned long count;
  44. unsigned long last_count;
  45. };
  46. struct thermal_state {
  47. struct _thermal_state core_throttle;
  48. struct _thermal_state core_power_limit;
  49. struct _thermal_state package_throttle;
  50. struct _thermal_state package_power_limit;
  51. struct _thermal_state core_thresh0;
  52. struct _thermal_state core_thresh1;
  53. struct _thermal_state pkg_thresh0;
  54. struct _thermal_state pkg_thresh1;
  55. };
  56. /* Callback to handle core threshold interrupts */
  57. int (*platform_thermal_notify)(__u64 msr_val);
  58. EXPORT_SYMBOL(platform_thermal_notify);
  59. /* Callback to handle core package threshold_interrupts */
  60. int (*platform_thermal_package_notify)(__u64 msr_val);
  61. EXPORT_SYMBOL_GPL(platform_thermal_package_notify);
  62. /* Callback support of rate control, return true, if
  63. * callback has rate control */
  64. bool (*platform_thermal_package_rate_control)(void);
  65. EXPORT_SYMBOL_GPL(platform_thermal_package_rate_control);
  66. static DEFINE_PER_CPU(struct thermal_state, thermal_state);
  67. static atomic_t therm_throt_en = ATOMIC_INIT(0);
  68. static u32 lvtthmr_init __read_mostly;
  69. #ifdef CONFIG_SYSFS
  70. #define define_therm_throt_device_one_ro(_name) \
  71. static DEVICE_ATTR(_name, 0444, \
  72. therm_throt_device_show_##_name, \
  73. NULL) \
  74. #define define_therm_throt_device_show_func(event, name) \
  75. \
  76. static ssize_t therm_throt_device_show_##event##_##name( \
  77. struct device *dev, \
  78. struct device_attribute *attr, \
  79. char *buf) \
  80. { \
  81. unsigned int cpu = dev->id; \
  82. ssize_t ret; \
  83. \
  84. preempt_disable(); /* CPU hotplug */ \
  85. if (cpu_online(cpu)) { \
  86. ret = sprintf(buf, "%lu\n", \
  87. per_cpu(thermal_state, cpu).event.name); \
  88. } else \
  89. ret = 0; \
  90. preempt_enable(); \
  91. \
  92. return ret; \
  93. }
  94. define_therm_throt_device_show_func(core_throttle, count);
  95. define_therm_throt_device_one_ro(core_throttle_count);
  96. define_therm_throt_device_show_func(core_power_limit, count);
  97. define_therm_throt_device_one_ro(core_power_limit_count);
  98. define_therm_throt_device_show_func(package_throttle, count);
  99. define_therm_throt_device_one_ro(package_throttle_count);
  100. define_therm_throt_device_show_func(package_power_limit, count);
  101. define_therm_throt_device_one_ro(package_power_limit_count);
  102. static struct attribute *thermal_throttle_attrs[] = {
  103. &dev_attr_core_throttle_count.attr,
  104. NULL
  105. };
  106. static struct attribute_group thermal_attr_group = {
  107. .attrs = thermal_throttle_attrs,
  108. .name = "thermal_throttle"
  109. };
  110. #endif /* CONFIG_SYSFS */
  111. #define CORE_LEVEL 0
  112. #define PACKAGE_LEVEL 1
  113. /***
  114. * therm_throt_process - Process thermal throttling event from interrupt
  115. * @curr: Whether the condition is current or not (boolean), since the
  116. * thermal interrupt normally gets called both when the thermal
  117. * event begins and once the event has ended.
  118. *
  119. * This function is called by the thermal interrupt after the
  120. * IRQ has been acknowledged.
  121. *
  122. * It will take care of rate limiting and printing messages to the syslog.
  123. *
  124. * Returns: 0 : Event should NOT be further logged, i.e. still in
  125. * "timeout" from previous log message.
  126. * 1 : Event should be logged further, and a message has been
  127. * printed to the syslog.
  128. */
  129. static int therm_throt_process(bool new_event, int event, int level)
  130. {
  131. struct _thermal_state *state;
  132. unsigned int this_cpu = smp_processor_id();
  133. bool old_event;
  134. u64 now;
  135. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  136. now = get_jiffies_64();
  137. if (level == CORE_LEVEL) {
  138. if (event == THERMAL_THROTTLING_EVENT)
  139. state = &pstate->core_throttle;
  140. else if (event == POWER_LIMIT_EVENT)
  141. state = &pstate->core_power_limit;
  142. else
  143. return 0;
  144. } else if (level == PACKAGE_LEVEL) {
  145. if (event == THERMAL_THROTTLING_EVENT)
  146. state = &pstate->package_throttle;
  147. else if (event == POWER_LIMIT_EVENT)
  148. state = &pstate->package_power_limit;
  149. else
  150. return 0;
  151. } else
  152. return 0;
  153. old_event = state->new_event;
  154. state->new_event = new_event;
  155. if (new_event)
  156. state->count++;
  157. if (time_before64(now, state->next_check) &&
  158. state->count != state->last_count)
  159. return 0;
  160. state->next_check = now + CHECK_INTERVAL;
  161. state->last_count = state->count;
  162. /* if we just entered the thermal event */
  163. if (new_event) {
  164. if (event == THERMAL_THROTTLING_EVENT)
  165. printk(KERN_CRIT "CPU%d: %s temperature above threshold, cpu clock throttled (total events = %lu)\n",
  166. this_cpu,
  167. level == CORE_LEVEL ? "Core" : "Package",
  168. state->count);
  169. return 1;
  170. }
  171. if (old_event) {
  172. if (event == THERMAL_THROTTLING_EVENT)
  173. printk(KERN_INFO "CPU%d: %s temperature/speed normal\n",
  174. this_cpu,
  175. level == CORE_LEVEL ? "Core" : "Package");
  176. return 1;
  177. }
  178. return 0;
  179. }
  180. static int thresh_event_valid(int level, int event)
  181. {
  182. struct _thermal_state *state;
  183. unsigned int this_cpu = smp_processor_id();
  184. struct thermal_state *pstate = &per_cpu(thermal_state, this_cpu);
  185. u64 now = get_jiffies_64();
  186. if (level == PACKAGE_LEVEL)
  187. state = (event == 0) ? &pstate->pkg_thresh0 :
  188. &pstate->pkg_thresh1;
  189. else
  190. state = (event == 0) ? &pstate->core_thresh0 :
  191. &pstate->core_thresh1;
  192. if (time_before64(now, state->next_check))
  193. return 0;
  194. state->next_check = now + CHECK_INTERVAL;
  195. return 1;
  196. }
  197. static bool int_pln_enable;
  198. static int __init int_pln_enable_setup(char *s)
  199. {
  200. int_pln_enable = true;
  201. return 1;
  202. }
  203. __setup("int_pln_enable", int_pln_enable_setup);
  204. #ifdef CONFIG_SYSFS
  205. /* Add/Remove thermal_throttle interface for CPU device: */
  206. static int thermal_throttle_add_dev(struct device *dev, unsigned int cpu)
  207. {
  208. int err;
  209. struct cpuinfo_x86 *c = &cpu_data(cpu);
  210. err = sysfs_create_group(&dev->kobj, &thermal_attr_group);
  211. if (err)
  212. return err;
  213. if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
  214. err = sysfs_add_file_to_group(&dev->kobj,
  215. &dev_attr_core_power_limit_count.attr,
  216. thermal_attr_group.name);
  217. if (cpu_has(c, X86_FEATURE_PTS)) {
  218. err = sysfs_add_file_to_group(&dev->kobj,
  219. &dev_attr_package_throttle_count.attr,
  220. thermal_attr_group.name);
  221. if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
  222. err = sysfs_add_file_to_group(&dev->kobj,
  223. &dev_attr_package_power_limit_count.attr,
  224. thermal_attr_group.name);
  225. }
  226. return err;
  227. }
  228. static void thermal_throttle_remove_dev(struct device *dev)
  229. {
  230. sysfs_remove_group(&dev->kobj, &thermal_attr_group);
  231. }
  232. /* Mutex protecting device creation against CPU hotplug: */
  233. static DEFINE_MUTEX(therm_cpu_lock);
  234. /* Get notified when a cpu comes on/off. Be hotplug friendly. */
  235. static int
  236. thermal_throttle_cpu_callback(struct notifier_block *nfb,
  237. unsigned long action,
  238. void *hcpu)
  239. {
  240. unsigned int cpu = (unsigned long)hcpu;
  241. struct device *dev;
  242. int err = 0;
  243. dev = get_cpu_device(cpu);
  244. switch (action) {
  245. case CPU_UP_PREPARE:
  246. case CPU_UP_PREPARE_FROZEN:
  247. mutex_lock(&therm_cpu_lock);
  248. err = thermal_throttle_add_dev(dev, cpu);
  249. mutex_unlock(&therm_cpu_lock);
  250. WARN_ON(err);
  251. break;
  252. case CPU_UP_CANCELED:
  253. case CPU_UP_CANCELED_FROZEN:
  254. case CPU_DEAD:
  255. case CPU_DEAD_FROZEN:
  256. mutex_lock(&therm_cpu_lock);
  257. thermal_throttle_remove_dev(dev);
  258. mutex_unlock(&therm_cpu_lock);
  259. break;
  260. }
  261. return notifier_from_errno(err);
  262. }
  263. static struct notifier_block thermal_throttle_cpu_notifier =
  264. {
  265. .notifier_call = thermal_throttle_cpu_callback,
  266. };
  267. static __init int thermal_throttle_init_device(void)
  268. {
  269. unsigned int cpu = 0;
  270. int err;
  271. if (!atomic_read(&therm_throt_en))
  272. return 0;
  273. register_hotcpu_notifier(&thermal_throttle_cpu_notifier);
  274. #ifdef CONFIG_HOTPLUG_CPU
  275. mutex_lock(&therm_cpu_lock);
  276. #endif
  277. /* connect live CPUs to sysfs */
  278. for_each_online_cpu(cpu) {
  279. err = thermal_throttle_add_dev(get_cpu_device(cpu), cpu);
  280. WARN_ON(err);
  281. }
  282. #ifdef CONFIG_HOTPLUG_CPU
  283. mutex_unlock(&therm_cpu_lock);
  284. #endif
  285. return 0;
  286. }
  287. device_initcall(thermal_throttle_init_device);
  288. #endif /* CONFIG_SYSFS */
  289. static void notify_package_thresholds(__u64 msr_val)
  290. {
  291. bool notify_thres_0 = false;
  292. bool notify_thres_1 = false;
  293. if (!platform_thermal_package_notify)
  294. return;
  295. /* lower threshold check */
  296. if (msr_val & THERM_LOG_THRESHOLD0)
  297. notify_thres_0 = true;
  298. /* higher threshold check */
  299. if (msr_val & THERM_LOG_THRESHOLD1)
  300. notify_thres_1 = true;
  301. if (!notify_thres_0 && !notify_thres_1)
  302. return;
  303. if (platform_thermal_package_rate_control &&
  304. platform_thermal_package_rate_control()) {
  305. /* Rate control is implemented in callback */
  306. platform_thermal_package_notify(msr_val);
  307. return;
  308. }
  309. /* lower threshold reached */
  310. if (notify_thres_0 && thresh_event_valid(PACKAGE_LEVEL, 0))
  311. platform_thermal_package_notify(msr_val);
  312. /* higher threshold reached */
  313. if (notify_thres_1 && thresh_event_valid(PACKAGE_LEVEL, 1))
  314. platform_thermal_package_notify(msr_val);
  315. }
  316. static void notify_thresholds(__u64 msr_val)
  317. {
  318. /* check whether the interrupt handler is defined;
  319. * otherwise simply return
  320. */
  321. if (!platform_thermal_notify)
  322. return;
  323. /* lower threshold reached */
  324. if ((msr_val & THERM_LOG_THRESHOLD0) &&
  325. thresh_event_valid(CORE_LEVEL, 0))
  326. platform_thermal_notify(msr_val);
  327. /* higher threshold reached */
  328. if ((msr_val & THERM_LOG_THRESHOLD1) &&
  329. thresh_event_valid(CORE_LEVEL, 1))
  330. platform_thermal_notify(msr_val);
  331. }
  332. /* Thermal transition interrupt handler */
  333. static void intel_thermal_interrupt(void)
  334. {
  335. __u64 msr_val;
  336. rdmsrl(MSR_IA32_THERM_STATUS, msr_val);
  337. /* Check for violation of core thermal thresholds*/
  338. notify_thresholds(msr_val);
  339. if (therm_throt_process(msr_val & THERM_STATUS_PROCHOT,
  340. THERMAL_THROTTLING_EVENT,
  341. CORE_LEVEL) != 0)
  342. mce_log_therm_throt_event(msr_val);
  343. if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
  344. therm_throt_process(msr_val & THERM_STATUS_POWER_LIMIT,
  345. POWER_LIMIT_EVENT,
  346. CORE_LEVEL);
  347. if (this_cpu_has(X86_FEATURE_PTS)) {
  348. rdmsrl(MSR_IA32_PACKAGE_THERM_STATUS, msr_val);
  349. /* check violations of package thermal thresholds */
  350. notify_package_thresholds(msr_val);
  351. therm_throt_process(msr_val & PACKAGE_THERM_STATUS_PROCHOT,
  352. THERMAL_THROTTLING_EVENT,
  353. PACKAGE_LEVEL);
  354. if (this_cpu_has(X86_FEATURE_PLN) && int_pln_enable)
  355. therm_throt_process(msr_val &
  356. PACKAGE_THERM_STATUS_POWER_LIMIT,
  357. POWER_LIMIT_EVENT,
  358. PACKAGE_LEVEL);
  359. }
  360. }
  361. static void unexpected_thermal_interrupt(void)
  362. {
  363. printk(KERN_ERR "CPU%d: Unexpected LVT thermal interrupt!\n",
  364. smp_processor_id());
  365. }
  366. static void (*smp_thermal_vector)(void) = unexpected_thermal_interrupt;
  367. static inline void __smp_thermal_interrupt(void)
  368. {
  369. inc_irq_stat(irq_thermal_count);
  370. smp_thermal_vector();
  371. }
  372. asmlinkage void smp_thermal_interrupt(struct pt_regs *regs)
  373. {
  374. entering_irq();
  375. __smp_thermal_interrupt();
  376. exiting_ack_irq();
  377. }
  378. asmlinkage void smp_trace_thermal_interrupt(struct pt_regs *regs)
  379. {
  380. entering_irq();
  381. trace_thermal_apic_entry(THERMAL_APIC_VECTOR);
  382. __smp_thermal_interrupt();
  383. trace_thermal_apic_exit(THERMAL_APIC_VECTOR);
  384. exiting_ack_irq();
  385. }
  386. /* Thermal monitoring depends on APIC, ACPI and clock modulation */
  387. static int intel_thermal_supported(struct cpuinfo_x86 *c)
  388. {
  389. if (!cpu_has_apic)
  390. return 0;
  391. if (!cpu_has(c, X86_FEATURE_ACPI) || !cpu_has(c, X86_FEATURE_ACC))
  392. return 0;
  393. return 1;
  394. }
  395. void __init mcheck_intel_therm_init(void)
  396. {
  397. /*
  398. * This function is only called on boot CPU. Save the init thermal
  399. * LVT value on BSP and use that value to restore APs' thermal LVT
  400. * entry BIOS programmed later
  401. */
  402. if (intel_thermal_supported(&boot_cpu_data))
  403. lvtthmr_init = apic_read(APIC_LVTTHMR);
  404. }
  405. void intel_init_thermal(struct cpuinfo_x86 *c)
  406. {
  407. unsigned int cpu = smp_processor_id();
  408. int tm2 = 0;
  409. u32 l, h;
  410. if (!intel_thermal_supported(c))
  411. return;
  412. /*
  413. * First check if its enabled already, in which case there might
  414. * be some SMM goo which handles it, so we can't even put a handler
  415. * since it might be delivered via SMI already:
  416. */
  417. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  418. h = lvtthmr_init;
  419. /*
  420. * The initial value of thermal LVT entries on all APs always reads
  421. * 0x10000 because APs are woken up by BSP issuing INIT-SIPI-SIPI
  422. * sequence to them and LVT registers are reset to 0s except for
  423. * the mask bits which are set to 1s when APs receive INIT IPI.
  424. * If BIOS takes over the thermal interrupt and sets its interrupt
  425. * delivery mode to SMI (not fixed), it restores the value that the
  426. * BIOS has programmed on AP based on BSP's info we saved since BIOS
  427. * is always setting the same value for all threads/cores.
  428. */
  429. if ((h & APIC_DM_FIXED_MASK) != APIC_DM_FIXED)
  430. apic_write(APIC_LVTTHMR, lvtthmr_init);
  431. if ((l & MSR_IA32_MISC_ENABLE_TM1) && (h & APIC_DM_SMI)) {
  432. printk(KERN_DEBUG
  433. "CPU%d: Thermal monitoring handled by SMI\n", cpu);
  434. return;
  435. }
  436. /* Check whether a vector already exists */
  437. if (h & APIC_VECTOR_MASK) {
  438. printk(KERN_DEBUG
  439. "CPU%d: Thermal LVT vector (%#x) already installed\n",
  440. cpu, (h & APIC_VECTOR_MASK));
  441. return;
  442. }
  443. /* early Pentium M models use different method for enabling TM2 */
  444. if (cpu_has(c, X86_FEATURE_TM2)) {
  445. if (c->x86 == 6 && (c->x86_model == 9 || c->x86_model == 13)) {
  446. rdmsr(MSR_THERM2_CTL, l, h);
  447. if (l & MSR_THERM2_CTL_TM_SELECT)
  448. tm2 = 1;
  449. } else if (l & MSR_IA32_MISC_ENABLE_TM2)
  450. tm2 = 1;
  451. }
  452. /* We'll mask the thermal vector in the lapic till we're ready: */
  453. h = THERMAL_APIC_VECTOR | APIC_DM_FIXED | APIC_LVT_MASKED;
  454. apic_write(APIC_LVTTHMR, h);
  455. rdmsr(MSR_IA32_THERM_INTERRUPT, l, h);
  456. if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
  457. wrmsr(MSR_IA32_THERM_INTERRUPT,
  458. (l | (THERM_INT_LOW_ENABLE
  459. | THERM_INT_HIGH_ENABLE)) & ~THERM_INT_PLN_ENABLE, h);
  460. else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
  461. wrmsr(MSR_IA32_THERM_INTERRUPT,
  462. l | (THERM_INT_LOW_ENABLE
  463. | THERM_INT_HIGH_ENABLE | THERM_INT_PLN_ENABLE), h);
  464. else
  465. wrmsr(MSR_IA32_THERM_INTERRUPT,
  466. l | (THERM_INT_LOW_ENABLE | THERM_INT_HIGH_ENABLE), h);
  467. if (cpu_has(c, X86_FEATURE_PTS)) {
  468. rdmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT, l, h);
  469. if (cpu_has(c, X86_FEATURE_PLN) && !int_pln_enable)
  470. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  471. (l | (PACKAGE_THERM_INT_LOW_ENABLE
  472. | PACKAGE_THERM_INT_HIGH_ENABLE))
  473. & ~PACKAGE_THERM_INT_PLN_ENABLE, h);
  474. else if (cpu_has(c, X86_FEATURE_PLN) && int_pln_enable)
  475. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  476. l | (PACKAGE_THERM_INT_LOW_ENABLE
  477. | PACKAGE_THERM_INT_HIGH_ENABLE
  478. | PACKAGE_THERM_INT_PLN_ENABLE), h);
  479. else
  480. wrmsr(MSR_IA32_PACKAGE_THERM_INTERRUPT,
  481. l | (PACKAGE_THERM_INT_LOW_ENABLE
  482. | PACKAGE_THERM_INT_HIGH_ENABLE), h);
  483. }
  484. smp_thermal_vector = intel_thermal_interrupt;
  485. rdmsr(MSR_IA32_MISC_ENABLE, l, h);
  486. wrmsr(MSR_IA32_MISC_ENABLE, l | MSR_IA32_MISC_ENABLE_TM1, h);
  487. /* Unmask the thermal vector: */
  488. l = apic_read(APIC_LVTTHMR);
  489. apic_write(APIC_LVTTHMR, l & ~APIC_LVT_MASKED);
  490. printk_once(KERN_INFO "CPU0: Thermal monitoring enabled (%s)\n",
  491. tm2 ? "TM2" : "TM1");
  492. /* enable thermal throttle processing */
  493. atomic_set(&therm_throt_en, 1);
  494. }