pci.h 4.9 KB

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  1. #ifndef __POWERNV_PCI_H
  2. #define __POWERNV_PCI_H
  3. struct pci_dn;
  4. enum pnv_phb_type {
  5. PNV_PHB_P5IOC2 = 0,
  6. PNV_PHB_IODA1 = 1,
  7. PNV_PHB_IODA2 = 2,
  8. };
  9. /* Precise PHB model for error management */
  10. enum pnv_phb_model {
  11. PNV_PHB_MODEL_UNKNOWN,
  12. PNV_PHB_MODEL_P5IOC2,
  13. PNV_PHB_MODEL_P7IOC,
  14. PNV_PHB_MODEL_PHB3,
  15. };
  16. #define PNV_PCI_DIAG_BUF_SIZE 4096
  17. #define PNV_IODA_PE_DEV (1 << 0) /* PE has single PCI device */
  18. #define PNV_IODA_PE_BUS (1 << 1) /* PE has primary PCI bus */
  19. #define PNV_IODA_PE_BUS_ALL (1 << 2) /* PE has subordinate buses */
  20. /* Data associated with a PE, including IOMMU tracking etc.. */
  21. struct pnv_phb;
  22. struct pnv_ioda_pe {
  23. unsigned long flags;
  24. struct pnv_phb *phb;
  25. /* A PE can be associated with a single device or an
  26. * entire bus (& children). In the former case, pdev
  27. * is populated, in the later case, pbus is.
  28. */
  29. struct pci_dev *pdev;
  30. struct pci_bus *pbus;
  31. /* Effective RID (device RID for a device PE and base bus
  32. * RID with devfn 0 for a bus PE)
  33. */
  34. unsigned int rid;
  35. /* PE number */
  36. unsigned int pe_number;
  37. /* "Weight" assigned to the PE for the sake of DMA resource
  38. * allocations
  39. */
  40. unsigned int dma_weight;
  41. /* "Base" iommu table, ie, 4K TCEs, 32-bit DMA */
  42. int tce32_seg;
  43. int tce32_segcount;
  44. struct iommu_table tce32_table;
  45. /* XXX TODO: Add support for additional 64-bit iommus */
  46. /* MSIs. MVE index is identical for for 32 and 64 bit MSI
  47. * and -1 if not supported. (It's actually identical to the
  48. * PE number)
  49. */
  50. int mve_number;
  51. /* Link in list of PE#s */
  52. struct list_head dma_link;
  53. struct list_head list;
  54. };
  55. /* IOC dependent EEH operations */
  56. #ifdef CONFIG_EEH
  57. struct pnv_eeh_ops {
  58. int (*post_init)(struct pci_controller *hose);
  59. int (*set_option)(struct eeh_pe *pe, int option);
  60. int (*get_state)(struct eeh_pe *pe);
  61. int (*reset)(struct eeh_pe *pe, int option);
  62. int (*get_log)(struct eeh_pe *pe, int severity,
  63. char *drv_log, unsigned long len);
  64. int (*configure_bridge)(struct eeh_pe *pe);
  65. int (*next_error)(struct eeh_pe **pe);
  66. };
  67. #define PNV_EEH_STATE_ENABLED (1 << 0) /* EEH enabled */
  68. #define PNV_EEH_STATE_REMOVED (1 << 1) /* PHB removed */
  69. #endif /* CONFIG_EEH */
  70. struct pnv_phb {
  71. struct pci_controller *hose;
  72. enum pnv_phb_type type;
  73. enum pnv_phb_model model;
  74. u64 hub_id;
  75. u64 opal_id;
  76. void __iomem *regs;
  77. int initialized;
  78. spinlock_t lock;
  79. #ifdef CONFIG_EEH
  80. struct pnv_eeh_ops *eeh_ops;
  81. int eeh_state;
  82. #endif
  83. #ifdef CONFIG_DEBUG_FS
  84. struct dentry *dbgfs;
  85. #endif
  86. #ifdef CONFIG_PCI_MSI
  87. unsigned int msi_base;
  88. unsigned int msi32_support;
  89. struct msi_bitmap msi_bmp;
  90. #endif
  91. int (*msi_setup)(struct pnv_phb *phb, struct pci_dev *dev,
  92. unsigned int hwirq, unsigned int virq,
  93. unsigned int is_64, struct msi_msg *msg);
  94. void (*dma_dev_setup)(struct pnv_phb *phb, struct pci_dev *pdev);
  95. void (*fixup_phb)(struct pci_controller *hose);
  96. u32 (*bdfn_to_pe)(struct pnv_phb *phb, struct pci_bus *bus, u32 devfn);
  97. void (*shutdown)(struct pnv_phb *phb);
  98. union {
  99. struct {
  100. struct iommu_table iommu_table;
  101. } p5ioc2;
  102. struct {
  103. /* Global bridge info */
  104. unsigned int total_pe;
  105. unsigned int m32_size;
  106. unsigned int m32_segsize;
  107. unsigned int m32_pci_base;
  108. unsigned int io_size;
  109. unsigned int io_segsize;
  110. unsigned int io_pci_base;
  111. /* PE allocation bitmap */
  112. unsigned long *pe_alloc;
  113. /* M32 & IO segment maps */
  114. unsigned int *m32_segmap;
  115. unsigned int *io_segmap;
  116. struct pnv_ioda_pe *pe_array;
  117. /* IRQ chip */
  118. int irq_chip_init;
  119. struct irq_chip irq_chip;
  120. /* Sorted list of used PE's based
  121. * on the sequence of creation
  122. */
  123. struct list_head pe_list;
  124. /* Reverse map of PEs, will have to extend if
  125. * we are to support more than 256 PEs, indexed
  126. * bus { bus, devfn }
  127. */
  128. unsigned char pe_rmap[0x10000];
  129. /* 32-bit TCE tables allocation */
  130. unsigned long tce32_count;
  131. /* Total "weight" for the sake of DMA resources
  132. * allocation
  133. */
  134. unsigned int dma_weight;
  135. unsigned int dma_pe_count;
  136. /* Sorted list of used PE's, sorted at
  137. * boot for resource allocation purposes
  138. */
  139. struct list_head pe_dma_list;
  140. } ioda;
  141. };
  142. /* PHB status structure */
  143. union {
  144. unsigned char blob[PNV_PCI_DIAG_BUF_SIZE];
  145. struct OpalIoP7IOCPhbErrorData p7ioc;
  146. } diag;
  147. };
  148. extern struct pci_ops pnv_pci_ops;
  149. #ifdef CONFIG_EEH
  150. extern struct pnv_eeh_ops ioda_eeh_ops;
  151. #endif
  152. int pnv_pci_cfg_read(struct device_node *dn,
  153. int where, int size, u32 *val);
  154. int pnv_pci_cfg_write(struct device_node *dn,
  155. int where, int size, u32 val);
  156. extern void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
  157. void *tce_mem, u64 tce_size,
  158. u64 dma_offset);
  159. extern void pnv_pci_init_p5ioc2_hub(struct device_node *np);
  160. extern void pnv_pci_init_ioda_hub(struct device_node *np);
  161. extern void pnv_pci_init_ioda2_phb(struct device_node *np);
  162. extern void pnv_pci_ioda_tce_invalidate(struct iommu_table *tbl,
  163. u64 *startp, u64 *endp);
  164. #endif /* __POWERNV_PCI_H */