pci.c 17 KB

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  1. /*
  2. * Support PCI/PCIe on PowerNV platforms
  3. *
  4. * Currently supports only P5IOC2
  5. *
  6. * Copyright 2011 Benjamin Herrenschmidt, IBM Corp.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License
  10. * as published by the Free Software Foundation; either version
  11. * 2 of the License, or (at your option) any later version.
  12. */
  13. #include <linux/kernel.h>
  14. #include <linux/pci.h>
  15. #include <linux/delay.h>
  16. #include <linux/string.h>
  17. #include <linux/init.h>
  18. #include <linux/bootmem.h>
  19. #include <linux/irq.h>
  20. #include <linux/io.h>
  21. #include <linux/msi.h>
  22. #include <linux/iommu.h>
  23. #include <asm/sections.h>
  24. #include <asm/io.h>
  25. #include <asm/prom.h>
  26. #include <asm/pci-bridge.h>
  27. #include <asm/machdep.h>
  28. #include <asm/msi_bitmap.h>
  29. #include <asm/ppc-pci.h>
  30. #include <asm/opal.h>
  31. #include <asm/iommu.h>
  32. #include <asm/tce.h>
  33. #include <asm/firmware.h>
  34. #include <asm/eeh_event.h>
  35. #include <asm/eeh.h>
  36. #include "powernv.h"
  37. #include "pci.h"
  38. /* Delay in usec */
  39. #define PCI_RESET_DELAY_US 3000000
  40. #define cfg_dbg(fmt...) do { } while(0)
  41. //#define cfg_dbg(fmt...) printk(fmt)
  42. #ifdef CONFIG_PCI_MSI
  43. static int pnv_msi_check_device(struct pci_dev* pdev, int nvec, int type)
  44. {
  45. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  46. struct pnv_phb *phb = hose->private_data;
  47. struct pci_dn *pdn = pci_get_pdn(pdev);
  48. if (pdn && pdn->force_32bit_msi && !phb->msi32_support)
  49. return -ENODEV;
  50. return (phb && phb->msi_bmp.bitmap) ? 0 : -ENODEV;
  51. }
  52. static int pnv_setup_msi_irqs(struct pci_dev *pdev, int nvec, int type)
  53. {
  54. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  55. struct pnv_phb *phb = hose->private_data;
  56. struct msi_desc *entry;
  57. struct msi_msg msg;
  58. int hwirq;
  59. unsigned int virq;
  60. int rc;
  61. if (WARN_ON(!phb))
  62. return -ENODEV;
  63. list_for_each_entry(entry, &pdev->msi_list, list) {
  64. if (!entry->msi_attrib.is_64 && !phb->msi32_support) {
  65. pr_warn("%s: Supports only 64-bit MSIs\n",
  66. pci_name(pdev));
  67. return -ENXIO;
  68. }
  69. hwirq = msi_bitmap_alloc_hwirqs(&phb->msi_bmp, 1);
  70. if (hwirq < 0) {
  71. pr_warn("%s: Failed to find a free MSI\n",
  72. pci_name(pdev));
  73. return -ENOSPC;
  74. }
  75. virq = irq_create_mapping(NULL, phb->msi_base + hwirq);
  76. if (virq == NO_IRQ) {
  77. pr_warn("%s: Failed to map MSI to linux irq\n",
  78. pci_name(pdev));
  79. msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  80. return -ENOMEM;
  81. }
  82. rc = phb->msi_setup(phb, pdev, phb->msi_base + hwirq,
  83. virq, entry->msi_attrib.is_64, &msg);
  84. if (rc) {
  85. pr_warn("%s: Failed to setup MSI\n", pci_name(pdev));
  86. irq_dispose_mapping(virq);
  87. msi_bitmap_free_hwirqs(&phb->msi_bmp, hwirq, 1);
  88. return rc;
  89. }
  90. irq_set_msi_desc(virq, entry);
  91. write_msi_msg(virq, &msg);
  92. }
  93. return 0;
  94. }
  95. static void pnv_teardown_msi_irqs(struct pci_dev *pdev)
  96. {
  97. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  98. struct pnv_phb *phb = hose->private_data;
  99. struct msi_desc *entry;
  100. if (WARN_ON(!phb))
  101. return;
  102. list_for_each_entry(entry, &pdev->msi_list, list) {
  103. if (entry->irq == NO_IRQ)
  104. continue;
  105. irq_set_msi_desc(entry->irq, NULL);
  106. msi_bitmap_free_hwirqs(&phb->msi_bmp,
  107. virq_to_hw(entry->irq) - phb->msi_base, 1);
  108. irq_dispose_mapping(entry->irq);
  109. }
  110. }
  111. #endif /* CONFIG_PCI_MSI */
  112. static void pnv_pci_dump_p7ioc_diag_data(struct pnv_phb *phb)
  113. {
  114. struct OpalIoP7IOCPhbErrorData *data = &phb->diag.p7ioc;
  115. int i;
  116. pr_info("PHB %d diagnostic data:\n", phb->hose->global_number);
  117. pr_info(" brdgCtl = 0x%08x\n", data->brdgCtl);
  118. pr_info(" portStatusReg = 0x%08x\n", data->portStatusReg);
  119. pr_info(" rootCmplxStatus = 0x%08x\n", data->rootCmplxStatus);
  120. pr_info(" busAgentStatus = 0x%08x\n", data->busAgentStatus);
  121. pr_info(" deviceStatus = 0x%08x\n", data->deviceStatus);
  122. pr_info(" slotStatus = 0x%08x\n", data->slotStatus);
  123. pr_info(" linkStatus = 0x%08x\n", data->linkStatus);
  124. pr_info(" devCmdStatus = 0x%08x\n", data->devCmdStatus);
  125. pr_info(" devSecStatus = 0x%08x\n", data->devSecStatus);
  126. pr_info(" rootErrorStatus = 0x%08x\n", data->rootErrorStatus);
  127. pr_info(" uncorrErrorStatus = 0x%08x\n", data->uncorrErrorStatus);
  128. pr_info(" corrErrorStatus = 0x%08x\n", data->corrErrorStatus);
  129. pr_info(" tlpHdr1 = 0x%08x\n", data->tlpHdr1);
  130. pr_info(" tlpHdr2 = 0x%08x\n", data->tlpHdr2);
  131. pr_info(" tlpHdr3 = 0x%08x\n", data->tlpHdr3);
  132. pr_info(" tlpHdr4 = 0x%08x\n", data->tlpHdr4);
  133. pr_info(" sourceId = 0x%08x\n", data->sourceId);
  134. pr_info(" errorClass = 0x%016llx\n", data->errorClass);
  135. pr_info(" correlator = 0x%016llx\n", data->correlator);
  136. pr_info(" p7iocPlssr = 0x%016llx\n", data->p7iocPlssr);
  137. pr_info(" p7iocCsr = 0x%016llx\n", data->p7iocCsr);
  138. pr_info(" lemFir = 0x%016llx\n", data->lemFir);
  139. pr_info(" lemErrorMask = 0x%016llx\n", data->lemErrorMask);
  140. pr_info(" lemWOF = 0x%016llx\n", data->lemWOF);
  141. pr_info(" phbErrorStatus = 0x%016llx\n", data->phbErrorStatus);
  142. pr_info(" phbFirstErrorStatus = 0x%016llx\n", data->phbFirstErrorStatus);
  143. pr_info(" phbErrorLog0 = 0x%016llx\n", data->phbErrorLog0);
  144. pr_info(" phbErrorLog1 = 0x%016llx\n", data->phbErrorLog1);
  145. pr_info(" mmioErrorStatus = 0x%016llx\n", data->mmioErrorStatus);
  146. pr_info(" mmioFirstErrorStatus = 0x%016llx\n", data->mmioFirstErrorStatus);
  147. pr_info(" mmioErrorLog0 = 0x%016llx\n", data->mmioErrorLog0);
  148. pr_info(" mmioErrorLog1 = 0x%016llx\n", data->mmioErrorLog1);
  149. pr_info(" dma0ErrorStatus = 0x%016llx\n", data->dma0ErrorStatus);
  150. pr_info(" dma0FirstErrorStatus = 0x%016llx\n", data->dma0FirstErrorStatus);
  151. pr_info(" dma0ErrorLog0 = 0x%016llx\n", data->dma0ErrorLog0);
  152. pr_info(" dma0ErrorLog1 = 0x%016llx\n", data->dma0ErrorLog1);
  153. pr_info(" dma1ErrorStatus = 0x%016llx\n", data->dma1ErrorStatus);
  154. pr_info(" dma1FirstErrorStatus = 0x%016llx\n", data->dma1FirstErrorStatus);
  155. pr_info(" dma1ErrorLog0 = 0x%016llx\n", data->dma1ErrorLog0);
  156. pr_info(" dma1ErrorLog1 = 0x%016llx\n", data->dma1ErrorLog1);
  157. for (i = 0; i < OPAL_P7IOC_NUM_PEST_REGS; i++) {
  158. if ((data->pestA[i] >> 63) == 0 &&
  159. (data->pestB[i] >> 63) == 0)
  160. continue;
  161. pr_info(" PE[%3d] PESTA = 0x%016llx\n", i, data->pestA[i]);
  162. pr_info(" PESTB = 0x%016llx\n", data->pestB[i]);
  163. }
  164. }
  165. static void pnv_pci_dump_phb_diag_data(struct pnv_phb *phb)
  166. {
  167. switch(phb->model) {
  168. case PNV_PHB_MODEL_P7IOC:
  169. pnv_pci_dump_p7ioc_diag_data(phb);
  170. break;
  171. default:
  172. pr_warning("PCI %d: Can't decode this PHB diag data\n",
  173. phb->hose->global_number);
  174. }
  175. }
  176. static void pnv_pci_handle_eeh_config(struct pnv_phb *phb, u32 pe_no)
  177. {
  178. unsigned long flags, rc;
  179. int has_diag;
  180. spin_lock_irqsave(&phb->lock, flags);
  181. rc = opal_pci_get_phb_diag_data2(phb->opal_id, phb->diag.blob,
  182. PNV_PCI_DIAG_BUF_SIZE);
  183. has_diag = (rc == OPAL_SUCCESS);
  184. rc = opal_pci_eeh_freeze_clear(phb->opal_id, pe_no,
  185. OPAL_EEH_ACTION_CLEAR_FREEZE_ALL);
  186. if (rc) {
  187. pr_warning("PCI %d: Failed to clear EEH freeze state"
  188. " for PE#%d, err %ld\n",
  189. phb->hose->global_number, pe_no, rc);
  190. /* For now, let's only display the diag buffer when we fail to clear
  191. * the EEH status. We'll do more sensible things later when we have
  192. * proper EEH support. We need to make sure we don't pollute ourselves
  193. * with the normal errors generated when probing empty slots
  194. */
  195. if (has_diag)
  196. pnv_pci_dump_phb_diag_data(phb);
  197. else
  198. pr_warning("PCI %d: No diag data available\n",
  199. phb->hose->global_number);
  200. }
  201. spin_unlock_irqrestore(&phb->lock, flags);
  202. }
  203. static void pnv_pci_config_check_eeh(struct pnv_phb *phb,
  204. struct device_node *dn)
  205. {
  206. s64 rc;
  207. u8 fstate;
  208. u16 pcierr;
  209. u32 pe_no;
  210. /*
  211. * Get the PE#. During the PCI probe stage, we might not
  212. * setup that yet. So all ER errors should be mapped to
  213. * PE#0
  214. */
  215. pe_no = PCI_DN(dn)->pe_number;
  216. if (pe_no == IODA_INVALID_PE)
  217. pe_no = 0;
  218. /* Read freeze status */
  219. rc = opal_pci_eeh_freeze_status(phb->opal_id, pe_no, &fstate, &pcierr,
  220. NULL);
  221. if (rc) {
  222. pr_warning("%s: Can't read EEH status (PE#%d) for "
  223. "%s, err %lld\n",
  224. __func__, pe_no, dn->full_name, rc);
  225. return;
  226. }
  227. cfg_dbg(" -> EEH check, bdfn=%04x PE#%d fstate=%x\n",
  228. (PCI_DN(dn)->busno << 8) | (PCI_DN(dn)->devfn),
  229. pe_no, fstate);
  230. if (fstate != 0)
  231. pnv_pci_handle_eeh_config(phb, pe_no);
  232. }
  233. int pnv_pci_cfg_read(struct device_node *dn,
  234. int where, int size, u32 *val)
  235. {
  236. struct pci_dn *pdn = PCI_DN(dn);
  237. struct pnv_phb *phb = pdn->phb->private_data;
  238. u32 bdfn = (pdn->busno << 8) | pdn->devfn;
  239. #ifdef CONFIG_EEH
  240. struct eeh_pe *phb_pe = NULL;
  241. #endif
  242. s64 rc;
  243. switch (size) {
  244. case 1: {
  245. u8 v8;
  246. rc = opal_pci_config_read_byte(phb->opal_id, bdfn, where, &v8);
  247. *val = (rc == OPAL_SUCCESS) ? v8 : 0xff;
  248. break;
  249. }
  250. case 2: {
  251. u16 v16;
  252. rc = opal_pci_config_read_half_word(phb->opal_id, bdfn, where,
  253. &v16);
  254. *val = (rc == OPAL_SUCCESS) ? v16 : 0xffff;
  255. break;
  256. }
  257. case 4: {
  258. u32 v32;
  259. rc = opal_pci_config_read_word(phb->opal_id, bdfn, where, &v32);
  260. *val = (rc == OPAL_SUCCESS) ? v32 : 0xffffffff;
  261. break;
  262. }
  263. default:
  264. return PCIBIOS_FUNC_NOT_SUPPORTED;
  265. }
  266. cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
  267. __func__, pdn->busno, pdn->devfn, where, size, *val);
  268. /*
  269. * Check if the specified PE has been put into frozen
  270. * state. On the other hand, we needn't do that while
  271. * the PHB has been put into frozen state because of
  272. * PHB-fatal errors.
  273. */
  274. #ifdef CONFIG_EEH
  275. phb_pe = eeh_phb_pe_get(pdn->phb);
  276. if (phb_pe && (phb_pe->state & EEH_PE_ISOLATED))
  277. return PCIBIOS_SUCCESSFUL;
  278. if (phb->eeh_state & PNV_EEH_STATE_ENABLED) {
  279. if (*val == EEH_IO_ERROR_VALUE(size) &&
  280. eeh_dev_check_failure(of_node_to_eeh_dev(dn)))
  281. return PCIBIOS_DEVICE_NOT_FOUND;
  282. } else {
  283. pnv_pci_config_check_eeh(phb, dn);
  284. }
  285. #else
  286. pnv_pci_config_check_eeh(phb, dn);
  287. #endif
  288. return PCIBIOS_SUCCESSFUL;
  289. }
  290. int pnv_pci_cfg_write(struct device_node *dn,
  291. int where, int size, u32 val)
  292. {
  293. struct pci_dn *pdn = PCI_DN(dn);
  294. struct pnv_phb *phb = pdn->phb->private_data;
  295. u32 bdfn = (pdn->busno << 8) | pdn->devfn;
  296. cfg_dbg("%s: bus: %x devfn: %x +%x/%x -> %08x\n",
  297. pdn->busno, pdn->devfn, where, size, val);
  298. switch (size) {
  299. case 1:
  300. opal_pci_config_write_byte(phb->opal_id, bdfn, where, val);
  301. break;
  302. case 2:
  303. opal_pci_config_write_half_word(phb->opal_id, bdfn, where, val);
  304. break;
  305. case 4:
  306. opal_pci_config_write_word(phb->opal_id, bdfn, where, val);
  307. break;
  308. default:
  309. return PCIBIOS_FUNC_NOT_SUPPORTED;
  310. }
  311. /* Check if the PHB got frozen due to an error (no response) */
  312. #ifdef CONFIG_EEH
  313. if (!(phb->eeh_state & PNV_EEH_STATE_ENABLED))
  314. pnv_pci_config_check_eeh(phb, dn);
  315. #else
  316. pnv_pci_config_check_eeh(phb, dn);
  317. #endif
  318. return PCIBIOS_SUCCESSFUL;
  319. }
  320. static int pnv_pci_read_config(struct pci_bus *bus,
  321. unsigned int devfn,
  322. int where, int size, u32 *val)
  323. {
  324. struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
  325. struct pci_dn *pdn;
  326. for (dn = busdn->child; dn; dn = dn->sibling) {
  327. pdn = PCI_DN(dn);
  328. if (pdn && pdn->devfn == devfn)
  329. return pnv_pci_cfg_read(dn, where, size, val);
  330. }
  331. *val = 0xFFFFFFFF;
  332. return PCIBIOS_DEVICE_NOT_FOUND;
  333. }
  334. static int pnv_pci_write_config(struct pci_bus *bus,
  335. unsigned int devfn,
  336. int where, int size, u32 val)
  337. {
  338. struct device_node *dn, *busdn = pci_bus_to_OF_node(bus);
  339. struct pci_dn *pdn;
  340. for (dn = busdn->child; dn; dn = dn->sibling) {
  341. pdn = PCI_DN(dn);
  342. if (pdn && pdn->devfn == devfn)
  343. return pnv_pci_cfg_write(dn, where, size, val);
  344. }
  345. return PCIBIOS_DEVICE_NOT_FOUND;
  346. }
  347. struct pci_ops pnv_pci_ops = {
  348. .read = pnv_pci_read_config,
  349. .write = pnv_pci_write_config,
  350. };
  351. static int pnv_tce_build(struct iommu_table *tbl, long index, long npages,
  352. unsigned long uaddr, enum dma_data_direction direction,
  353. struct dma_attrs *attrs)
  354. {
  355. u64 proto_tce;
  356. u64 *tcep, *tces;
  357. u64 rpn;
  358. proto_tce = TCE_PCI_READ; // Read allowed
  359. if (direction != DMA_TO_DEVICE)
  360. proto_tce |= TCE_PCI_WRITE;
  361. tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
  362. rpn = __pa(uaddr) >> TCE_SHIFT;
  363. while (npages--)
  364. *(tcep++) = proto_tce | (rpn++ << TCE_RPN_SHIFT);
  365. /* Some implementations won't cache invalid TCEs and thus may not
  366. * need that flush. We'll probably turn it_type into a bit mask
  367. * of flags if that becomes the case
  368. */
  369. if (tbl->it_type & TCE_PCI_SWINV_CREATE)
  370. pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
  371. return 0;
  372. }
  373. static void pnv_tce_free(struct iommu_table *tbl, long index, long npages)
  374. {
  375. u64 *tcep, *tces;
  376. tces = tcep = ((u64 *)tbl->it_base) + index - tbl->it_offset;
  377. while (npages--)
  378. *(tcep++) = 0;
  379. if (tbl->it_type & TCE_PCI_SWINV_FREE)
  380. pnv_pci_ioda_tce_invalidate(tbl, tces, tcep - 1);
  381. }
  382. static unsigned long pnv_tce_get(struct iommu_table *tbl, long index)
  383. {
  384. return ((u64 *)tbl->it_base)[index - tbl->it_offset];
  385. }
  386. void pnv_pci_setup_iommu_table(struct iommu_table *tbl,
  387. void *tce_mem, u64 tce_size,
  388. u64 dma_offset)
  389. {
  390. tbl->it_blocksize = 16;
  391. tbl->it_base = (unsigned long)tce_mem;
  392. tbl->it_offset = dma_offset >> IOMMU_PAGE_SHIFT;
  393. tbl->it_index = 0;
  394. tbl->it_size = tce_size >> 3;
  395. tbl->it_busno = 0;
  396. tbl->it_type = TCE_PCI;
  397. }
  398. static struct iommu_table *pnv_pci_setup_bml_iommu(struct pci_controller *hose)
  399. {
  400. struct iommu_table *tbl;
  401. const __be64 *basep, *swinvp;
  402. const __be32 *sizep;
  403. basep = of_get_property(hose->dn, "linux,tce-base", NULL);
  404. sizep = of_get_property(hose->dn, "linux,tce-size", NULL);
  405. if (basep == NULL || sizep == NULL) {
  406. pr_err("PCI: %s has missing tce entries !\n",
  407. hose->dn->full_name);
  408. return NULL;
  409. }
  410. tbl = kzalloc_node(sizeof(struct iommu_table), GFP_KERNEL, hose->node);
  411. if (WARN_ON(!tbl))
  412. return NULL;
  413. pnv_pci_setup_iommu_table(tbl, __va(be64_to_cpup(basep)),
  414. be32_to_cpup(sizep), 0);
  415. iommu_init_table(tbl, hose->node);
  416. iommu_register_group(tbl, pci_domain_nr(hose->bus), 0);
  417. /* Deal with SW invalidated TCEs when needed (BML way) */
  418. swinvp = of_get_property(hose->dn, "linux,tce-sw-invalidate-info",
  419. NULL);
  420. if (swinvp) {
  421. tbl->it_busno = swinvp[1];
  422. tbl->it_index = (unsigned long)ioremap(swinvp[0], 8);
  423. tbl->it_type = TCE_PCI_SWINV_CREATE | TCE_PCI_SWINV_FREE;
  424. }
  425. return tbl;
  426. }
  427. static void pnv_pci_dma_fallback_setup(struct pci_controller *hose,
  428. struct pci_dev *pdev)
  429. {
  430. struct device_node *np = pci_bus_to_OF_node(hose->bus);
  431. struct pci_dn *pdn;
  432. if (np == NULL)
  433. return;
  434. pdn = PCI_DN(np);
  435. if (!pdn->iommu_table)
  436. pdn->iommu_table = pnv_pci_setup_bml_iommu(hose);
  437. if (!pdn->iommu_table)
  438. return;
  439. set_iommu_table_base(&pdev->dev, pdn->iommu_table);
  440. }
  441. static void pnv_pci_dma_dev_setup(struct pci_dev *pdev)
  442. {
  443. struct pci_controller *hose = pci_bus_to_host(pdev->bus);
  444. struct pnv_phb *phb = hose->private_data;
  445. /* If we have no phb structure, try to setup a fallback based on
  446. * the device-tree (RTAS PCI for example)
  447. */
  448. if (phb && phb->dma_dev_setup)
  449. phb->dma_dev_setup(phb, pdev);
  450. else
  451. pnv_pci_dma_fallback_setup(hose, pdev);
  452. }
  453. void pnv_pci_shutdown(void)
  454. {
  455. struct pci_controller *hose;
  456. list_for_each_entry(hose, &hose_list, list_node) {
  457. struct pnv_phb *phb = hose->private_data;
  458. if (phb && phb->shutdown)
  459. phb->shutdown(phb);
  460. }
  461. }
  462. /* Fixup wrong class code in p7ioc and p8 root complex */
  463. static void pnv_p7ioc_rc_quirk(struct pci_dev *dev)
  464. {
  465. dev->class = PCI_CLASS_BRIDGE_PCI << 8;
  466. }
  467. DECLARE_PCI_FIXUP_EARLY(PCI_VENDOR_ID_IBM, 0x3b9, pnv_p7ioc_rc_quirk);
  468. static int pnv_pci_probe_mode(struct pci_bus *bus)
  469. {
  470. struct pci_controller *hose = pci_bus_to_host(bus);
  471. const __be64 *tstamp;
  472. u64 now, target;
  473. /* We hijack this as a way to ensure we have waited long
  474. * enough since the reset was lifted on the PCI bus
  475. */
  476. if (bus != hose->bus)
  477. return PCI_PROBE_NORMAL;
  478. tstamp = of_get_property(hose->dn, "reset-clear-timestamp", NULL);
  479. if (!tstamp || !*tstamp)
  480. return PCI_PROBE_NORMAL;
  481. now = mftb() / tb_ticks_per_usec;
  482. target = (be64_to_cpup(tstamp) / tb_ticks_per_usec)
  483. + PCI_RESET_DELAY_US;
  484. pr_devel("pci %04d: Reset target: 0x%llx now: 0x%llx\n",
  485. hose->global_number, target, now);
  486. if (now < target)
  487. msleep((target - now + 999) / 1000);
  488. return PCI_PROBE_NORMAL;
  489. }
  490. void __init pnv_pci_init(void)
  491. {
  492. struct device_node *np;
  493. pci_add_flags(PCI_CAN_SKIP_ISA_ALIGN);
  494. /* OPAL absent, try POPAL first then RTAS detection of PHBs */
  495. if (!firmware_has_feature(FW_FEATURE_OPAL)) {
  496. #ifdef CONFIG_PPC_POWERNV_RTAS
  497. init_pci_config_tokens();
  498. find_and_init_phbs();
  499. #endif /* CONFIG_PPC_POWERNV_RTAS */
  500. }
  501. /* OPAL is here, do our normal stuff */
  502. else {
  503. int found_ioda = 0;
  504. /* Look for IODA IO-Hubs. We don't support mixing IODA
  505. * and p5ioc2 due to the need to change some global
  506. * probing flags
  507. */
  508. for_each_compatible_node(np, NULL, "ibm,ioda-hub") {
  509. pnv_pci_init_ioda_hub(np);
  510. found_ioda = 1;
  511. }
  512. /* Look for p5ioc2 IO-Hubs */
  513. if (!found_ioda)
  514. for_each_compatible_node(np, NULL, "ibm,p5ioc2")
  515. pnv_pci_init_p5ioc2_hub(np);
  516. /* Look for ioda2 built-in PHB3's */
  517. for_each_compatible_node(np, NULL, "ibm,ioda2-phb")
  518. pnv_pci_init_ioda2_phb(np);
  519. }
  520. /* Setup the linkage between OF nodes and PHBs */
  521. pci_devs_phb_init();
  522. /* Configure IOMMU DMA hooks */
  523. ppc_md.pci_dma_dev_setup = pnv_pci_dma_dev_setup;
  524. ppc_md.tce_build = pnv_tce_build;
  525. ppc_md.tce_free = pnv_tce_free;
  526. ppc_md.tce_get = pnv_tce_get;
  527. ppc_md.pci_probe_mode = pnv_pci_probe_mode;
  528. set_pci_dma_ops(&dma_iommu_ops);
  529. /* Configure MSIs */
  530. #ifdef CONFIG_PCI_MSI
  531. ppc_md.msi_check_device = pnv_msi_check_device;
  532. ppc_md.setup_msi_irqs = pnv_setup_msi_irqs;
  533. ppc_md.teardown_msi_irqs = pnv_teardown_msi_irqs;
  534. #endif
  535. }