mpic.c 42 KB

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  1. /*
  2. * OpenPIC emulation
  3. *
  4. * Copyright (c) 2004 Jocelyn Mayer
  5. * 2011 Alexander Graf
  6. *
  7. * Permission is hereby granted, free of charge, to any person obtaining a copy
  8. * of this software and associated documentation files (the "Software"), to deal
  9. * in the Software without restriction, including without limitation the rights
  10. * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  11. * copies of the Software, and to permit persons to whom the Software is
  12. * furnished to do so, subject to the following conditions:
  13. *
  14. * The above copyright notice and this permission notice shall be included in
  15. * all copies or substantial portions of the Software.
  16. *
  17. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  18. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  19. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  20. * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  21. * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  22. * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  23. * THE SOFTWARE.
  24. */
  25. #include <linux/slab.h>
  26. #include <linux/mutex.h>
  27. #include <linux/kvm_host.h>
  28. #include <linux/errno.h>
  29. #include <linux/fs.h>
  30. #include <linux/anon_inodes.h>
  31. #include <asm/uaccess.h>
  32. #include <asm/mpic.h>
  33. #include <asm/kvm_para.h>
  34. #include <asm/kvm_host.h>
  35. #include <asm/kvm_ppc.h>
  36. #include "iodev.h"
  37. #define MAX_CPU 32
  38. #define MAX_SRC 256
  39. #define MAX_TMR 4
  40. #define MAX_IPI 4
  41. #define MAX_MSI 8
  42. #define MAX_IRQ (MAX_SRC + MAX_IPI + MAX_TMR)
  43. #define VID 0x03 /* MPIC version ID */
  44. /* OpenPIC capability flags */
  45. #define OPENPIC_FLAG_IDR_CRIT (1 << 0)
  46. #define OPENPIC_FLAG_ILR (2 << 0)
  47. /* OpenPIC address map */
  48. #define OPENPIC_REG_SIZE 0x40000
  49. #define OPENPIC_GLB_REG_START 0x0
  50. #define OPENPIC_GLB_REG_SIZE 0x10F0
  51. #define OPENPIC_TMR_REG_START 0x10F0
  52. #define OPENPIC_TMR_REG_SIZE 0x220
  53. #define OPENPIC_MSI_REG_START 0x1600
  54. #define OPENPIC_MSI_REG_SIZE 0x200
  55. #define OPENPIC_SUMMARY_REG_START 0x3800
  56. #define OPENPIC_SUMMARY_REG_SIZE 0x800
  57. #define OPENPIC_SRC_REG_START 0x10000
  58. #define OPENPIC_SRC_REG_SIZE (MAX_SRC * 0x20)
  59. #define OPENPIC_CPU_REG_START 0x20000
  60. #define OPENPIC_CPU_REG_SIZE (0x100 + ((MAX_CPU - 1) * 0x1000))
  61. struct fsl_mpic_info {
  62. int max_ext;
  63. };
  64. static struct fsl_mpic_info fsl_mpic_20 = {
  65. .max_ext = 12,
  66. };
  67. static struct fsl_mpic_info fsl_mpic_42 = {
  68. .max_ext = 12,
  69. };
  70. #define FRR_NIRQ_SHIFT 16
  71. #define FRR_NCPU_SHIFT 8
  72. #define FRR_VID_SHIFT 0
  73. #define VID_REVISION_1_2 2
  74. #define VID_REVISION_1_3 3
  75. #define VIR_GENERIC 0x00000000 /* Generic Vendor ID */
  76. #define GCR_RESET 0x80000000
  77. #define GCR_MODE_PASS 0x00000000
  78. #define GCR_MODE_MIXED 0x20000000
  79. #define GCR_MODE_PROXY 0x60000000
  80. #define TBCR_CI 0x80000000 /* count inhibit */
  81. #define TCCR_TOG 0x80000000 /* toggles when decrement to zero */
  82. #define IDR_EP_SHIFT 31
  83. #define IDR_EP_MASK (1 << IDR_EP_SHIFT)
  84. #define IDR_CI0_SHIFT 30
  85. #define IDR_CI1_SHIFT 29
  86. #define IDR_P1_SHIFT 1
  87. #define IDR_P0_SHIFT 0
  88. #define ILR_INTTGT_MASK 0x000000ff
  89. #define ILR_INTTGT_INT 0x00
  90. #define ILR_INTTGT_CINT 0x01 /* critical */
  91. #define ILR_INTTGT_MCP 0x02 /* machine check */
  92. #define NUM_OUTPUTS 3
  93. #define MSIIR_OFFSET 0x140
  94. #define MSIIR_SRS_SHIFT 29
  95. #define MSIIR_SRS_MASK (0x7 << MSIIR_SRS_SHIFT)
  96. #define MSIIR_IBS_SHIFT 24
  97. #define MSIIR_IBS_MASK (0x1f << MSIIR_IBS_SHIFT)
  98. static int get_current_cpu(void)
  99. {
  100. #if defined(CONFIG_KVM) && defined(CONFIG_BOOKE)
  101. struct kvm_vcpu *vcpu = current->thread.kvm_vcpu;
  102. return vcpu ? vcpu->arch.irq_cpu_id : -1;
  103. #else
  104. /* XXX */
  105. return -1;
  106. #endif
  107. }
  108. static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
  109. u32 val, int idx);
  110. static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
  111. u32 *ptr, int idx);
  112. enum irq_type {
  113. IRQ_TYPE_NORMAL = 0,
  114. IRQ_TYPE_FSLINT, /* FSL internal interrupt -- level only */
  115. IRQ_TYPE_FSLSPECIAL, /* FSL timer/IPI interrupt, edge, no polarity */
  116. };
  117. struct irq_queue {
  118. /* Round up to the nearest 64 IRQs so that the queue length
  119. * won't change when moving between 32 and 64 bit hosts.
  120. */
  121. unsigned long queue[BITS_TO_LONGS((MAX_IRQ + 63) & ~63)];
  122. int next;
  123. int priority;
  124. };
  125. struct irq_source {
  126. uint32_t ivpr; /* IRQ vector/priority register */
  127. uint32_t idr; /* IRQ destination register */
  128. uint32_t destmask; /* bitmap of CPU destinations */
  129. int last_cpu;
  130. int output; /* IRQ level, e.g. ILR_INTTGT_INT */
  131. int pending; /* TRUE if IRQ is pending */
  132. enum irq_type type;
  133. bool level:1; /* level-triggered */
  134. bool nomask:1; /* critical interrupts ignore mask on some FSL MPICs */
  135. };
  136. #define IVPR_MASK_SHIFT 31
  137. #define IVPR_MASK_MASK (1 << IVPR_MASK_SHIFT)
  138. #define IVPR_ACTIVITY_SHIFT 30
  139. #define IVPR_ACTIVITY_MASK (1 << IVPR_ACTIVITY_SHIFT)
  140. #define IVPR_MODE_SHIFT 29
  141. #define IVPR_MODE_MASK (1 << IVPR_MODE_SHIFT)
  142. #define IVPR_POLARITY_SHIFT 23
  143. #define IVPR_POLARITY_MASK (1 << IVPR_POLARITY_SHIFT)
  144. #define IVPR_SENSE_SHIFT 22
  145. #define IVPR_SENSE_MASK (1 << IVPR_SENSE_SHIFT)
  146. #define IVPR_PRIORITY_MASK (0xF << 16)
  147. #define IVPR_PRIORITY(_ivprr_) ((int)(((_ivprr_) & IVPR_PRIORITY_MASK) >> 16))
  148. #define IVPR_VECTOR(opp, _ivprr_) ((_ivprr_) & (opp)->vector_mask)
  149. /* IDR[EP/CI] are only for FSL MPIC prior to v4.0 */
  150. #define IDR_EP 0x80000000 /* external pin */
  151. #define IDR_CI 0x40000000 /* critical interrupt */
  152. struct irq_dest {
  153. struct kvm_vcpu *vcpu;
  154. int32_t ctpr; /* CPU current task priority */
  155. struct irq_queue raised;
  156. struct irq_queue servicing;
  157. /* Count of IRQ sources asserting on non-INT outputs */
  158. uint32_t outputs_active[NUM_OUTPUTS];
  159. };
  160. #define MAX_MMIO_REGIONS 10
  161. struct openpic {
  162. struct kvm *kvm;
  163. struct kvm_device *dev;
  164. struct kvm_io_device mmio;
  165. const struct mem_reg *mmio_regions[MAX_MMIO_REGIONS];
  166. int num_mmio_regions;
  167. gpa_t reg_base;
  168. spinlock_t lock;
  169. /* Behavior control */
  170. struct fsl_mpic_info *fsl;
  171. uint32_t model;
  172. uint32_t flags;
  173. uint32_t nb_irqs;
  174. uint32_t vid;
  175. uint32_t vir; /* Vendor identification register */
  176. uint32_t vector_mask;
  177. uint32_t tfrr_reset;
  178. uint32_t ivpr_reset;
  179. uint32_t idr_reset;
  180. uint32_t brr1;
  181. uint32_t mpic_mode_mask;
  182. /* Global registers */
  183. uint32_t frr; /* Feature reporting register */
  184. uint32_t gcr; /* Global configuration register */
  185. uint32_t pir; /* Processor initialization register */
  186. uint32_t spve; /* Spurious vector register */
  187. uint32_t tfrr; /* Timer frequency reporting register */
  188. /* Source registers */
  189. struct irq_source src[MAX_IRQ];
  190. /* Local registers per output pin */
  191. struct irq_dest dst[MAX_CPU];
  192. uint32_t nb_cpus;
  193. /* Timer registers */
  194. struct {
  195. uint32_t tccr; /* Global timer current count register */
  196. uint32_t tbcr; /* Global timer base count register */
  197. } timers[MAX_TMR];
  198. /* Shared MSI registers */
  199. struct {
  200. uint32_t msir; /* Shared Message Signaled Interrupt Register */
  201. } msi[MAX_MSI];
  202. uint32_t max_irq;
  203. uint32_t irq_ipi0;
  204. uint32_t irq_tim0;
  205. uint32_t irq_msi;
  206. };
  207. static void mpic_irq_raise(struct openpic *opp, struct irq_dest *dst,
  208. int output)
  209. {
  210. struct kvm_interrupt irq = {
  211. .irq = KVM_INTERRUPT_SET_LEVEL,
  212. };
  213. if (!dst->vcpu) {
  214. pr_debug("%s: destination cpu %d does not exist\n",
  215. __func__, (int)(dst - &opp->dst[0]));
  216. return;
  217. }
  218. pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
  219. output);
  220. if (output != ILR_INTTGT_INT) /* TODO */
  221. return;
  222. kvm_vcpu_ioctl_interrupt(dst->vcpu, &irq);
  223. }
  224. static void mpic_irq_lower(struct openpic *opp, struct irq_dest *dst,
  225. int output)
  226. {
  227. if (!dst->vcpu) {
  228. pr_debug("%s: destination cpu %d does not exist\n",
  229. __func__, (int)(dst - &opp->dst[0]));
  230. return;
  231. }
  232. pr_debug("%s: cpu %d output %d\n", __func__, dst->vcpu->arch.irq_cpu_id,
  233. output);
  234. if (output != ILR_INTTGT_INT) /* TODO */
  235. return;
  236. kvmppc_core_dequeue_external(dst->vcpu);
  237. }
  238. static inline void IRQ_setbit(struct irq_queue *q, int n_IRQ)
  239. {
  240. set_bit(n_IRQ, q->queue);
  241. }
  242. static inline void IRQ_resetbit(struct irq_queue *q, int n_IRQ)
  243. {
  244. clear_bit(n_IRQ, q->queue);
  245. }
  246. static inline int IRQ_testbit(struct irq_queue *q, int n_IRQ)
  247. {
  248. return test_bit(n_IRQ, q->queue);
  249. }
  250. static void IRQ_check(struct openpic *opp, struct irq_queue *q)
  251. {
  252. int irq = -1;
  253. int next = -1;
  254. int priority = -1;
  255. for (;;) {
  256. irq = find_next_bit(q->queue, opp->max_irq, irq + 1);
  257. if (irq == opp->max_irq)
  258. break;
  259. pr_debug("IRQ_check: irq %d set ivpr_pr=%d pr=%d\n",
  260. irq, IVPR_PRIORITY(opp->src[irq].ivpr), priority);
  261. if (IVPR_PRIORITY(opp->src[irq].ivpr) > priority) {
  262. next = irq;
  263. priority = IVPR_PRIORITY(opp->src[irq].ivpr);
  264. }
  265. }
  266. q->next = next;
  267. q->priority = priority;
  268. }
  269. static int IRQ_get_next(struct openpic *opp, struct irq_queue *q)
  270. {
  271. /* XXX: optimize */
  272. IRQ_check(opp, q);
  273. return q->next;
  274. }
  275. static void IRQ_local_pipe(struct openpic *opp, int n_CPU, int n_IRQ,
  276. bool active, bool was_active)
  277. {
  278. struct irq_dest *dst;
  279. struct irq_source *src;
  280. int priority;
  281. dst = &opp->dst[n_CPU];
  282. src = &opp->src[n_IRQ];
  283. pr_debug("%s: IRQ %d active %d was %d\n",
  284. __func__, n_IRQ, active, was_active);
  285. if (src->output != ILR_INTTGT_INT) {
  286. pr_debug("%s: output %d irq %d active %d was %d count %d\n",
  287. __func__, src->output, n_IRQ, active, was_active,
  288. dst->outputs_active[src->output]);
  289. /* On Freescale MPIC, critical interrupts ignore priority,
  290. * IACK, EOI, etc. Before MPIC v4.1 they also ignore
  291. * masking.
  292. */
  293. if (active) {
  294. if (!was_active &&
  295. dst->outputs_active[src->output]++ == 0) {
  296. pr_debug("%s: Raise OpenPIC output %d cpu %d irq %d\n",
  297. __func__, src->output, n_CPU, n_IRQ);
  298. mpic_irq_raise(opp, dst, src->output);
  299. }
  300. } else {
  301. if (was_active &&
  302. --dst->outputs_active[src->output] == 0) {
  303. pr_debug("%s: Lower OpenPIC output %d cpu %d irq %d\n",
  304. __func__, src->output, n_CPU, n_IRQ);
  305. mpic_irq_lower(opp, dst, src->output);
  306. }
  307. }
  308. return;
  309. }
  310. priority = IVPR_PRIORITY(src->ivpr);
  311. /* Even if the interrupt doesn't have enough priority,
  312. * it is still raised, in case ctpr is lowered later.
  313. */
  314. if (active)
  315. IRQ_setbit(&dst->raised, n_IRQ);
  316. else
  317. IRQ_resetbit(&dst->raised, n_IRQ);
  318. IRQ_check(opp, &dst->raised);
  319. if (active && priority <= dst->ctpr) {
  320. pr_debug("%s: IRQ %d priority %d too low for ctpr %d on CPU %d\n",
  321. __func__, n_IRQ, priority, dst->ctpr, n_CPU);
  322. active = 0;
  323. }
  324. if (active) {
  325. if (IRQ_get_next(opp, &dst->servicing) >= 0 &&
  326. priority <= dst->servicing.priority) {
  327. pr_debug("%s: IRQ %d is hidden by servicing IRQ %d on CPU %d\n",
  328. __func__, n_IRQ, dst->servicing.next, n_CPU);
  329. } else {
  330. pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d/%d\n",
  331. __func__, n_CPU, n_IRQ, dst->raised.next);
  332. mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
  333. }
  334. } else {
  335. IRQ_get_next(opp, &dst->servicing);
  336. if (dst->raised.priority > dst->ctpr &&
  337. dst->raised.priority > dst->servicing.priority) {
  338. pr_debug("%s: IRQ %d inactive, IRQ %d prio %d above %d/%d, CPU %d\n",
  339. __func__, n_IRQ, dst->raised.next,
  340. dst->raised.priority, dst->ctpr,
  341. dst->servicing.priority, n_CPU);
  342. /* IRQ line stays asserted */
  343. } else {
  344. pr_debug("%s: IRQ %d inactive, current prio %d/%d, CPU %d\n",
  345. __func__, n_IRQ, dst->ctpr,
  346. dst->servicing.priority, n_CPU);
  347. mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
  348. }
  349. }
  350. }
  351. /* update pic state because registers for n_IRQ have changed value */
  352. static void openpic_update_irq(struct openpic *opp, int n_IRQ)
  353. {
  354. struct irq_source *src;
  355. bool active, was_active;
  356. int i;
  357. src = &opp->src[n_IRQ];
  358. active = src->pending;
  359. if ((src->ivpr & IVPR_MASK_MASK) && !src->nomask) {
  360. /* Interrupt source is disabled */
  361. pr_debug("%s: IRQ %d is disabled\n", __func__, n_IRQ);
  362. active = false;
  363. }
  364. was_active = !!(src->ivpr & IVPR_ACTIVITY_MASK);
  365. /*
  366. * We don't have a similar check for already-active because
  367. * ctpr may have changed and we need to withdraw the interrupt.
  368. */
  369. if (!active && !was_active) {
  370. pr_debug("%s: IRQ %d is already inactive\n", __func__, n_IRQ);
  371. return;
  372. }
  373. if (active)
  374. src->ivpr |= IVPR_ACTIVITY_MASK;
  375. else
  376. src->ivpr &= ~IVPR_ACTIVITY_MASK;
  377. if (src->destmask == 0) {
  378. /* No target */
  379. pr_debug("%s: IRQ %d has no target\n", __func__, n_IRQ);
  380. return;
  381. }
  382. if (src->destmask == (1 << src->last_cpu)) {
  383. /* Only one CPU is allowed to receive this IRQ */
  384. IRQ_local_pipe(opp, src->last_cpu, n_IRQ, active, was_active);
  385. } else if (!(src->ivpr & IVPR_MODE_MASK)) {
  386. /* Directed delivery mode */
  387. for (i = 0; i < opp->nb_cpus; i++) {
  388. if (src->destmask & (1 << i)) {
  389. IRQ_local_pipe(opp, i, n_IRQ, active,
  390. was_active);
  391. }
  392. }
  393. } else {
  394. /* Distributed delivery mode */
  395. for (i = src->last_cpu + 1; i != src->last_cpu; i++) {
  396. if (i == opp->nb_cpus)
  397. i = 0;
  398. if (src->destmask & (1 << i)) {
  399. IRQ_local_pipe(opp, i, n_IRQ, active,
  400. was_active);
  401. src->last_cpu = i;
  402. break;
  403. }
  404. }
  405. }
  406. }
  407. static void openpic_set_irq(void *opaque, int n_IRQ, int level)
  408. {
  409. struct openpic *opp = opaque;
  410. struct irq_source *src;
  411. if (n_IRQ >= MAX_IRQ) {
  412. WARN_ONCE(1, "%s: IRQ %d out of range\n", __func__, n_IRQ);
  413. return;
  414. }
  415. src = &opp->src[n_IRQ];
  416. pr_debug("openpic: set irq %d = %d ivpr=0x%08x\n",
  417. n_IRQ, level, src->ivpr);
  418. if (src->level) {
  419. /* level-sensitive irq */
  420. src->pending = level;
  421. openpic_update_irq(opp, n_IRQ);
  422. } else {
  423. /* edge-sensitive irq */
  424. if (level) {
  425. src->pending = 1;
  426. openpic_update_irq(opp, n_IRQ);
  427. }
  428. if (src->output != ILR_INTTGT_INT) {
  429. /* Edge-triggered interrupts shouldn't be used
  430. * with non-INT delivery, but just in case,
  431. * try to make it do something sane rather than
  432. * cause an interrupt storm. This is close to
  433. * what you'd probably see happen in real hardware.
  434. */
  435. src->pending = 0;
  436. openpic_update_irq(opp, n_IRQ);
  437. }
  438. }
  439. }
  440. static void openpic_reset(struct openpic *opp)
  441. {
  442. int i;
  443. opp->gcr = GCR_RESET;
  444. /* Initialise controller registers */
  445. opp->frr = ((opp->nb_irqs - 1) << FRR_NIRQ_SHIFT) |
  446. (opp->vid << FRR_VID_SHIFT);
  447. opp->pir = 0;
  448. opp->spve = -1 & opp->vector_mask;
  449. opp->tfrr = opp->tfrr_reset;
  450. /* Initialise IRQ sources */
  451. for (i = 0; i < opp->max_irq; i++) {
  452. opp->src[i].ivpr = opp->ivpr_reset;
  453. opp->src[i].idr = opp->idr_reset;
  454. switch (opp->src[i].type) {
  455. case IRQ_TYPE_NORMAL:
  456. opp->src[i].level =
  457. !!(opp->ivpr_reset & IVPR_SENSE_MASK);
  458. break;
  459. case IRQ_TYPE_FSLINT:
  460. opp->src[i].ivpr |= IVPR_POLARITY_MASK;
  461. break;
  462. case IRQ_TYPE_FSLSPECIAL:
  463. break;
  464. }
  465. }
  466. /* Initialise IRQ destinations */
  467. for (i = 0; i < MAX_CPU; i++) {
  468. opp->dst[i].ctpr = 15;
  469. memset(&opp->dst[i].raised, 0, sizeof(struct irq_queue));
  470. opp->dst[i].raised.next = -1;
  471. memset(&opp->dst[i].servicing, 0, sizeof(struct irq_queue));
  472. opp->dst[i].servicing.next = -1;
  473. }
  474. /* Initialise timers */
  475. for (i = 0; i < MAX_TMR; i++) {
  476. opp->timers[i].tccr = 0;
  477. opp->timers[i].tbcr = TBCR_CI;
  478. }
  479. /* Go out of RESET state */
  480. opp->gcr = 0;
  481. }
  482. static inline uint32_t read_IRQreg_idr(struct openpic *opp, int n_IRQ)
  483. {
  484. return opp->src[n_IRQ].idr;
  485. }
  486. static inline uint32_t read_IRQreg_ilr(struct openpic *opp, int n_IRQ)
  487. {
  488. if (opp->flags & OPENPIC_FLAG_ILR)
  489. return opp->src[n_IRQ].output;
  490. return 0xffffffff;
  491. }
  492. static inline uint32_t read_IRQreg_ivpr(struct openpic *opp, int n_IRQ)
  493. {
  494. return opp->src[n_IRQ].ivpr;
  495. }
  496. static inline void write_IRQreg_idr(struct openpic *opp, int n_IRQ,
  497. uint32_t val)
  498. {
  499. struct irq_source *src = &opp->src[n_IRQ];
  500. uint32_t normal_mask = (1UL << opp->nb_cpus) - 1;
  501. uint32_t crit_mask = 0;
  502. uint32_t mask = normal_mask;
  503. int crit_shift = IDR_EP_SHIFT - opp->nb_cpus;
  504. int i;
  505. if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
  506. crit_mask = mask << crit_shift;
  507. mask |= crit_mask | IDR_EP;
  508. }
  509. src->idr = val & mask;
  510. pr_debug("Set IDR %d to 0x%08x\n", n_IRQ, src->idr);
  511. if (opp->flags & OPENPIC_FLAG_IDR_CRIT) {
  512. if (src->idr & crit_mask) {
  513. if (src->idr & normal_mask) {
  514. pr_debug("%s: IRQ configured for multiple output types, using critical\n",
  515. __func__);
  516. }
  517. src->output = ILR_INTTGT_CINT;
  518. src->nomask = true;
  519. src->destmask = 0;
  520. for (i = 0; i < opp->nb_cpus; i++) {
  521. int n_ci = IDR_CI0_SHIFT - i;
  522. if (src->idr & (1UL << n_ci))
  523. src->destmask |= 1UL << i;
  524. }
  525. } else {
  526. src->output = ILR_INTTGT_INT;
  527. src->nomask = false;
  528. src->destmask = src->idr & normal_mask;
  529. }
  530. } else {
  531. src->destmask = src->idr;
  532. }
  533. }
  534. static inline void write_IRQreg_ilr(struct openpic *opp, int n_IRQ,
  535. uint32_t val)
  536. {
  537. if (opp->flags & OPENPIC_FLAG_ILR) {
  538. struct irq_source *src = &opp->src[n_IRQ];
  539. src->output = val & ILR_INTTGT_MASK;
  540. pr_debug("Set ILR %d to 0x%08x, output %d\n", n_IRQ, src->idr,
  541. src->output);
  542. /* TODO: on MPIC v4.0 only, set nomask for non-INT */
  543. }
  544. }
  545. static inline void write_IRQreg_ivpr(struct openpic *opp, int n_IRQ,
  546. uint32_t val)
  547. {
  548. uint32_t mask;
  549. /* NOTE when implementing newer FSL MPIC models: starting with v4.0,
  550. * the polarity bit is read-only on internal interrupts.
  551. */
  552. mask = IVPR_MASK_MASK | IVPR_PRIORITY_MASK | IVPR_SENSE_MASK |
  553. IVPR_POLARITY_MASK | opp->vector_mask;
  554. /* ACTIVITY bit is read-only */
  555. opp->src[n_IRQ].ivpr =
  556. (opp->src[n_IRQ].ivpr & IVPR_ACTIVITY_MASK) | (val & mask);
  557. /* For FSL internal interrupts, The sense bit is reserved and zero,
  558. * and the interrupt is always level-triggered. Timers and IPIs
  559. * have no sense or polarity bits, and are edge-triggered.
  560. */
  561. switch (opp->src[n_IRQ].type) {
  562. case IRQ_TYPE_NORMAL:
  563. opp->src[n_IRQ].level =
  564. !!(opp->src[n_IRQ].ivpr & IVPR_SENSE_MASK);
  565. break;
  566. case IRQ_TYPE_FSLINT:
  567. opp->src[n_IRQ].ivpr &= ~IVPR_SENSE_MASK;
  568. break;
  569. case IRQ_TYPE_FSLSPECIAL:
  570. opp->src[n_IRQ].ivpr &= ~(IVPR_POLARITY_MASK | IVPR_SENSE_MASK);
  571. break;
  572. }
  573. openpic_update_irq(opp, n_IRQ);
  574. pr_debug("Set IVPR %d to 0x%08x -> 0x%08x\n", n_IRQ, val,
  575. opp->src[n_IRQ].ivpr);
  576. }
  577. static void openpic_gcr_write(struct openpic *opp, uint64_t val)
  578. {
  579. if (val & GCR_RESET) {
  580. openpic_reset(opp);
  581. return;
  582. }
  583. opp->gcr &= ~opp->mpic_mode_mask;
  584. opp->gcr |= val & opp->mpic_mode_mask;
  585. }
  586. static int openpic_gbl_write(void *opaque, gpa_t addr, u32 val)
  587. {
  588. struct openpic *opp = opaque;
  589. int err = 0;
  590. pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
  591. if (addr & 0xF)
  592. return 0;
  593. switch (addr) {
  594. case 0x00: /* Block Revision Register1 (BRR1) is Readonly */
  595. break;
  596. case 0x40:
  597. case 0x50:
  598. case 0x60:
  599. case 0x70:
  600. case 0x80:
  601. case 0x90:
  602. case 0xA0:
  603. case 0xB0:
  604. err = openpic_cpu_write_internal(opp, addr, val,
  605. get_current_cpu());
  606. break;
  607. case 0x1000: /* FRR */
  608. break;
  609. case 0x1020: /* GCR */
  610. openpic_gcr_write(opp, val);
  611. break;
  612. case 0x1080: /* VIR */
  613. break;
  614. case 0x1090: /* PIR */
  615. /*
  616. * This register is used to reset a CPU core --
  617. * let userspace handle it.
  618. */
  619. err = -ENXIO;
  620. break;
  621. case 0x10A0: /* IPI_IVPR */
  622. case 0x10B0:
  623. case 0x10C0:
  624. case 0x10D0: {
  625. int idx;
  626. idx = (addr - 0x10A0) >> 4;
  627. write_IRQreg_ivpr(opp, opp->irq_ipi0 + idx, val);
  628. break;
  629. }
  630. case 0x10E0: /* SPVE */
  631. opp->spve = val & opp->vector_mask;
  632. break;
  633. default:
  634. break;
  635. }
  636. return err;
  637. }
  638. static int openpic_gbl_read(void *opaque, gpa_t addr, u32 *ptr)
  639. {
  640. struct openpic *opp = opaque;
  641. u32 retval;
  642. int err = 0;
  643. pr_debug("%s: addr %#llx\n", __func__, addr);
  644. retval = 0xFFFFFFFF;
  645. if (addr & 0xF)
  646. goto out;
  647. switch (addr) {
  648. case 0x1000: /* FRR */
  649. retval = opp->frr;
  650. retval |= (opp->nb_cpus - 1) << FRR_NCPU_SHIFT;
  651. break;
  652. case 0x1020: /* GCR */
  653. retval = opp->gcr;
  654. break;
  655. case 0x1080: /* VIR */
  656. retval = opp->vir;
  657. break;
  658. case 0x1090: /* PIR */
  659. retval = 0x00000000;
  660. break;
  661. case 0x00: /* Block Revision Register1 (BRR1) */
  662. retval = opp->brr1;
  663. break;
  664. case 0x40:
  665. case 0x50:
  666. case 0x60:
  667. case 0x70:
  668. case 0x80:
  669. case 0x90:
  670. case 0xA0:
  671. case 0xB0:
  672. err = openpic_cpu_read_internal(opp, addr,
  673. &retval, get_current_cpu());
  674. break;
  675. case 0x10A0: /* IPI_IVPR */
  676. case 0x10B0:
  677. case 0x10C0:
  678. case 0x10D0:
  679. {
  680. int idx;
  681. idx = (addr - 0x10A0) >> 4;
  682. retval = read_IRQreg_ivpr(opp, opp->irq_ipi0 + idx);
  683. }
  684. break;
  685. case 0x10E0: /* SPVE */
  686. retval = opp->spve;
  687. break;
  688. default:
  689. break;
  690. }
  691. out:
  692. pr_debug("%s: => 0x%08x\n", __func__, retval);
  693. *ptr = retval;
  694. return err;
  695. }
  696. static int openpic_tmr_write(void *opaque, gpa_t addr, u32 val)
  697. {
  698. struct openpic *opp = opaque;
  699. int idx;
  700. addr += 0x10f0;
  701. pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
  702. if (addr & 0xF)
  703. return 0;
  704. if (addr == 0x10f0) {
  705. /* TFRR */
  706. opp->tfrr = val;
  707. return 0;
  708. }
  709. idx = (addr >> 6) & 0x3;
  710. addr = addr & 0x30;
  711. switch (addr & 0x30) {
  712. case 0x00: /* TCCR */
  713. break;
  714. case 0x10: /* TBCR */
  715. if ((opp->timers[idx].tccr & TCCR_TOG) != 0 &&
  716. (val & TBCR_CI) == 0 &&
  717. (opp->timers[idx].tbcr & TBCR_CI) != 0)
  718. opp->timers[idx].tccr &= ~TCCR_TOG;
  719. opp->timers[idx].tbcr = val;
  720. break;
  721. case 0x20: /* TVPR */
  722. write_IRQreg_ivpr(opp, opp->irq_tim0 + idx, val);
  723. break;
  724. case 0x30: /* TDR */
  725. write_IRQreg_idr(opp, opp->irq_tim0 + idx, val);
  726. break;
  727. }
  728. return 0;
  729. }
  730. static int openpic_tmr_read(void *opaque, gpa_t addr, u32 *ptr)
  731. {
  732. struct openpic *opp = opaque;
  733. uint32_t retval = -1;
  734. int idx;
  735. pr_debug("%s: addr %#llx\n", __func__, addr);
  736. if (addr & 0xF)
  737. goto out;
  738. idx = (addr >> 6) & 0x3;
  739. if (addr == 0x0) {
  740. /* TFRR */
  741. retval = opp->tfrr;
  742. goto out;
  743. }
  744. switch (addr & 0x30) {
  745. case 0x00: /* TCCR */
  746. retval = opp->timers[idx].tccr;
  747. break;
  748. case 0x10: /* TBCR */
  749. retval = opp->timers[idx].tbcr;
  750. break;
  751. case 0x20: /* TIPV */
  752. retval = read_IRQreg_ivpr(opp, opp->irq_tim0 + idx);
  753. break;
  754. case 0x30: /* TIDE (TIDR) */
  755. retval = read_IRQreg_idr(opp, opp->irq_tim0 + idx);
  756. break;
  757. }
  758. out:
  759. pr_debug("%s: => 0x%08x\n", __func__, retval);
  760. *ptr = retval;
  761. return 0;
  762. }
  763. static int openpic_src_write(void *opaque, gpa_t addr, u32 val)
  764. {
  765. struct openpic *opp = opaque;
  766. int idx;
  767. pr_debug("%s: addr %#llx <= %08x\n", __func__, addr, val);
  768. addr = addr & 0xffff;
  769. idx = addr >> 5;
  770. switch (addr & 0x1f) {
  771. case 0x00:
  772. write_IRQreg_ivpr(opp, idx, val);
  773. break;
  774. case 0x10:
  775. write_IRQreg_idr(opp, idx, val);
  776. break;
  777. case 0x18:
  778. write_IRQreg_ilr(opp, idx, val);
  779. break;
  780. }
  781. return 0;
  782. }
  783. static int openpic_src_read(void *opaque, gpa_t addr, u32 *ptr)
  784. {
  785. struct openpic *opp = opaque;
  786. uint32_t retval;
  787. int idx;
  788. pr_debug("%s: addr %#llx\n", __func__, addr);
  789. retval = 0xFFFFFFFF;
  790. addr = addr & 0xffff;
  791. idx = addr >> 5;
  792. switch (addr & 0x1f) {
  793. case 0x00:
  794. retval = read_IRQreg_ivpr(opp, idx);
  795. break;
  796. case 0x10:
  797. retval = read_IRQreg_idr(opp, idx);
  798. break;
  799. case 0x18:
  800. retval = read_IRQreg_ilr(opp, idx);
  801. break;
  802. }
  803. pr_debug("%s: => 0x%08x\n", __func__, retval);
  804. *ptr = retval;
  805. return 0;
  806. }
  807. static int openpic_msi_write(void *opaque, gpa_t addr, u32 val)
  808. {
  809. struct openpic *opp = opaque;
  810. int idx = opp->irq_msi;
  811. int srs, ibs;
  812. pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
  813. if (addr & 0xF)
  814. return 0;
  815. switch (addr) {
  816. case MSIIR_OFFSET:
  817. srs = val >> MSIIR_SRS_SHIFT;
  818. idx += srs;
  819. ibs = (val & MSIIR_IBS_MASK) >> MSIIR_IBS_SHIFT;
  820. opp->msi[srs].msir |= 1 << ibs;
  821. openpic_set_irq(opp, idx, 1);
  822. break;
  823. default:
  824. /* most registers are read-only, thus ignored */
  825. break;
  826. }
  827. return 0;
  828. }
  829. static int openpic_msi_read(void *opaque, gpa_t addr, u32 *ptr)
  830. {
  831. struct openpic *opp = opaque;
  832. uint32_t r = 0;
  833. int i, srs;
  834. pr_debug("%s: addr %#llx\n", __func__, addr);
  835. if (addr & 0xF)
  836. return -ENXIO;
  837. srs = addr >> 4;
  838. switch (addr) {
  839. case 0x00:
  840. case 0x10:
  841. case 0x20:
  842. case 0x30:
  843. case 0x40:
  844. case 0x50:
  845. case 0x60:
  846. case 0x70: /* MSIRs */
  847. r = opp->msi[srs].msir;
  848. /* Clear on read */
  849. opp->msi[srs].msir = 0;
  850. openpic_set_irq(opp, opp->irq_msi + srs, 0);
  851. break;
  852. case 0x120: /* MSISR */
  853. for (i = 0; i < MAX_MSI; i++)
  854. r |= (opp->msi[i].msir ? 1 : 0) << i;
  855. break;
  856. }
  857. pr_debug("%s: => 0x%08x\n", __func__, r);
  858. *ptr = r;
  859. return 0;
  860. }
  861. static int openpic_summary_read(void *opaque, gpa_t addr, u32 *ptr)
  862. {
  863. uint32_t r = 0;
  864. pr_debug("%s: addr %#llx\n", __func__, addr);
  865. /* TODO: EISR/EIMR */
  866. *ptr = r;
  867. return 0;
  868. }
  869. static int openpic_summary_write(void *opaque, gpa_t addr, u32 val)
  870. {
  871. pr_debug("%s: addr %#llx <= 0x%08x\n", __func__, addr, val);
  872. /* TODO: EISR/EIMR */
  873. return 0;
  874. }
  875. static int openpic_cpu_write_internal(void *opaque, gpa_t addr,
  876. u32 val, int idx)
  877. {
  878. struct openpic *opp = opaque;
  879. struct irq_source *src;
  880. struct irq_dest *dst;
  881. int s_IRQ, n_IRQ;
  882. pr_debug("%s: cpu %d addr %#llx <= 0x%08x\n", __func__, idx,
  883. addr, val);
  884. if (idx < 0)
  885. return 0;
  886. if (addr & 0xF)
  887. return 0;
  888. dst = &opp->dst[idx];
  889. addr &= 0xFF0;
  890. switch (addr) {
  891. case 0x40: /* IPIDR */
  892. case 0x50:
  893. case 0x60:
  894. case 0x70:
  895. idx = (addr - 0x40) >> 4;
  896. /* we use IDE as mask which CPUs to deliver the IPI to still. */
  897. opp->src[opp->irq_ipi0 + idx].destmask |= val;
  898. openpic_set_irq(opp, opp->irq_ipi0 + idx, 1);
  899. openpic_set_irq(opp, opp->irq_ipi0 + idx, 0);
  900. break;
  901. case 0x80: /* CTPR */
  902. dst->ctpr = val & 0x0000000F;
  903. pr_debug("%s: set CPU %d ctpr to %d, raised %d servicing %d\n",
  904. __func__, idx, dst->ctpr, dst->raised.priority,
  905. dst->servicing.priority);
  906. if (dst->raised.priority <= dst->ctpr) {
  907. pr_debug("%s: Lower OpenPIC INT output cpu %d due to ctpr\n",
  908. __func__, idx);
  909. mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
  910. } else if (dst->raised.priority > dst->servicing.priority) {
  911. pr_debug("%s: Raise OpenPIC INT output cpu %d irq %d\n",
  912. __func__, idx, dst->raised.next);
  913. mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
  914. }
  915. break;
  916. case 0x90: /* WHOAMI */
  917. /* Read-only register */
  918. break;
  919. case 0xA0: /* IACK */
  920. /* Read-only register */
  921. break;
  922. case 0xB0: { /* EOI */
  923. int notify_eoi;
  924. pr_debug("EOI\n");
  925. s_IRQ = IRQ_get_next(opp, &dst->servicing);
  926. if (s_IRQ < 0) {
  927. pr_debug("%s: EOI with no interrupt in service\n",
  928. __func__);
  929. break;
  930. }
  931. IRQ_resetbit(&dst->servicing, s_IRQ);
  932. /* Notify listeners that the IRQ is over */
  933. notify_eoi = s_IRQ;
  934. /* Set up next servicing IRQ */
  935. s_IRQ = IRQ_get_next(opp, &dst->servicing);
  936. /* Check queued interrupts. */
  937. n_IRQ = IRQ_get_next(opp, &dst->raised);
  938. src = &opp->src[n_IRQ];
  939. if (n_IRQ != -1 &&
  940. (s_IRQ == -1 ||
  941. IVPR_PRIORITY(src->ivpr) > dst->servicing.priority)) {
  942. pr_debug("Raise OpenPIC INT output cpu %d irq %d\n",
  943. idx, n_IRQ);
  944. mpic_irq_raise(opp, dst, ILR_INTTGT_INT);
  945. }
  946. spin_unlock(&opp->lock);
  947. kvm_notify_acked_irq(opp->kvm, 0, notify_eoi);
  948. spin_lock(&opp->lock);
  949. break;
  950. }
  951. default:
  952. break;
  953. }
  954. return 0;
  955. }
  956. static int openpic_cpu_write(void *opaque, gpa_t addr, u32 val)
  957. {
  958. struct openpic *opp = opaque;
  959. return openpic_cpu_write_internal(opp, addr, val,
  960. (addr & 0x1f000) >> 12);
  961. }
  962. static uint32_t openpic_iack(struct openpic *opp, struct irq_dest *dst,
  963. int cpu)
  964. {
  965. struct irq_source *src;
  966. int retval, irq;
  967. pr_debug("Lower OpenPIC INT output\n");
  968. mpic_irq_lower(opp, dst, ILR_INTTGT_INT);
  969. irq = IRQ_get_next(opp, &dst->raised);
  970. pr_debug("IACK: irq=%d\n", irq);
  971. if (irq == -1)
  972. /* No more interrupt pending */
  973. return opp->spve;
  974. src = &opp->src[irq];
  975. if (!(src->ivpr & IVPR_ACTIVITY_MASK) ||
  976. !(IVPR_PRIORITY(src->ivpr) > dst->ctpr)) {
  977. pr_err("%s: bad raised IRQ %d ctpr %d ivpr 0x%08x\n",
  978. __func__, irq, dst->ctpr, src->ivpr);
  979. openpic_update_irq(opp, irq);
  980. retval = opp->spve;
  981. } else {
  982. /* IRQ enter servicing state */
  983. IRQ_setbit(&dst->servicing, irq);
  984. retval = IVPR_VECTOR(opp, src->ivpr);
  985. }
  986. if (!src->level) {
  987. /* edge-sensitive IRQ */
  988. src->ivpr &= ~IVPR_ACTIVITY_MASK;
  989. src->pending = 0;
  990. IRQ_resetbit(&dst->raised, irq);
  991. }
  992. if ((irq >= opp->irq_ipi0) && (irq < (opp->irq_ipi0 + MAX_IPI))) {
  993. src->destmask &= ~(1 << cpu);
  994. if (src->destmask && !src->level) {
  995. /* trigger on CPUs that didn't know about it yet */
  996. openpic_set_irq(opp, irq, 1);
  997. openpic_set_irq(opp, irq, 0);
  998. /* if all CPUs knew about it, set active bit again */
  999. src->ivpr |= IVPR_ACTIVITY_MASK;
  1000. }
  1001. }
  1002. return retval;
  1003. }
  1004. void kvmppc_mpic_set_epr(struct kvm_vcpu *vcpu)
  1005. {
  1006. struct openpic *opp = vcpu->arch.mpic;
  1007. int cpu = vcpu->arch.irq_cpu_id;
  1008. unsigned long flags;
  1009. spin_lock_irqsave(&opp->lock, flags);
  1010. if ((opp->gcr & opp->mpic_mode_mask) == GCR_MODE_PROXY)
  1011. kvmppc_set_epr(vcpu, openpic_iack(opp, &opp->dst[cpu], cpu));
  1012. spin_unlock_irqrestore(&opp->lock, flags);
  1013. }
  1014. static int openpic_cpu_read_internal(void *opaque, gpa_t addr,
  1015. u32 *ptr, int idx)
  1016. {
  1017. struct openpic *opp = opaque;
  1018. struct irq_dest *dst;
  1019. uint32_t retval;
  1020. pr_debug("%s: cpu %d addr %#llx\n", __func__, idx, addr);
  1021. retval = 0xFFFFFFFF;
  1022. if (idx < 0)
  1023. goto out;
  1024. if (addr & 0xF)
  1025. goto out;
  1026. dst = &opp->dst[idx];
  1027. addr &= 0xFF0;
  1028. switch (addr) {
  1029. case 0x80: /* CTPR */
  1030. retval = dst->ctpr;
  1031. break;
  1032. case 0x90: /* WHOAMI */
  1033. retval = idx;
  1034. break;
  1035. case 0xA0: /* IACK */
  1036. retval = openpic_iack(opp, dst, idx);
  1037. break;
  1038. case 0xB0: /* EOI */
  1039. retval = 0;
  1040. break;
  1041. default:
  1042. break;
  1043. }
  1044. pr_debug("%s: => 0x%08x\n", __func__, retval);
  1045. out:
  1046. *ptr = retval;
  1047. return 0;
  1048. }
  1049. static int openpic_cpu_read(void *opaque, gpa_t addr, u32 *ptr)
  1050. {
  1051. struct openpic *opp = opaque;
  1052. return openpic_cpu_read_internal(opp, addr, ptr,
  1053. (addr & 0x1f000) >> 12);
  1054. }
  1055. struct mem_reg {
  1056. int (*read)(void *opaque, gpa_t addr, u32 *ptr);
  1057. int (*write)(void *opaque, gpa_t addr, u32 val);
  1058. gpa_t start_addr;
  1059. int size;
  1060. };
  1061. static const struct mem_reg openpic_gbl_mmio = {
  1062. .write = openpic_gbl_write,
  1063. .read = openpic_gbl_read,
  1064. .start_addr = OPENPIC_GLB_REG_START,
  1065. .size = OPENPIC_GLB_REG_SIZE,
  1066. };
  1067. static const struct mem_reg openpic_tmr_mmio = {
  1068. .write = openpic_tmr_write,
  1069. .read = openpic_tmr_read,
  1070. .start_addr = OPENPIC_TMR_REG_START,
  1071. .size = OPENPIC_TMR_REG_SIZE,
  1072. };
  1073. static const struct mem_reg openpic_cpu_mmio = {
  1074. .write = openpic_cpu_write,
  1075. .read = openpic_cpu_read,
  1076. .start_addr = OPENPIC_CPU_REG_START,
  1077. .size = OPENPIC_CPU_REG_SIZE,
  1078. };
  1079. static const struct mem_reg openpic_src_mmio = {
  1080. .write = openpic_src_write,
  1081. .read = openpic_src_read,
  1082. .start_addr = OPENPIC_SRC_REG_START,
  1083. .size = OPENPIC_SRC_REG_SIZE,
  1084. };
  1085. static const struct mem_reg openpic_msi_mmio = {
  1086. .read = openpic_msi_read,
  1087. .write = openpic_msi_write,
  1088. .start_addr = OPENPIC_MSI_REG_START,
  1089. .size = OPENPIC_MSI_REG_SIZE,
  1090. };
  1091. static const struct mem_reg openpic_summary_mmio = {
  1092. .read = openpic_summary_read,
  1093. .write = openpic_summary_write,
  1094. .start_addr = OPENPIC_SUMMARY_REG_START,
  1095. .size = OPENPIC_SUMMARY_REG_SIZE,
  1096. };
  1097. static void add_mmio_region(struct openpic *opp, const struct mem_reg *mr)
  1098. {
  1099. if (opp->num_mmio_regions >= MAX_MMIO_REGIONS) {
  1100. WARN(1, "kvm mpic: too many mmio regions\n");
  1101. return;
  1102. }
  1103. opp->mmio_regions[opp->num_mmio_regions++] = mr;
  1104. }
  1105. static void fsl_common_init(struct openpic *opp)
  1106. {
  1107. int i;
  1108. int virq = MAX_SRC;
  1109. add_mmio_region(opp, &openpic_msi_mmio);
  1110. add_mmio_region(opp, &openpic_summary_mmio);
  1111. opp->vid = VID_REVISION_1_2;
  1112. opp->vir = VIR_GENERIC;
  1113. opp->vector_mask = 0xFFFF;
  1114. opp->tfrr_reset = 0;
  1115. opp->ivpr_reset = IVPR_MASK_MASK;
  1116. opp->idr_reset = 1 << 0;
  1117. opp->max_irq = MAX_IRQ;
  1118. opp->irq_ipi0 = virq;
  1119. virq += MAX_IPI;
  1120. opp->irq_tim0 = virq;
  1121. virq += MAX_TMR;
  1122. BUG_ON(virq > MAX_IRQ);
  1123. opp->irq_msi = 224;
  1124. for (i = 0; i < opp->fsl->max_ext; i++)
  1125. opp->src[i].level = false;
  1126. /* Internal interrupts, including message and MSI */
  1127. for (i = 16; i < MAX_SRC; i++) {
  1128. opp->src[i].type = IRQ_TYPE_FSLINT;
  1129. opp->src[i].level = true;
  1130. }
  1131. /* timers and IPIs */
  1132. for (i = MAX_SRC; i < virq; i++) {
  1133. opp->src[i].type = IRQ_TYPE_FSLSPECIAL;
  1134. opp->src[i].level = false;
  1135. }
  1136. }
  1137. static int kvm_mpic_read_internal(struct openpic *opp, gpa_t addr, u32 *ptr)
  1138. {
  1139. int i;
  1140. for (i = 0; i < opp->num_mmio_regions; i++) {
  1141. const struct mem_reg *mr = opp->mmio_regions[i];
  1142. if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
  1143. continue;
  1144. return mr->read(opp, addr - mr->start_addr, ptr);
  1145. }
  1146. return -ENXIO;
  1147. }
  1148. static int kvm_mpic_write_internal(struct openpic *opp, gpa_t addr, u32 val)
  1149. {
  1150. int i;
  1151. for (i = 0; i < opp->num_mmio_regions; i++) {
  1152. const struct mem_reg *mr = opp->mmio_regions[i];
  1153. if (mr->start_addr > addr || addr >= mr->start_addr + mr->size)
  1154. continue;
  1155. return mr->write(opp, addr - mr->start_addr, val);
  1156. }
  1157. return -ENXIO;
  1158. }
  1159. static int kvm_mpic_read(struct kvm_io_device *this, gpa_t addr,
  1160. int len, void *ptr)
  1161. {
  1162. struct openpic *opp = container_of(this, struct openpic, mmio);
  1163. int ret;
  1164. union {
  1165. u32 val;
  1166. u8 bytes[4];
  1167. } u;
  1168. if (addr & (len - 1)) {
  1169. pr_debug("%s: bad alignment %llx/%d\n",
  1170. __func__, addr, len);
  1171. return -EINVAL;
  1172. }
  1173. spin_lock_irq(&opp->lock);
  1174. ret = kvm_mpic_read_internal(opp, addr - opp->reg_base, &u.val);
  1175. spin_unlock_irq(&opp->lock);
  1176. /*
  1177. * Technically only 32-bit accesses are allowed, but be nice to
  1178. * people dumping registers a byte at a time -- it works in real
  1179. * hardware (reads only, not writes).
  1180. */
  1181. if (len == 4) {
  1182. *(u32 *)ptr = u.val;
  1183. pr_debug("%s: addr %llx ret %d len 4 val %x\n",
  1184. __func__, addr, ret, u.val);
  1185. } else if (len == 1) {
  1186. *(u8 *)ptr = u.bytes[addr & 3];
  1187. pr_debug("%s: addr %llx ret %d len 1 val %x\n",
  1188. __func__, addr, ret, u.bytes[addr & 3]);
  1189. } else {
  1190. pr_debug("%s: bad length %d\n", __func__, len);
  1191. return -EINVAL;
  1192. }
  1193. return ret;
  1194. }
  1195. static int kvm_mpic_write(struct kvm_io_device *this, gpa_t addr,
  1196. int len, const void *ptr)
  1197. {
  1198. struct openpic *opp = container_of(this, struct openpic, mmio);
  1199. int ret;
  1200. if (len != 4) {
  1201. pr_debug("%s: bad length %d\n", __func__, len);
  1202. return -EOPNOTSUPP;
  1203. }
  1204. if (addr & 3) {
  1205. pr_debug("%s: bad alignment %llx/%d\n", __func__, addr, len);
  1206. return -EOPNOTSUPP;
  1207. }
  1208. spin_lock_irq(&opp->lock);
  1209. ret = kvm_mpic_write_internal(opp, addr - opp->reg_base,
  1210. *(const u32 *)ptr);
  1211. spin_unlock_irq(&opp->lock);
  1212. pr_debug("%s: addr %llx ret %d val %x\n",
  1213. __func__, addr, ret, *(const u32 *)ptr);
  1214. return ret;
  1215. }
  1216. static const struct kvm_io_device_ops mpic_mmio_ops = {
  1217. .read = kvm_mpic_read,
  1218. .write = kvm_mpic_write,
  1219. };
  1220. static void map_mmio(struct openpic *opp)
  1221. {
  1222. kvm_iodevice_init(&opp->mmio, &mpic_mmio_ops);
  1223. kvm_io_bus_register_dev(opp->kvm, KVM_MMIO_BUS,
  1224. opp->reg_base, OPENPIC_REG_SIZE,
  1225. &opp->mmio);
  1226. }
  1227. static void unmap_mmio(struct openpic *opp)
  1228. {
  1229. kvm_io_bus_unregister_dev(opp->kvm, KVM_MMIO_BUS, &opp->mmio);
  1230. }
  1231. static int set_base_addr(struct openpic *opp, struct kvm_device_attr *attr)
  1232. {
  1233. u64 base;
  1234. if (copy_from_user(&base, (u64 __user *)(long)attr->addr, sizeof(u64)))
  1235. return -EFAULT;
  1236. if (base & 0x3ffff) {
  1237. pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx not aligned\n",
  1238. __func__, base);
  1239. return -EINVAL;
  1240. }
  1241. if (base == opp->reg_base)
  1242. return 0;
  1243. mutex_lock(&opp->kvm->slots_lock);
  1244. unmap_mmio(opp);
  1245. opp->reg_base = base;
  1246. pr_debug("kvm mpic %s: KVM_DEV_MPIC_BASE_ADDR %08llx\n",
  1247. __func__, base);
  1248. if (base == 0)
  1249. goto out;
  1250. map_mmio(opp);
  1251. out:
  1252. mutex_unlock(&opp->kvm->slots_lock);
  1253. return 0;
  1254. }
  1255. #define ATTR_SET 0
  1256. #define ATTR_GET 1
  1257. static int access_reg(struct openpic *opp, gpa_t addr, u32 *val, int type)
  1258. {
  1259. int ret;
  1260. if (addr & 3)
  1261. return -ENXIO;
  1262. spin_lock_irq(&opp->lock);
  1263. if (type == ATTR_SET)
  1264. ret = kvm_mpic_write_internal(opp, addr, *val);
  1265. else
  1266. ret = kvm_mpic_read_internal(opp, addr, val);
  1267. spin_unlock_irq(&opp->lock);
  1268. pr_debug("%s: type %d addr %llx val %x\n", __func__, type, addr, *val);
  1269. return ret;
  1270. }
  1271. static int mpic_set_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
  1272. {
  1273. struct openpic *opp = dev->private;
  1274. u32 attr32;
  1275. switch (attr->group) {
  1276. case KVM_DEV_MPIC_GRP_MISC:
  1277. switch (attr->attr) {
  1278. case KVM_DEV_MPIC_BASE_ADDR:
  1279. return set_base_addr(opp, attr);
  1280. }
  1281. break;
  1282. case KVM_DEV_MPIC_GRP_REGISTER:
  1283. if (get_user(attr32, (u32 __user *)(long)attr->addr))
  1284. return -EFAULT;
  1285. return access_reg(opp, attr->attr, &attr32, ATTR_SET);
  1286. case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
  1287. if (attr->attr > MAX_SRC)
  1288. return -EINVAL;
  1289. if (get_user(attr32, (u32 __user *)(long)attr->addr))
  1290. return -EFAULT;
  1291. if (attr32 != 0 && attr32 != 1)
  1292. return -EINVAL;
  1293. spin_lock_irq(&opp->lock);
  1294. openpic_set_irq(opp, attr->attr, attr32);
  1295. spin_unlock_irq(&opp->lock);
  1296. return 0;
  1297. }
  1298. return -ENXIO;
  1299. }
  1300. static int mpic_get_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
  1301. {
  1302. struct openpic *opp = dev->private;
  1303. u64 attr64;
  1304. u32 attr32;
  1305. int ret;
  1306. switch (attr->group) {
  1307. case KVM_DEV_MPIC_GRP_MISC:
  1308. switch (attr->attr) {
  1309. case KVM_DEV_MPIC_BASE_ADDR:
  1310. mutex_lock(&opp->kvm->slots_lock);
  1311. attr64 = opp->reg_base;
  1312. mutex_unlock(&opp->kvm->slots_lock);
  1313. if (copy_to_user((u64 __user *)(long)attr->addr,
  1314. &attr64, sizeof(u64)))
  1315. return -EFAULT;
  1316. return 0;
  1317. }
  1318. break;
  1319. case KVM_DEV_MPIC_GRP_REGISTER:
  1320. ret = access_reg(opp, attr->attr, &attr32, ATTR_GET);
  1321. if (ret)
  1322. return ret;
  1323. if (put_user(attr32, (u32 __user *)(long)attr->addr))
  1324. return -EFAULT;
  1325. return 0;
  1326. case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
  1327. if (attr->attr > MAX_SRC)
  1328. return -EINVAL;
  1329. spin_lock_irq(&opp->lock);
  1330. attr32 = opp->src[attr->attr].pending;
  1331. spin_unlock_irq(&opp->lock);
  1332. if (put_user(attr32, (u32 __user *)(long)attr->addr))
  1333. return -EFAULT;
  1334. return 0;
  1335. }
  1336. return -ENXIO;
  1337. }
  1338. static int mpic_has_attr(struct kvm_device *dev, struct kvm_device_attr *attr)
  1339. {
  1340. switch (attr->group) {
  1341. case KVM_DEV_MPIC_GRP_MISC:
  1342. switch (attr->attr) {
  1343. case KVM_DEV_MPIC_BASE_ADDR:
  1344. return 0;
  1345. }
  1346. break;
  1347. case KVM_DEV_MPIC_GRP_REGISTER:
  1348. return 0;
  1349. case KVM_DEV_MPIC_GRP_IRQ_ACTIVE:
  1350. if (attr->attr > MAX_SRC)
  1351. break;
  1352. return 0;
  1353. }
  1354. return -ENXIO;
  1355. }
  1356. static void mpic_destroy(struct kvm_device *dev)
  1357. {
  1358. struct openpic *opp = dev->private;
  1359. dev->kvm->arch.mpic = NULL;
  1360. kfree(opp);
  1361. }
  1362. static int mpic_set_default_irq_routing(struct openpic *opp)
  1363. {
  1364. struct kvm_irq_routing_entry *routing;
  1365. /* Create a nop default map, so that dereferencing it still works */
  1366. routing = kzalloc((sizeof(*routing)), GFP_KERNEL);
  1367. if (!routing)
  1368. return -ENOMEM;
  1369. kvm_set_irq_routing(opp->kvm, routing, 0, 0);
  1370. kfree(routing);
  1371. return 0;
  1372. }
  1373. static int mpic_create(struct kvm_device *dev, u32 type)
  1374. {
  1375. struct openpic *opp;
  1376. int ret;
  1377. /* We only support one MPIC at a time for now */
  1378. if (dev->kvm->arch.mpic)
  1379. return -EINVAL;
  1380. opp = kzalloc(sizeof(struct openpic), GFP_KERNEL);
  1381. if (!opp)
  1382. return -ENOMEM;
  1383. dev->private = opp;
  1384. opp->kvm = dev->kvm;
  1385. opp->dev = dev;
  1386. opp->model = type;
  1387. spin_lock_init(&opp->lock);
  1388. add_mmio_region(opp, &openpic_gbl_mmio);
  1389. add_mmio_region(opp, &openpic_tmr_mmio);
  1390. add_mmio_region(opp, &openpic_src_mmio);
  1391. add_mmio_region(opp, &openpic_cpu_mmio);
  1392. switch (opp->model) {
  1393. case KVM_DEV_TYPE_FSL_MPIC_20:
  1394. opp->fsl = &fsl_mpic_20;
  1395. opp->brr1 = 0x00400200;
  1396. opp->flags |= OPENPIC_FLAG_IDR_CRIT;
  1397. opp->nb_irqs = 80;
  1398. opp->mpic_mode_mask = GCR_MODE_MIXED;
  1399. fsl_common_init(opp);
  1400. break;
  1401. case KVM_DEV_TYPE_FSL_MPIC_42:
  1402. opp->fsl = &fsl_mpic_42;
  1403. opp->brr1 = 0x00400402;
  1404. opp->flags |= OPENPIC_FLAG_ILR;
  1405. opp->nb_irqs = 196;
  1406. opp->mpic_mode_mask = GCR_MODE_PROXY;
  1407. fsl_common_init(opp);
  1408. break;
  1409. default:
  1410. ret = -ENODEV;
  1411. goto err;
  1412. }
  1413. ret = mpic_set_default_irq_routing(opp);
  1414. if (ret)
  1415. goto err;
  1416. openpic_reset(opp);
  1417. smp_wmb();
  1418. dev->kvm->arch.mpic = opp;
  1419. return 0;
  1420. err:
  1421. kfree(opp);
  1422. return ret;
  1423. }
  1424. struct kvm_device_ops kvm_mpic_ops = {
  1425. .name = "kvm-mpic",
  1426. .create = mpic_create,
  1427. .destroy = mpic_destroy,
  1428. .set_attr = mpic_set_attr,
  1429. .get_attr = mpic_get_attr,
  1430. .has_attr = mpic_has_attr,
  1431. };
  1432. int kvmppc_mpic_connect_vcpu(struct kvm_device *dev, struct kvm_vcpu *vcpu,
  1433. u32 cpu)
  1434. {
  1435. struct openpic *opp = dev->private;
  1436. int ret = 0;
  1437. if (dev->ops != &kvm_mpic_ops)
  1438. return -EPERM;
  1439. if (opp->kvm != vcpu->kvm)
  1440. return -EPERM;
  1441. if (cpu < 0 || cpu >= MAX_CPU)
  1442. return -EPERM;
  1443. spin_lock_irq(&opp->lock);
  1444. if (opp->dst[cpu].vcpu) {
  1445. ret = -EEXIST;
  1446. goto out;
  1447. }
  1448. if (vcpu->arch.irq_type) {
  1449. ret = -EBUSY;
  1450. goto out;
  1451. }
  1452. opp->dst[cpu].vcpu = vcpu;
  1453. opp->nb_cpus = max(opp->nb_cpus, cpu + 1);
  1454. vcpu->arch.mpic = opp;
  1455. vcpu->arch.irq_cpu_id = cpu;
  1456. vcpu->arch.irq_type = KVMPPC_IRQ_MPIC;
  1457. /* This might need to be changed if GCR gets extended */
  1458. if (opp->mpic_mode_mask == GCR_MODE_PROXY)
  1459. vcpu->arch.epr_flags |= KVMPPC_EPR_KERNEL;
  1460. out:
  1461. spin_unlock_irq(&opp->lock);
  1462. return ret;
  1463. }
  1464. /*
  1465. * This should only happen immediately before the mpic is destroyed,
  1466. * so we shouldn't need to worry about anything still trying to
  1467. * access the vcpu pointer.
  1468. */
  1469. void kvmppc_mpic_disconnect_vcpu(struct openpic *opp, struct kvm_vcpu *vcpu)
  1470. {
  1471. BUG_ON(!opp->dst[vcpu->arch.irq_cpu_id].vcpu);
  1472. opp->dst[vcpu->arch.irq_cpu_id].vcpu = NULL;
  1473. }
  1474. /*
  1475. * Return value:
  1476. * < 0 Interrupt was ignored (masked or not delivered for other reasons)
  1477. * = 0 Interrupt was coalesced (previous irq is still pending)
  1478. * > 0 Number of CPUs interrupt was delivered to
  1479. */
  1480. static int mpic_set_irq(struct kvm_kernel_irq_routing_entry *e,
  1481. struct kvm *kvm, int irq_source_id, int level,
  1482. bool line_status)
  1483. {
  1484. u32 irq = e->irqchip.pin;
  1485. struct openpic *opp = kvm->arch.mpic;
  1486. unsigned long flags;
  1487. spin_lock_irqsave(&opp->lock, flags);
  1488. openpic_set_irq(opp, irq, level);
  1489. spin_unlock_irqrestore(&opp->lock, flags);
  1490. /* All code paths we care about don't check for the return value */
  1491. return 0;
  1492. }
  1493. int kvm_set_msi(struct kvm_kernel_irq_routing_entry *e,
  1494. struct kvm *kvm, int irq_source_id, int level, bool line_status)
  1495. {
  1496. struct openpic *opp = kvm->arch.mpic;
  1497. unsigned long flags;
  1498. spin_lock_irqsave(&opp->lock, flags);
  1499. /*
  1500. * XXX We ignore the target address for now, as we only support
  1501. * a single MSI bank.
  1502. */
  1503. openpic_msi_write(kvm->arch.mpic, MSIIR_OFFSET, e->msi.data);
  1504. spin_unlock_irqrestore(&opp->lock, flags);
  1505. /* All code paths we care about don't check for the return value */
  1506. return 0;
  1507. }
  1508. int kvm_set_routing_entry(struct kvm_irq_routing_table *rt,
  1509. struct kvm_kernel_irq_routing_entry *e,
  1510. const struct kvm_irq_routing_entry *ue)
  1511. {
  1512. int r = -EINVAL;
  1513. switch (ue->type) {
  1514. case KVM_IRQ_ROUTING_IRQCHIP:
  1515. e->set = mpic_set_irq;
  1516. e->irqchip.irqchip = ue->u.irqchip.irqchip;
  1517. e->irqchip.pin = ue->u.irqchip.pin;
  1518. if (e->irqchip.pin >= KVM_IRQCHIP_NUM_PINS)
  1519. goto out;
  1520. rt->chip[ue->u.irqchip.irqchip][e->irqchip.pin] = ue->gsi;
  1521. break;
  1522. case KVM_IRQ_ROUTING_MSI:
  1523. e->set = kvm_set_msi;
  1524. e->msi.address_lo = ue->u.msi.address_lo;
  1525. e->msi.address_hi = ue->u.msi.address_hi;
  1526. e->msi.data = ue->u.msi.data;
  1527. break;
  1528. default:
  1529. goto out;
  1530. }
  1531. r = 0;
  1532. out:
  1533. return r;
  1534. }