eeh_cache.c 8.6 KB

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  1. /*
  2. * PCI address cache; allows the lookup of PCI devices based on I/O address
  3. *
  4. * Copyright IBM Corporation 2004
  5. * Copyright Linas Vepstas <linas@austin.ibm.com> 2004
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/list.h>
  22. #include <linux/pci.h>
  23. #include <linux/rbtree.h>
  24. #include <linux/slab.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/atomic.h>
  27. #include <asm/pci-bridge.h>
  28. #include <asm/ppc-pci.h>
  29. /**
  30. * The pci address cache subsystem. This subsystem places
  31. * PCI device address resources into a red-black tree, sorted
  32. * according to the address range, so that given only an i/o
  33. * address, the corresponding PCI device can be **quickly**
  34. * found. It is safe to perform an address lookup in an interrupt
  35. * context; this ability is an important feature.
  36. *
  37. * Currently, the only customer of this code is the EEH subsystem;
  38. * thus, this code has been somewhat tailored to suit EEH better.
  39. * In particular, the cache does *not* hold the addresses of devices
  40. * for which EEH is not enabled.
  41. *
  42. * (Implementation Note: The RB tree seems to be better/faster
  43. * than any hash algo I could think of for this problem, even
  44. * with the penalty of slow pointer chases for d-cache misses).
  45. */
  46. struct pci_io_addr_range {
  47. struct rb_node rb_node;
  48. unsigned long addr_lo;
  49. unsigned long addr_hi;
  50. struct eeh_dev *edev;
  51. struct pci_dev *pcidev;
  52. unsigned int flags;
  53. };
  54. static struct pci_io_addr_cache {
  55. struct rb_root rb_root;
  56. spinlock_t piar_lock;
  57. } pci_io_addr_cache_root;
  58. static inline struct eeh_dev *__eeh_addr_cache_get_device(unsigned long addr)
  59. {
  60. struct rb_node *n = pci_io_addr_cache_root.rb_root.rb_node;
  61. while (n) {
  62. struct pci_io_addr_range *piar;
  63. piar = rb_entry(n, struct pci_io_addr_range, rb_node);
  64. if (addr < piar->addr_lo)
  65. n = n->rb_left;
  66. else if (addr > piar->addr_hi)
  67. n = n->rb_right;
  68. else
  69. return piar->edev;
  70. }
  71. return NULL;
  72. }
  73. /**
  74. * eeh_addr_cache_get_dev - Get device, given only address
  75. * @addr: mmio (PIO) phys address or i/o port number
  76. *
  77. * Given an mmio phys address, or a port number, find a pci device
  78. * that implements this address. Be sure to pci_dev_put the device
  79. * when finished. I/O port numbers are assumed to be offset
  80. * from zero (that is, they do *not* have pci_io_addr added in).
  81. * It is safe to call this function within an interrupt.
  82. */
  83. struct eeh_dev *eeh_addr_cache_get_dev(unsigned long addr)
  84. {
  85. struct eeh_dev *edev;
  86. unsigned long flags;
  87. spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
  88. edev = __eeh_addr_cache_get_device(addr);
  89. spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
  90. return edev;
  91. }
  92. #ifdef DEBUG
  93. /*
  94. * Handy-dandy debug print routine, does nothing more
  95. * than print out the contents of our addr cache.
  96. */
  97. static void eeh_addr_cache_print(struct pci_io_addr_cache *cache)
  98. {
  99. struct rb_node *n;
  100. int cnt = 0;
  101. n = rb_first(&cache->rb_root);
  102. while (n) {
  103. struct pci_io_addr_range *piar;
  104. piar = rb_entry(n, struct pci_io_addr_range, rb_node);
  105. pr_debug("PCI: %s addr range %d [%lx-%lx]: %s\n",
  106. (piar->flags & IORESOURCE_IO) ? "i/o" : "mem", cnt,
  107. piar->addr_lo, piar->addr_hi, pci_name(piar->pcidev));
  108. cnt++;
  109. n = rb_next(n);
  110. }
  111. }
  112. #endif
  113. /* Insert address range into the rb tree. */
  114. static struct pci_io_addr_range *
  115. eeh_addr_cache_insert(struct pci_dev *dev, unsigned long alo,
  116. unsigned long ahi, unsigned int flags)
  117. {
  118. struct rb_node **p = &pci_io_addr_cache_root.rb_root.rb_node;
  119. struct rb_node *parent = NULL;
  120. struct pci_io_addr_range *piar;
  121. /* Walk tree, find a place to insert into tree */
  122. while (*p) {
  123. parent = *p;
  124. piar = rb_entry(parent, struct pci_io_addr_range, rb_node);
  125. if (ahi < piar->addr_lo) {
  126. p = &parent->rb_left;
  127. } else if (alo > piar->addr_hi) {
  128. p = &parent->rb_right;
  129. } else {
  130. if (dev != piar->pcidev ||
  131. alo != piar->addr_lo || ahi != piar->addr_hi) {
  132. pr_warning("PIAR: overlapping address range\n");
  133. }
  134. return piar;
  135. }
  136. }
  137. piar = kzalloc(sizeof(struct pci_io_addr_range), GFP_ATOMIC);
  138. if (!piar)
  139. return NULL;
  140. piar->addr_lo = alo;
  141. piar->addr_hi = ahi;
  142. piar->edev = pci_dev_to_eeh_dev(dev);
  143. piar->pcidev = dev;
  144. piar->flags = flags;
  145. #ifdef DEBUG
  146. pr_debug("PIAR: insert range=[%lx:%lx] dev=%s\n",
  147. alo, ahi, pci_name(dev));
  148. #endif
  149. rb_link_node(&piar->rb_node, parent, p);
  150. rb_insert_color(&piar->rb_node, &pci_io_addr_cache_root.rb_root);
  151. return piar;
  152. }
  153. static void __eeh_addr_cache_insert_dev(struct pci_dev *dev)
  154. {
  155. struct device_node *dn;
  156. struct eeh_dev *edev;
  157. int i;
  158. dn = pci_device_to_OF_node(dev);
  159. if (!dn) {
  160. pr_warning("PCI: no pci dn found for dev=%s\n", pci_name(dev));
  161. return;
  162. }
  163. edev = of_node_to_eeh_dev(dn);
  164. if (!edev) {
  165. pr_warning("PCI: no EEH dev found for dn=%s\n",
  166. dn->full_name);
  167. return;
  168. }
  169. /* Skip any devices for which EEH is not enabled. */
  170. if (!eeh_probe_mode_dev() && !edev->pe) {
  171. #ifdef DEBUG
  172. pr_info("PCI: skip building address cache for=%s - %s\n",
  173. pci_name(dev), dn->full_name);
  174. #endif
  175. return;
  176. }
  177. /* Walk resources on this device, poke them into the tree */
  178. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  179. unsigned long start = pci_resource_start(dev,i);
  180. unsigned long end = pci_resource_end(dev,i);
  181. unsigned int flags = pci_resource_flags(dev,i);
  182. /* We are interested only bus addresses, not dma or other stuff */
  183. if (0 == (flags & (IORESOURCE_IO | IORESOURCE_MEM)))
  184. continue;
  185. if (start == 0 || ~start == 0 || end == 0 || ~end == 0)
  186. continue;
  187. eeh_addr_cache_insert(dev, start, end, flags);
  188. }
  189. }
  190. /**
  191. * eeh_addr_cache_insert_dev - Add a device to the address cache
  192. * @dev: PCI device whose I/O addresses we are interested in.
  193. *
  194. * In order to support the fast lookup of devices based on addresses,
  195. * we maintain a cache of devices that can be quickly searched.
  196. * This routine adds a device to that cache.
  197. */
  198. void eeh_addr_cache_insert_dev(struct pci_dev *dev)
  199. {
  200. unsigned long flags;
  201. /* Ignore PCI bridges */
  202. if ((dev->class >> 16) == PCI_BASE_CLASS_BRIDGE)
  203. return;
  204. spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
  205. __eeh_addr_cache_insert_dev(dev);
  206. spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
  207. }
  208. static inline void __eeh_addr_cache_rmv_dev(struct pci_dev *dev)
  209. {
  210. struct rb_node *n;
  211. restart:
  212. n = rb_first(&pci_io_addr_cache_root.rb_root);
  213. while (n) {
  214. struct pci_io_addr_range *piar;
  215. piar = rb_entry(n, struct pci_io_addr_range, rb_node);
  216. if (piar->pcidev == dev) {
  217. rb_erase(n, &pci_io_addr_cache_root.rb_root);
  218. kfree(piar);
  219. goto restart;
  220. }
  221. n = rb_next(n);
  222. }
  223. }
  224. /**
  225. * eeh_addr_cache_rmv_dev - remove pci device from addr cache
  226. * @dev: device to remove
  227. *
  228. * Remove a device from the addr-cache tree.
  229. * This is potentially expensive, since it will walk
  230. * the tree multiple times (once per resource).
  231. * But so what; device removal doesn't need to be that fast.
  232. */
  233. void eeh_addr_cache_rmv_dev(struct pci_dev *dev)
  234. {
  235. unsigned long flags;
  236. spin_lock_irqsave(&pci_io_addr_cache_root.piar_lock, flags);
  237. __eeh_addr_cache_rmv_dev(dev);
  238. spin_unlock_irqrestore(&pci_io_addr_cache_root.piar_lock, flags);
  239. }
  240. /**
  241. * eeh_addr_cache_build - Build a cache of I/O addresses
  242. *
  243. * Build a cache of pci i/o addresses. This cache will be used to
  244. * find the pci device that corresponds to a given address.
  245. * This routine scans all pci busses to build the cache.
  246. * Must be run late in boot process, after the pci controllers
  247. * have been scanned for devices (after all device resources are known).
  248. */
  249. void eeh_addr_cache_build(void)
  250. {
  251. struct device_node *dn;
  252. struct eeh_dev *edev;
  253. struct pci_dev *dev = NULL;
  254. spin_lock_init(&pci_io_addr_cache_root.piar_lock);
  255. for_each_pci_dev(dev) {
  256. dn = pci_device_to_OF_node(dev);
  257. if (!dn)
  258. continue;
  259. edev = of_node_to_eeh_dev(dn);
  260. if (!edev)
  261. continue;
  262. dev->dev.archdata.edev = edev;
  263. edev->pdev = dev;
  264. eeh_addr_cache_insert_dev(dev);
  265. eeh_sysfs_add_device(dev);
  266. }
  267. #ifdef DEBUG
  268. /* Verify tree built up above, echo back the list of addrs. */
  269. eeh_addr_cache_print(&pci_io_addr_cache_root);
  270. #endif
  271. }