cpu_setup_power.S 3.1 KB

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  1. /*
  2. * This file contains low level CPU setup functions.
  3. * Copyright (C) 2003 Benjamin Herrenschmidt (benh@kernel.crashing.org)
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License
  7. * as published by the Free Software Foundation; either version
  8. * 2 of the License, or (at your option) any later version.
  9. *
  10. */
  11. #include <asm/processor.h>
  12. #include <asm/page.h>
  13. #include <asm/cputable.h>
  14. #include <asm/ppc_asm.h>
  15. #include <asm/asm-offsets.h>
  16. #include <asm/cache.h>
  17. /* Entry: r3 = crap, r4 = ptr to cputable entry
  18. *
  19. * Note that we can be called twice for pseudo-PVRs
  20. */
  21. _GLOBAL(__setup_cpu_power7)
  22. mflr r11
  23. bl __init_hvmode_206
  24. mtlr r11
  25. beqlr
  26. li r0,0
  27. mtspr SPRN_LPID,r0
  28. mfspr r3,SPRN_LPCR
  29. bl __init_LPCR
  30. bl __init_TLB
  31. mtlr r11
  32. blr
  33. _GLOBAL(__restore_cpu_power7)
  34. mflr r11
  35. mfmsr r3
  36. rldicl. r0,r3,4,63
  37. beqlr
  38. li r0,0
  39. mtspr SPRN_LPID,r0
  40. mfspr r3,SPRN_LPCR
  41. bl __init_LPCR
  42. bl __init_TLB
  43. mtlr r11
  44. blr
  45. _GLOBAL(__setup_cpu_power8)
  46. mflr r11
  47. bl __init_FSCR
  48. bl __init_PMU
  49. bl __init_hvmode_206
  50. mtlr r11
  51. beqlr
  52. li r0,0
  53. mtspr SPRN_LPID,r0
  54. mfspr r3,SPRN_LPCR
  55. oris r3, r3, LPCR_AIL_3@h
  56. bl __init_LPCR
  57. bl __init_HFSCR
  58. bl __init_TLB
  59. bl __init_PMU_HV
  60. mtlr r11
  61. blr
  62. _GLOBAL(__restore_cpu_power8)
  63. mflr r11
  64. bl __init_FSCR
  65. bl __init_PMU
  66. mfmsr r3
  67. rldicl. r0,r3,4,63
  68. mtlr r11
  69. beqlr
  70. li r0,0
  71. mtspr SPRN_LPID,r0
  72. mfspr r3,SPRN_LPCR
  73. oris r3, r3, LPCR_AIL_3@h
  74. bl __init_LPCR
  75. bl __init_HFSCR
  76. bl __init_TLB
  77. bl __init_PMU_HV
  78. mtlr r11
  79. blr
  80. __init_hvmode_206:
  81. /* Disable CPU_FTR_HVMODE and exit if MSR:HV is not set */
  82. mfmsr r3
  83. rldicl. r0,r3,4,63
  84. bnelr
  85. ld r5,CPU_SPEC_FEATURES(r4)
  86. LOAD_REG_IMMEDIATE(r6,CPU_FTR_HVMODE)
  87. xor r5,r5,r6
  88. std r5,CPU_SPEC_FEATURES(r4)
  89. blr
  90. __init_LPCR:
  91. /* Setup a sane LPCR:
  92. * Called with initial LPCR in R3
  93. *
  94. * LPES = 0b01 (HSRR0/1 used for 0x500)
  95. * PECE = 0b111
  96. * DPFD = 4
  97. * HDICE = 0
  98. * VC = 0b100 (VPM0=1, VPM1=0, ISL=0)
  99. * VRMASD = 0b10000 (L=1, LP=00)
  100. *
  101. * Other bits untouched for now
  102. */
  103. li r5,1
  104. rldimi r3,r5, LPCR_LPES_SH, 64-LPCR_LPES_SH-2
  105. ori r3,r3,(LPCR_PECE0|LPCR_PECE1|LPCR_PECE2)
  106. li r5,4
  107. rldimi r3,r5, LPCR_DPFD_SH, 64-LPCR_DPFD_SH-3
  108. clrrdi r3,r3,1 /* clear HDICE */
  109. li r5,4
  110. rldimi r3,r5, LPCR_VC_SH, 0
  111. li r5,0x10
  112. rldimi r3,r5, LPCR_VRMASD_SH, 64-LPCR_VRMASD_SH-5
  113. mtspr SPRN_LPCR,r3
  114. isync
  115. blr
  116. __init_FSCR:
  117. mfspr r3,SPRN_FSCR
  118. ori r3,r3,FSCR_TAR|FSCR_DSCR|FSCR_EBB
  119. mtspr SPRN_FSCR,r3
  120. blr
  121. __init_HFSCR:
  122. mfspr r3,SPRN_HFSCR
  123. ori r3,r3,HFSCR_TAR|HFSCR_TM|HFSCR_BHRB|HFSCR_PM|\
  124. HFSCR_DSCR|HFSCR_VECVSX|HFSCR_FP|HFSCR_EBB
  125. mtspr SPRN_HFSCR,r3
  126. blr
  127. __init_TLB:
  128. /*
  129. * Clear the TLB using the "IS 3" form of tlbiel instruction
  130. * (invalidate by congruence class). P7 has 128 CCs, P8 has 512
  131. * so we just always do 512
  132. */
  133. li r6,512
  134. mtctr r6
  135. li r7,0xc00 /* IS field = 0b11 */
  136. ptesync
  137. 2: tlbiel r7
  138. addi r7,r7,0x1000
  139. bdnz 2b
  140. ptesync
  141. 1: blr
  142. __init_PMU_HV:
  143. li r5,0
  144. mtspr SPRN_MMCRC,r5
  145. mtspr SPRN_MMCRH,r5
  146. blr
  147. __init_PMU:
  148. li r5,0
  149. mtspr SPRN_MMCRS,r5
  150. mtspr SPRN_MMCRA,r5
  151. mtspr SPRN_MMCR0,r5
  152. mtspr SPRN_MMCR1,r5
  153. mtspr SPRN_MMCR2,r5
  154. blr