ops-pmcmsp.c 29 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593594595596597598599600601602603604605606607608609610611612613614615616617618619620621622623624625626627628629630631632633634635636637638639640641642643644645646647648649650651652653654655656657658659660661662663664665666667668669670671672673674675676677678679680681682683684685686687688689690691692693694695696697698699700701702703704705706707708709710711712713714715716717718719720721722723724725726727728729730731732733734735736737738739740741742743744745746747748749750751752753754755756757758759760761762763764765766767768769770771772773774775776777778779780781782783784785786787788789790791792793794795796797798799800801802803804805806807808809810811812813814815816817818819820821822823824825826827828829830831832833834835836837838839840841842843844845846847848849850851852853854855856857858859860861862863864865866867868869870871872873874875876877878879880881882883884885886887888889890891892893894895896897898899900901902903904905906907908909910911912913914915916917918919920921922923924925926927928929930931932933934935936937938939940941942943944945946947948949950951952953954955956957958959960961962963964965966967968969970971972973974975976977978979980981982983984985
  1. /*
  2. * PMC-Sierra MSP board specific pci_ops
  3. *
  4. * Copyright 2001 MontaVista Software Inc.
  5. * Copyright 2005-2007 PMC-Sierra, Inc
  6. *
  7. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  8. *
  9. * Much of the code is derived from the original DDB5074 port by
  10. * Geert Uytterhoeven <geert@sonycom.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License as published by the
  14. * Free Software Foundation; either version 2 of the License, or (at your
  15. * option) any later version.
  16. *
  17. */
  18. #define PCI_COUNTERS 1
  19. #include <linux/types.h>
  20. #include <linux/pci.h>
  21. #include <linux/interrupt.h>
  22. #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
  23. #include <linux/proc_fs.h>
  24. #include <linux/seq_file.h>
  25. #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
  26. #include <linux/kernel.h>
  27. #include <linux/init.h>
  28. #include <asm/byteorder.h>
  29. #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
  30. #include <asm/mipsmtregs.h>
  31. #endif
  32. #include <msp_prom.h>
  33. #include <msp_cic_int.h>
  34. #include <msp_pci.h>
  35. #include <msp_regs.h>
  36. #include <msp_regops.h>
  37. #define PCI_ACCESS_READ 0
  38. #define PCI_ACCESS_WRITE 1
  39. #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
  40. static char proc_init;
  41. extern struct proc_dir_entry *proc_bus_pci_dir;
  42. unsigned int pci_int_count[32];
  43. static void pci_proc_init(void);
  44. /*****************************************************************************
  45. *
  46. * FUNCTION: show_msp_pci_counts
  47. * _________________________________________________________________________
  48. *
  49. * DESCRIPTION: Prints the count of how many times each PCI
  50. * interrupt has asserted. Can be invoked by the
  51. * /proc filesystem.
  52. *
  53. * INPUTS: m - synthetic file construction data
  54. * v - iterator
  55. *
  56. * RETURNS: 0 or error
  57. *
  58. ****************************************************************************/
  59. static int show_msp_pci_counts(struct seq_file *m, void *v)
  60. {
  61. int i;
  62. unsigned int intcount, total = 0;
  63. for (i = 0; i < 32; ++i) {
  64. intcount = pci_int_count[i];
  65. if (intcount != 0) {
  66. seq_printf(m, "[%d] = %u\n", i, intcount);
  67. total += intcount;
  68. }
  69. }
  70. seq_printf(m, "total = %u\n", total);
  71. return 0;
  72. }
  73. static int msp_pci_rd_cnt_open(struct inode *inode, struct file *file)
  74. {
  75. return single_open(file, show_msp_pci_counts, NULL);
  76. }
  77. static const struct file_operations msp_pci_rd_cnt_fops = {
  78. .open = msp_pci_rd_cnt_open,
  79. .read = seq_read,
  80. .llseek = seq_lseek,
  81. .release = single_release,
  82. };
  83. /*****************************************************************************
  84. *
  85. * FUNCTION: gen_pci_cfg_wr_show
  86. * _________________________________________________________________________
  87. *
  88. * DESCRIPTION: Generates a configuration write cycle for debug purposes.
  89. * The IDSEL line asserted and location and data written are
  90. * immaterial. Just want to be able to prove that a
  91. * configuration write can be correctly generated on the
  92. * PCI bus. Intent is that this function by invocable from
  93. * the /proc filesystem.
  94. *
  95. * INPUTS: m - synthetic file construction data
  96. * v - iterator
  97. *
  98. * RETURNS: 0 or error
  99. *
  100. ****************************************************************************/
  101. static int gen_pci_cfg_wr_show(struct seq_file *m, void *v)
  102. {
  103. unsigned char where = 0; /* Write to static Device/Vendor ID */
  104. unsigned char bus_num = 0; /* Bus 0 */
  105. unsigned char dev_fn = 0xF; /* Arbitrary device number */
  106. u32 wr_data = 0xFF00AA00; /* Arbitrary data */
  107. struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
  108. unsigned long value;
  109. int intr;
  110. seq_puts(m, "PMC MSP PCI: Beginning\n");
  111. if (proc_init == 0) {
  112. pci_proc_init();
  113. proc_init = ~0;
  114. }
  115. seq_puts(m, "PMC MSP PCI: Before Cfg Wr\n");
  116. /*
  117. * Generate PCI Configuration Write Cycle
  118. */
  119. /* Clear cause register bits */
  120. preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
  121. /* Setup address that is to appear on PCI bus */
  122. preg->config_addr = BPCI_CFGADDR_ENABLE |
  123. (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
  124. (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
  125. (where & 0xFC);
  126. value = cpu_to_le32(wr_data);
  127. /* Launch the PCI configuration write cycle */
  128. *PCI_CONFIG_SPACE_REG = value;
  129. /*
  130. * Check if the PCI configuration cycle (rd or wr) succeeded, by
  131. * checking the status bits for errors like master or target abort.
  132. */
  133. intr = preg->if_status;
  134. seq_puts(m, "PMC MSP PCI: After Cfg Wr\n");
  135. return 0;
  136. }
  137. static int gen_pci_cfg_wr_open(struct inode *inode, struct file *file)
  138. {
  139. return single_open(file, gen_pci_cfg_wr_show, NULL);
  140. }
  141. static const struct file_operations gen_pci_cfg_wr_fops = {
  142. .open = gen_pci_cfg_wr_open,
  143. .read = seq_read,
  144. .llseek = seq_lseek,
  145. .release = single_release,
  146. };
  147. /*****************************************************************************
  148. *
  149. * FUNCTION: pci_proc_init
  150. * _________________________________________________________________________
  151. *
  152. * DESCRIPTION: Create entries in the /proc filesystem for debug access.
  153. *
  154. * INPUTS: none
  155. *
  156. * OUTPUTS: none
  157. *
  158. * RETURNS: none
  159. *
  160. ****************************************************************************/
  161. static void pci_proc_init(void)
  162. {
  163. proc_create("pmc_msp_pci_rd_cnt", 0, NULL, &msp_pci_rd_cnt_fops);
  164. proc_create("pmc_msp_pci_cfg_wr", 0, NULL, &gen_pci_cfg_wr_fops);
  165. }
  166. #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
  167. static DEFINE_SPINLOCK(bpci_lock);
  168. /*****************************************************************************
  169. *
  170. * STRUCT: pci_io_resource
  171. * _________________________________________________________________________
  172. *
  173. * DESCRIPTION: Defines the address range that pciauto() will use to
  174. * assign to the I/O BARs of PCI devices.
  175. *
  176. * Use the start and end addresses of the MSP7120 PCI Host
  177. * Controller I/O space, in the form that they appear on the
  178. * PCI bus AFTER MSP7120 has performed address translation.
  179. *
  180. * For I/O accesses, MSP7120 ignores OATRAN and maps I/O
  181. * accesses into the bottom 0xFFF region of address space,
  182. * so that is the range to put into the pci_io_resource
  183. * struct.
  184. *
  185. * In MSP4200, the start address was 0x04 instead of the
  186. * expected 0x00. Will just assume there was a good reason
  187. * for this!
  188. *
  189. * NOTES: Linux, by default, will assign I/O space to the lowest
  190. * region of address space. Since MSP7120 and Linux,
  191. * by default, have no offset in between how they map, the
  192. * io_offset element of pci_controller struct should be set
  193. * to zero.
  194. * ELEMENTS:
  195. * name - String used for a meaningful name.
  196. *
  197. * start - Start address of MSP7120's I/O space, as MSP7120 presents
  198. * the address on the PCI bus.
  199. *
  200. * end - End address of MSP7120's I/O space, as MSP7120 presents
  201. * the address on the PCI bus.
  202. *
  203. * flags - Attributes indicating the type of resource. In this case,
  204. * indicate I/O space.
  205. *
  206. ****************************************************************************/
  207. static struct resource pci_io_resource = {
  208. .name = "pci IO space",
  209. .start = 0x04,
  210. .end = 0x0FFF,
  211. .flags = IORESOURCE_IO /* I/O space */
  212. };
  213. /*****************************************************************************
  214. *
  215. * STRUCT: pci_mem_resource
  216. * _________________________________________________________________________
  217. *
  218. * DESCRIPTION: Defines the address range that pciauto() will use to
  219. * assign to the memory BARs of PCI devices.
  220. *
  221. * The .start and .end values are dependent upon how address
  222. * translation is performed by the OATRAN regiser.
  223. *
  224. * The values to use for .start and .end are the values
  225. * in the form they appear on the PCI bus AFTER MSP7120 has
  226. * performed OATRAN address translation.
  227. *
  228. * ELEMENTS:
  229. * name - String used for a meaningful name.
  230. *
  231. * start - Start address of MSP7120's memory space, as MSP7120 presents
  232. * the address on the PCI bus.
  233. *
  234. * end - End address of MSP7120's memory space, as MSP7120 presents
  235. * the address on the PCI bus.
  236. *
  237. * flags - Attributes indicating the type of resource. In this case,
  238. * indicate memory space.
  239. *
  240. ****************************************************************************/
  241. static struct resource pci_mem_resource = {
  242. .name = "pci memory space",
  243. .start = MSP_PCI_SPACE_BASE,
  244. .end = MSP_PCI_SPACE_END,
  245. .flags = IORESOURCE_MEM /* memory space */
  246. };
  247. /*****************************************************************************
  248. *
  249. * FUNCTION: bpci_interrupt
  250. * _________________________________________________________________________
  251. *
  252. * DESCRIPTION: PCI status interrupt handler. Updates the count of how
  253. * many times each status bit has been set, then clears
  254. * the status bits. If the appropriate macros are defined,
  255. * these counts can be viewed via the /proc filesystem.
  256. *
  257. * INPUTS: irq - unused
  258. * dev_id - unused
  259. * pt_regs - unused
  260. *
  261. * OUTPUTS: none
  262. *
  263. * RETURNS: PCIBIOS_SUCCESSFUL - success
  264. *
  265. ****************************************************************************/
  266. static irqreturn_t bpci_interrupt(int irq, void *dev_id)
  267. {
  268. struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
  269. unsigned int stat = preg->if_status;
  270. #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
  271. int i;
  272. for (i = 0; i < 32; ++i) {
  273. if ((1 << i) & stat)
  274. ++pci_int_count[i];
  275. }
  276. #endif /* PROC_FS && PCI_COUNTERS */
  277. /* printk("PCI ISR: Status=%08X\n", stat); */
  278. /* write to clear all asserted interrupts */
  279. preg->if_status = stat;
  280. return IRQ_HANDLED;
  281. }
  282. /*****************************************************************************
  283. *
  284. * FUNCTION: msp_pcibios_config_access
  285. * _________________________________________________________________________
  286. *
  287. * DESCRIPTION: Performs a PCI configuration access (rd or wr), then
  288. * checks that the access succeeded by querying MSP7120's
  289. * PCI status bits.
  290. *
  291. * INPUTS:
  292. * access_type - kind of PCI configuration cycle to perform
  293. * (read or write). Legal values are
  294. * PCI_ACCESS_WRITE and PCI_ACCESS_READ.
  295. *
  296. * bus - pointer to the bus number of the device to
  297. * be targeted for the configuration cycle.
  298. * The only element of the pci_bus structure
  299. * used is bus->number. This argument determines
  300. * if the configuration access will be Type 0 or
  301. * Type 1. Since MSP7120 assumes itself to be the
  302. * PCI Host, any non-zero bus->number generates
  303. * a Type 1 access.
  304. *
  305. * devfn - this is an 8-bit field. The lower three bits
  306. * specify the function number of the device to
  307. * be targeted for the configuration cycle, with
  308. * all three-bit combinations being legal. The
  309. * upper five bits specify the device number,
  310. * with legal values being 10 to 31.
  311. *
  312. * where - address within the Configuration Header
  313. * space to access.
  314. *
  315. * data - for write accesses, contains the data to
  316. * write.
  317. *
  318. * OUTPUTS:
  319. * data - for read accesses, contains the value read.
  320. *
  321. * RETURNS: PCIBIOS_SUCCESSFUL - success
  322. * -1 - access failure
  323. *
  324. ****************************************************************************/
  325. int msp_pcibios_config_access(unsigned char access_type,
  326. struct pci_bus *bus,
  327. unsigned int devfn,
  328. unsigned char where,
  329. u32 *data)
  330. {
  331. struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
  332. unsigned char bus_num = bus->number;
  333. unsigned char dev_fn = (unsigned char)devfn;
  334. unsigned long flags;
  335. unsigned long intr;
  336. unsigned long value;
  337. static char pciirqflag;
  338. int ret;
  339. #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
  340. unsigned int vpe_status;
  341. #endif
  342. #if defined(CONFIG_PROC_FS) && defined(PCI_COUNTERS)
  343. if (proc_init == 0) {
  344. pci_proc_init();
  345. proc_init = ~0;
  346. }
  347. #endif /* CONFIG_PROC_FS && PCI_COUNTERS */
  348. /*
  349. * Just the first time this function invokes, allocate
  350. * an interrupt line for PCI host status interrupts. The
  351. * allocation assigns an interrupt handler to the interrupt.
  352. */
  353. if (pciirqflag == 0) {
  354. ret = request_irq(MSP_INT_PCI,/* Hardcoded internal MSP7120 wiring */
  355. bpci_interrupt,
  356. IRQF_SHARED,
  357. "PMC MSP PCI Host",
  358. preg);
  359. if (ret != 0)
  360. return ret;
  361. pciirqflag = ~0;
  362. }
  363. #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
  364. local_irq_save(flags);
  365. vpe_status = dvpe();
  366. #else
  367. spin_lock_irqsave(&bpci_lock, flags);
  368. #endif
  369. /*
  370. * Clear PCI cause register bits.
  371. *
  372. * In Polo, the PCI Host had a dedicated DMA called the
  373. * Block Copy (not to be confused with the general purpose Block
  374. * Copy Engine block). There appear to have been special interrupts
  375. * for this Block Copy, called Block Copy 0 Fault (BC0F) and
  376. * Block Copy 1 Fault (BC1F). MSP4200 and MSP7120 don't have this
  377. * dedicated Block Copy block, so these two interrupts are now
  378. * marked reserved. In case the Block Copy is resurrected in a
  379. * future design, maintain the code that treats these two interrupts
  380. * specially.
  381. *
  382. * Write to clear all interrupts in the PCI status register, aside
  383. * from BC0F and BC1F.
  384. */
  385. preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
  386. /* Setup address that is to appear on PCI bus */
  387. preg->config_addr = BPCI_CFGADDR_ENABLE |
  388. (bus_num << BPCI_CFGADDR_BUSNUM_SHF) |
  389. (dev_fn << BPCI_CFGADDR_FUNCTNUM_SHF) |
  390. (where & 0xFC);
  391. /* IF access is a PCI configuration write */
  392. if (access_type == PCI_ACCESS_WRITE) {
  393. value = cpu_to_le32(*data);
  394. *PCI_CONFIG_SPACE_REG = value;
  395. } else {
  396. /* ELSE access is a PCI configuration read */
  397. value = le32_to_cpu(*PCI_CONFIG_SPACE_REG);
  398. *data = value;
  399. }
  400. /*
  401. * Check if the PCI configuration cycle (rd or wr) succeeded, by
  402. * checking the status bits for errors like master or target abort.
  403. */
  404. intr = preg->if_status;
  405. /* Clear config access */
  406. preg->config_addr = 0;
  407. /* IF error occurred */
  408. if (intr & ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F)) {
  409. /* Clear status bits */
  410. preg->if_status = ~(BPCI_IFSTATUS_BC0F | BPCI_IFSTATUS_BC1F);
  411. #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
  412. evpe(vpe_status);
  413. local_irq_restore(flags);
  414. #else
  415. spin_unlock_irqrestore(&bpci_lock, flags);
  416. #endif
  417. return -1;
  418. }
  419. #if defined(CONFIG_PMC_MSP7120_GW) || defined(CONFIG_PMC_MSP7120_EVAL)
  420. evpe(vpe_status);
  421. local_irq_restore(flags);
  422. #else
  423. spin_unlock_irqrestore(&bpci_lock, flags);
  424. #endif
  425. return PCIBIOS_SUCCESSFUL;
  426. }
  427. /*****************************************************************************
  428. *
  429. * FUNCTION: msp_pcibios_read_config_byte
  430. * _________________________________________________________________________
  431. *
  432. * DESCRIPTION: Read a byte from PCI configuration address spac
  433. * Since the hardware can't address 8 bit chunks
  434. * directly, read a 32-bit chunk, then mask off extraneous
  435. * bits.
  436. *
  437. * INPUTS bus - structure containing attributes for the PCI bus
  438. * that the read is destined for.
  439. * devfn - device/function combination that the read is
  440. * destined for.
  441. * where - register within the Configuration Header space
  442. * to access.
  443. *
  444. * OUTPUTS val - read data
  445. *
  446. * RETURNS: PCIBIOS_SUCCESSFUL - success
  447. * -1 - read access failure
  448. *
  449. ****************************************************************************/
  450. static int
  451. msp_pcibios_read_config_byte(struct pci_bus *bus,
  452. unsigned int devfn,
  453. int where,
  454. u32 *val)
  455. {
  456. u32 data = 0;
  457. /*
  458. * If the config access did not complete normally (e.g., underwent
  459. * master abort) do the PCI compliant thing, which is to supply an
  460. * all ones value.
  461. */
  462. if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  463. where, &data)) {
  464. *val = 0xFFFFFFFF;
  465. return -1;
  466. }
  467. *val = (data >> ((where & 3) << 3)) & 0x0ff;
  468. return PCIBIOS_SUCCESSFUL;
  469. }
  470. /*****************************************************************************
  471. *
  472. * FUNCTION: msp_pcibios_read_config_word
  473. * _________________________________________________________________________
  474. *
  475. * DESCRIPTION: Read a word (16 bits) from PCI configuration address space.
  476. * Since the hardware can't address 16 bit chunks
  477. * directly, read a 32-bit chunk, then mask off extraneous
  478. * bits.
  479. *
  480. * INPUTS bus - structure containing attributes for the PCI bus
  481. * that the read is destined for.
  482. * devfn - device/function combination that the read is
  483. * destined for.
  484. * where - register within the Configuration Header space
  485. * to access.
  486. *
  487. * OUTPUTS val - read data
  488. *
  489. * RETURNS: PCIBIOS_SUCCESSFUL - success
  490. * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
  491. * -1 - read access failure
  492. *
  493. ****************************************************************************/
  494. static int
  495. msp_pcibios_read_config_word(struct pci_bus *bus,
  496. unsigned int devfn,
  497. int where,
  498. u32 *val)
  499. {
  500. u32 data = 0;
  501. /* if (where & 1) */ /* Commented out non-compliant code.
  502. * Should allow word access to configuration
  503. * registers, with only exception being when
  504. * the word access would wrap around into
  505. * the next dword.
  506. */
  507. if ((where & 3) == 3) {
  508. *val = 0xFFFFFFFF;
  509. return PCIBIOS_BAD_REGISTER_NUMBER;
  510. }
  511. /*
  512. * If the config access did not complete normally (e.g., underwent
  513. * master abort) do the PCI compliant thing, which is to supply an
  514. * all ones value.
  515. */
  516. if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  517. where, &data)) {
  518. *val = 0xFFFFFFFF;
  519. return -1;
  520. }
  521. *val = (data >> ((where & 3) << 3)) & 0x0ffff;
  522. return PCIBIOS_SUCCESSFUL;
  523. }
  524. /*****************************************************************************
  525. *
  526. * FUNCTION: msp_pcibios_read_config_dword
  527. * _________________________________________________________________________
  528. *
  529. * DESCRIPTION: Read a double word (32 bits) from PCI configuration
  530. * address space.
  531. *
  532. * INPUTS bus - structure containing attributes for the PCI bus
  533. * that the read is destined for.
  534. * devfn - device/function combination that the read is
  535. * destined for.
  536. * where - register within the Configuration Header space
  537. * to access.
  538. *
  539. * OUTPUTS val - read data
  540. *
  541. * RETURNS: PCIBIOS_SUCCESSFUL - success
  542. * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
  543. * -1 - read access failure
  544. *
  545. ****************************************************************************/
  546. static int
  547. msp_pcibios_read_config_dword(struct pci_bus *bus,
  548. unsigned int devfn,
  549. int where,
  550. u32 *val)
  551. {
  552. u32 data = 0;
  553. /* Address must be dword aligned. */
  554. if (where & 3) {
  555. *val = 0xFFFFFFFF;
  556. return PCIBIOS_BAD_REGISTER_NUMBER;
  557. }
  558. /*
  559. * If the config access did not complete normally (e.g., underwent
  560. * master abort) do the PCI compliant thing, which is to supply an
  561. * all ones value.
  562. */
  563. if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  564. where, &data)) {
  565. *val = 0xFFFFFFFF;
  566. return -1;
  567. }
  568. *val = data;
  569. return PCIBIOS_SUCCESSFUL;
  570. }
  571. /*****************************************************************************
  572. *
  573. * FUNCTION: msp_pcibios_write_config_byte
  574. * _________________________________________________________________________
  575. *
  576. * DESCRIPTION: Write a byte to PCI configuration address space.
  577. * Since the hardware can't address 8 bit chunks
  578. * directly, a read-modify-write is performed.
  579. *
  580. * INPUTS bus - structure containing attributes for the PCI bus
  581. * that the write is destined for.
  582. * devfn - device/function combination that the write is
  583. * destined for.
  584. * where - register within the Configuration Header space
  585. * to access.
  586. * val - value to write
  587. *
  588. * OUTPUTS none
  589. *
  590. * RETURNS: PCIBIOS_SUCCESSFUL - success
  591. * -1 - write access failure
  592. *
  593. ****************************************************************************/
  594. static int
  595. msp_pcibios_write_config_byte(struct pci_bus *bus,
  596. unsigned int devfn,
  597. int where,
  598. u8 val)
  599. {
  600. u32 data = 0;
  601. /* read config space */
  602. if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  603. where, &data))
  604. return -1;
  605. /* modify the byte within the dword */
  606. data = (data & ~(0xff << ((where & 3) << 3))) |
  607. (val << ((where & 3) << 3));
  608. /* write back the full dword */
  609. if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
  610. where, &data))
  611. return -1;
  612. return PCIBIOS_SUCCESSFUL;
  613. }
  614. /*****************************************************************************
  615. *
  616. * FUNCTION: msp_pcibios_write_config_word
  617. * _________________________________________________________________________
  618. *
  619. * DESCRIPTION: Write a word (16-bits) to PCI configuration address space.
  620. * Since the hardware can't address 16 bit chunks
  621. * directly, a read-modify-write is performed.
  622. *
  623. * INPUTS bus - structure containing attributes for the PCI bus
  624. * that the write is destined for.
  625. * devfn - device/function combination that the write is
  626. * destined for.
  627. * where - register within the Configuration Header space
  628. * to access.
  629. * val - value to write
  630. *
  631. * OUTPUTS none
  632. *
  633. * RETURNS: PCIBIOS_SUCCESSFUL - success
  634. * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
  635. * -1 - write access failure
  636. *
  637. ****************************************************************************/
  638. static int
  639. msp_pcibios_write_config_word(struct pci_bus *bus,
  640. unsigned int devfn,
  641. int where,
  642. u16 val)
  643. {
  644. u32 data = 0;
  645. /* Fixed non-compliance: if (where & 1) */
  646. if ((where & 3) == 3)
  647. return PCIBIOS_BAD_REGISTER_NUMBER;
  648. /* read config space */
  649. if (msp_pcibios_config_access(PCI_ACCESS_READ, bus, devfn,
  650. where, &data))
  651. return -1;
  652. /* modify the word within the dword */
  653. data = (data & ~(0xffff << ((where & 3) << 3))) |
  654. (val << ((where & 3) << 3));
  655. /* write back the full dword */
  656. if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
  657. where, &data))
  658. return -1;
  659. return PCIBIOS_SUCCESSFUL;
  660. }
  661. /*****************************************************************************
  662. *
  663. * FUNCTION: msp_pcibios_write_config_dword
  664. * _________________________________________________________________________
  665. *
  666. * DESCRIPTION: Write a double word (32-bits) to PCI configuration address
  667. * space.
  668. *
  669. * INPUTS bus - structure containing attributes for the PCI bus
  670. * that the write is destined for.
  671. * devfn - device/function combination that the write is
  672. * destined for.
  673. * where - register within the Configuration Header space
  674. * to access.
  675. * val - value to write
  676. *
  677. * OUTPUTS none
  678. *
  679. * RETURNS: PCIBIOS_SUCCESSFUL - success
  680. * PCIBIOS_BAD_REGISTER_NUMBER - bad register address
  681. * -1 - write access failure
  682. *
  683. ****************************************************************************/
  684. static int
  685. msp_pcibios_write_config_dword(struct pci_bus *bus,
  686. unsigned int devfn,
  687. int where,
  688. u32 val)
  689. {
  690. /* check that address is dword aligned */
  691. if (where & 3)
  692. return PCIBIOS_BAD_REGISTER_NUMBER;
  693. /* perform write */
  694. if (msp_pcibios_config_access(PCI_ACCESS_WRITE, bus, devfn,
  695. where, &val))
  696. return -1;
  697. return PCIBIOS_SUCCESSFUL;
  698. }
  699. /*****************************************************************************
  700. *
  701. * FUNCTION: msp_pcibios_read_config
  702. * _________________________________________________________________________
  703. *
  704. * DESCRIPTION: Interface the PCI configuration read request with
  705. * the appropriate function, based on how many bytes
  706. * the read request is.
  707. *
  708. * INPUTS bus - structure containing attributes for the PCI bus
  709. * that the write is destined for.
  710. * devfn - device/function combination that the write is
  711. * destined for.
  712. * where - register within the Configuration Header space
  713. * to access.
  714. * size - in units of bytes, should be 1, 2, or 4.
  715. *
  716. * OUTPUTS val - value read, with any extraneous bytes masked
  717. * to zero.
  718. *
  719. * RETURNS: PCIBIOS_SUCCESSFUL - success
  720. * -1 - failure
  721. *
  722. ****************************************************************************/
  723. int
  724. msp_pcibios_read_config(struct pci_bus *bus,
  725. unsigned int devfn,
  726. int where,
  727. int size,
  728. u32 *val)
  729. {
  730. if (size == 1) {
  731. if (msp_pcibios_read_config_byte(bus, devfn, where, val)) {
  732. return -1;
  733. }
  734. } else if (size == 2) {
  735. if (msp_pcibios_read_config_word(bus, devfn, where, val)) {
  736. return -1;
  737. }
  738. } else if (size == 4) {
  739. if (msp_pcibios_read_config_dword(bus, devfn, where, val)) {
  740. return -1;
  741. }
  742. } else {
  743. *val = 0xFFFFFFFF;
  744. return -1;
  745. }
  746. return PCIBIOS_SUCCESSFUL;
  747. }
  748. /*****************************************************************************
  749. *
  750. * FUNCTION: msp_pcibios_write_config
  751. * _________________________________________________________________________
  752. *
  753. * DESCRIPTION: Interface the PCI configuration write request with
  754. * the appropriate function, based on how many bytes
  755. * the read request is.
  756. *
  757. * INPUTS bus - structure containing attributes for the PCI bus
  758. * that the write is destined for.
  759. * devfn - device/function combination that the write is
  760. * destined for.
  761. * where - register within the Configuration Header space
  762. * to access.
  763. * size - in units of bytes, should be 1, 2, or 4.
  764. * val - value to write
  765. *
  766. * OUTPUTS: none
  767. *
  768. * RETURNS: PCIBIOS_SUCCESSFUL - success
  769. * -1 - failure
  770. *
  771. ****************************************************************************/
  772. int
  773. msp_pcibios_write_config(struct pci_bus *bus,
  774. unsigned int devfn,
  775. int where,
  776. int size,
  777. u32 val)
  778. {
  779. if (size == 1) {
  780. if (msp_pcibios_write_config_byte(bus, devfn,
  781. where, (u8)(0xFF & val))) {
  782. return -1;
  783. }
  784. } else if (size == 2) {
  785. if (msp_pcibios_write_config_word(bus, devfn,
  786. where, (u16)(0xFFFF & val))) {
  787. return -1;
  788. }
  789. } else if (size == 4) {
  790. if (msp_pcibios_write_config_dword(bus, devfn, where, val)) {
  791. return -1;
  792. }
  793. } else {
  794. return -1;
  795. }
  796. return PCIBIOS_SUCCESSFUL;
  797. }
  798. /*****************************************************************************
  799. *
  800. * STRUCTURE: msp_pci_ops
  801. * _________________________________________________________________________
  802. *
  803. * DESCRIPTION: structure to abstract the hardware specific PCI
  804. * configuration accesses.
  805. *
  806. * ELEMENTS:
  807. * read - function for Linux to generate PCI Configuration reads.
  808. * write - function for Linux to generate PCI Configuration writes.
  809. *
  810. ****************************************************************************/
  811. struct pci_ops msp_pci_ops = {
  812. .read = msp_pcibios_read_config,
  813. .write = msp_pcibios_write_config
  814. };
  815. /*****************************************************************************
  816. *
  817. * STRUCTURE: msp_pci_controller
  818. * _________________________________________________________________________
  819. *
  820. * Describes the attributes of the MSP7120 PCI Host Controller
  821. *
  822. * ELEMENTS:
  823. * pci_ops - abstracts the hardware specific PCI configuration
  824. * accesses.
  825. *
  826. * mem_resource - address range pciauto() uses to assign to PCI device
  827. * memory BARs.
  828. *
  829. * mem_offset - offset between how MSP7120 outbound PCI memory
  830. * transaction addresses appear on the PCI bus and how Linux
  831. * wants to configure memory BARs of the PCI devices.
  832. * MSP7120 does nothing funky, so just set to zero.
  833. *
  834. * io_resource - address range pciauto() uses to assign to PCI device
  835. * I/O BARs.
  836. *
  837. * io_offset - offset between how MSP7120 outbound PCI I/O
  838. * transaction addresses appear on the PCI bus and how
  839. * Linux defaults to configure I/O BARs of the PCI devices.
  840. * MSP7120 maps outbound I/O accesses into the bottom
  841. * bottom 4K of PCI address space (and ignores OATRAN).
  842. * Since the Linux default is to configure I/O BARs to the
  843. * bottom 4K, no special offset is needed. Just set to zero.
  844. *
  845. ****************************************************************************/
  846. static struct pci_controller msp_pci_controller = {
  847. .pci_ops = &msp_pci_ops,
  848. .mem_resource = &pci_mem_resource,
  849. .mem_offset = 0,
  850. .io_map_base = MSP_PCI_IOSPACE_BASE,
  851. .io_resource = &pci_io_resource,
  852. .io_offset = 0
  853. };
  854. /*****************************************************************************
  855. *
  856. * FUNCTION: msp_pci_init
  857. * _________________________________________________________________________
  858. *
  859. * DESCRIPTION: Initialize the PCI Host Controller and register it with
  860. * Linux so Linux can seize control of the PCI bus.
  861. *
  862. ****************************************************************************/
  863. void __init msp_pci_init(void)
  864. {
  865. struct msp_pci_regs *preg = (void *)PCI_BASE_REG;
  866. u32 id;
  867. /* Extract Device ID */
  868. id = read_reg32(PCI_JTAG_DEVID_REG, 0xFFFF) >> 12;
  869. /* Check if JTAG ID identifies MSP7120 */
  870. if (!MSP_HAS_PCI(id)) {
  871. printk(KERN_WARNING "PCI: No PCI; id reads as %x\n", id);
  872. goto no_pci;
  873. }
  874. /*
  875. * Enable flushing of the PCI-SDRAM queue upon a read
  876. * of the SDRAM's Memory Configuration Register.
  877. */
  878. *(unsigned long *)QFLUSH_REG_1 = 3;
  879. /* Configure PCI Host Controller. */
  880. preg->if_status = ~0; /* Clear cause register bits */
  881. preg->config_addr = 0; /* Clear config access */
  882. preg->oatran = MSP_PCI_OATRAN; /* PCI outbound addr translation */
  883. preg->if_mask = 0xF8BF87C0; /* Enable all PCI status interrupts */
  884. /* configure so inb(), outb(), and family are functional */
  885. set_io_port_base(MSP_PCI_IOSPACE_BASE);
  886. /* Tell Linux the details of the MSP7120 PCI Host Controller */
  887. register_pci_controller(&msp_pci_controller);
  888. return;
  889. no_pci:
  890. /* Disable PCI channel */
  891. printk(KERN_WARNING "PCI: no host PCI bus detected\n");
  892. }