sead3-time.c 2.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  7. */
  8. #include <linux/init.h>
  9. #include <asm/setup.h>
  10. #include <asm/time.h>
  11. #include <asm/irq.h>
  12. #include <asm/mips-boards/generic.h>
  13. unsigned long cpu_khz;
  14. static int mips_cpu_timer_irq;
  15. static int mips_cpu_perf_irq;
  16. static void mips_timer_dispatch(void)
  17. {
  18. do_IRQ(mips_cpu_timer_irq);
  19. }
  20. static void mips_perf_dispatch(void)
  21. {
  22. do_IRQ(mips_cpu_perf_irq);
  23. }
  24. static void __iomem *status_reg = (void __iomem *)0xbf000410;
  25. /*
  26. * Estimate CPU frequency. Sets mips_hpt_frequency as a side-effect.
  27. */
  28. static unsigned int __init estimate_cpu_frequency(void)
  29. {
  30. unsigned int prid = read_c0_prid() & 0xffff00;
  31. unsigned int tick = 0;
  32. unsigned int freq;
  33. unsigned int orig;
  34. unsigned long flags;
  35. local_irq_save(flags);
  36. orig = readl(status_reg) & 0x2; /* get original sample */
  37. /* wait for transition */
  38. while ((readl(status_reg) & 0x2) == orig)
  39. ;
  40. orig = orig ^ 0x2; /* flip the bit */
  41. write_c0_count(0);
  42. /* wait 1 second (the sampling clock transitions every 10ms) */
  43. while (tick < 100) {
  44. /* wait for transition */
  45. while ((readl(status_reg) & 0x2) == orig)
  46. ;
  47. orig = orig ^ 0x2; /* flip the bit */
  48. tick++;
  49. }
  50. freq = read_c0_count();
  51. local_irq_restore(flags);
  52. mips_hpt_frequency = freq;
  53. /* Adjust for processor */
  54. if ((prid != (PRID_COMP_MIPS | PRID_IMP_20KC)) &&
  55. (prid != (PRID_COMP_MIPS | PRID_IMP_25KF)))
  56. freq *= 2;
  57. freq += 5000; /* rounding */
  58. freq -= freq%10000;
  59. return freq ;
  60. }
  61. void read_persistent_clock(struct timespec *ts)
  62. {
  63. ts->tv_sec = 0;
  64. ts->tv_nsec = 0;
  65. }
  66. static void __init plat_perf_setup(void)
  67. {
  68. if (cp0_perfcount_irq >= 0) {
  69. if (cpu_has_vint)
  70. set_vi_handler(cp0_perfcount_irq, mips_perf_dispatch);
  71. mips_cpu_perf_irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq;
  72. }
  73. }
  74. unsigned int get_c0_compare_int(void)
  75. {
  76. if (cpu_has_vint)
  77. set_vi_handler(cp0_compare_irq, mips_timer_dispatch);
  78. mips_cpu_timer_irq = MIPS_CPU_IRQ_BASE + cp0_compare_irq;
  79. return mips_cpu_timer_irq;
  80. }
  81. void __init plat_time_init(void)
  82. {
  83. unsigned int est_freq;
  84. est_freq = estimate_cpu_frequency();
  85. pr_debug("CPU frequency %d.%02d MHz\n", (est_freq / 1000000),
  86. (est_freq % 1000000) * 100 / 1000000);
  87. cpu_khz = est_freq / 1000;
  88. mips_scroll_message();
  89. plat_perf_setup();
  90. }