unaligned.c 41 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058105910601061106210631064106510661067106810691070107110721073107410751076107710781079108010811082108310841085108610871088108910901091109210931094109510961097109810991100110111021103110411051106110711081109111011111112111311141115111611171118111911201121112211231124112511261127112811291130113111321133113411351136113711381139114011411142114311441145114611471148114911501151115211531154115511561157115811591160116111621163116411651166116711681169117011711172117311741175117611771178117911801181118211831184118511861187118811891190119111921193119411951196119711981199120012011202120312041205120612071208120912101211121212131214121512161217121812191220122112221223122412251226122712281229123012311232123312341235123612371238123912401241124212431244124512461247124812491250125112521253125412551256125712581259126012611262126312641265126612671268126912701271127212731274127512761277127812791280128112821283128412851286128712881289129012911292129312941295129612971298129913001301130213031304130513061307130813091310131113121313131413151316131713181319132013211322132313241325132613271328132913301331133213331334133513361337133813391340134113421343134413451346134713481349135013511352135313541355135613571358135913601361136213631364136513661367136813691370137113721373137413751376137713781379138013811382138313841385138613871388138913901391139213931394139513961397139813991400140114021403140414051406140714081409141014111412141314141415141614171418141914201421142214231424142514261427142814291430143114321433143414351436143714381439144014411442144314441445144614471448144914501451145214531454145514561457145814591460146114621463146414651466146714681469147014711472147314741475147614771478147914801481148214831484148514861487148814891490149114921493149414951496149714981499150015011502150315041505150615071508150915101511151215131514151515161517151815191520152115221523152415251526152715281529153015311532153315341535153615371538153915401541154215431544154515461547154815491550155115521553155415551556155715581559156015611562156315641565156615671568156915701571157215731574157515761577157815791580158115821583158415851586158715881589159015911592159315941595159615971598159916001601160216031604160516061607160816091610161116121613161416151616161716181619162016211622162316241625162616271628162916301631163216331634163516361637163816391640164116421643164416451646164716481649165016511652165316541655165616571658
  1. /*
  2. * Handle unaligned accesses by emulation.
  3. *
  4. * This file is subject to the terms and conditions of the GNU General Public
  5. * License. See the file "COPYING" in the main directory of this archive
  6. * for more details.
  7. *
  8. * Copyright (C) 1996, 1998, 1999, 2002 by Ralf Baechle
  9. * Copyright (C) 1999 Silicon Graphics, Inc.
  10. *
  11. * This file contains exception handler for address error exception with the
  12. * special capability to execute faulting instructions in software. The
  13. * handler does not try to handle the case when the program counter points
  14. * to an address not aligned to a word boundary.
  15. *
  16. * Putting data to unaligned addresses is a bad practice even on Intel where
  17. * only the performance is affected. Much worse is that such code is non-
  18. * portable. Due to several programs that die on MIPS due to alignment
  19. * problems I decided to implement this handler anyway though I originally
  20. * didn't intend to do this at all for user code.
  21. *
  22. * For now I enable fixing of address errors by default to make life easier.
  23. * I however intend to disable this somewhen in the future when the alignment
  24. * problems with user programs have been fixed. For programmers this is the
  25. * right way to go.
  26. *
  27. * Fixing address errors is a per process option. The option is inherited
  28. * across fork(2) and execve(2) calls. If you really want to use the
  29. * option in your user programs - I discourage the use of the software
  30. * emulation strongly - use the following code in your userland stuff:
  31. *
  32. * #include <sys/sysmips.h>
  33. *
  34. * ...
  35. * sysmips(MIPS_FIXADE, x);
  36. * ...
  37. *
  38. * The argument x is 0 for disabling software emulation, enabled otherwise.
  39. *
  40. * Below a little program to play around with this feature.
  41. *
  42. * #include <stdio.h>
  43. * #include <sys/sysmips.h>
  44. *
  45. * struct foo {
  46. * unsigned char bar[8];
  47. * };
  48. *
  49. * main(int argc, char *argv[])
  50. * {
  51. * struct foo x = {0, 1, 2, 3, 4, 5, 6, 7};
  52. * unsigned int *p = (unsigned int *) (x.bar + 3);
  53. * int i;
  54. *
  55. * if (argc > 1)
  56. * sysmips(MIPS_FIXADE, atoi(argv[1]));
  57. *
  58. * printf("*p = %08lx\n", *p);
  59. *
  60. * *p = 0xdeadface;
  61. *
  62. * for(i = 0; i <= 7; i++)
  63. * printf("%02x ", x.bar[i]);
  64. * printf("\n");
  65. * }
  66. *
  67. * Coprocessor loads are not supported; I think this case is unimportant
  68. * in the practice.
  69. *
  70. * TODO: Handle ndc (attempted store to doubleword in uncached memory)
  71. * exception for the R6000.
  72. * A store crossing a page boundary might be executed only partially.
  73. * Undo the partial store in this case.
  74. */
  75. #include <linux/context_tracking.h>
  76. #include <linux/mm.h>
  77. #include <linux/signal.h>
  78. #include <linux/smp.h>
  79. #include <linux/sched.h>
  80. #include <linux/debugfs.h>
  81. #include <linux/perf_event.h>
  82. #include <asm/asm.h>
  83. #include <asm/branch.h>
  84. #include <asm/byteorder.h>
  85. #include <asm/cop2.h>
  86. #include <asm/fpu.h>
  87. #include <asm/fpu_emulator.h>
  88. #include <asm/inst.h>
  89. #include <asm/uaccess.h>
  90. #include <asm/fpu.h>
  91. #include <asm/fpu_emulator.h>
  92. #define STR(x) __STR(x)
  93. #define __STR(x) #x
  94. enum {
  95. UNALIGNED_ACTION_QUIET,
  96. UNALIGNED_ACTION_SIGNAL,
  97. UNALIGNED_ACTION_SHOW,
  98. };
  99. #ifdef CONFIG_DEBUG_FS
  100. static u32 unaligned_instructions;
  101. static u32 unaligned_action;
  102. #else
  103. #define unaligned_action UNALIGNED_ACTION_QUIET
  104. #endif
  105. extern void show_registers(struct pt_regs *regs);
  106. #ifdef __BIG_ENDIAN
  107. #define LoadHW(addr, value, res) \
  108. __asm__ __volatile__ (".set\tnoat\n" \
  109. "1:\tlb\t%0, 0(%2)\n" \
  110. "2:\tlbu\t$1, 1(%2)\n\t" \
  111. "sll\t%0, 0x8\n\t" \
  112. "or\t%0, $1\n\t" \
  113. "li\t%1, 0\n" \
  114. "3:\t.set\tat\n\t" \
  115. ".insn\n\t" \
  116. ".section\t.fixup,\"ax\"\n\t" \
  117. "4:\tli\t%1, %3\n\t" \
  118. "j\t3b\n\t" \
  119. ".previous\n\t" \
  120. ".section\t__ex_table,\"a\"\n\t" \
  121. STR(PTR)"\t1b, 4b\n\t" \
  122. STR(PTR)"\t2b, 4b\n\t" \
  123. ".previous" \
  124. : "=&r" (value), "=r" (res) \
  125. : "r" (addr), "i" (-EFAULT));
  126. #define LoadW(addr, value, res) \
  127. __asm__ __volatile__ ( \
  128. "1:\tlwl\t%0, (%2)\n" \
  129. "2:\tlwr\t%0, 3(%2)\n\t" \
  130. "li\t%1, 0\n" \
  131. "3:\n\t" \
  132. ".insn\n\t" \
  133. ".section\t.fixup,\"ax\"\n\t" \
  134. "4:\tli\t%1, %3\n\t" \
  135. "j\t3b\n\t" \
  136. ".previous\n\t" \
  137. ".section\t__ex_table,\"a\"\n\t" \
  138. STR(PTR)"\t1b, 4b\n\t" \
  139. STR(PTR)"\t2b, 4b\n\t" \
  140. ".previous" \
  141. : "=&r" (value), "=r" (res) \
  142. : "r" (addr), "i" (-EFAULT));
  143. #define LoadHWU(addr, value, res) \
  144. __asm__ __volatile__ ( \
  145. ".set\tnoat\n" \
  146. "1:\tlbu\t%0, 0(%2)\n" \
  147. "2:\tlbu\t$1, 1(%2)\n\t" \
  148. "sll\t%0, 0x8\n\t" \
  149. "or\t%0, $1\n\t" \
  150. "li\t%1, 0\n" \
  151. "3:\n\t" \
  152. ".insn\n\t" \
  153. ".set\tat\n\t" \
  154. ".section\t.fixup,\"ax\"\n\t" \
  155. "4:\tli\t%1, %3\n\t" \
  156. "j\t3b\n\t" \
  157. ".previous\n\t" \
  158. ".section\t__ex_table,\"a\"\n\t" \
  159. STR(PTR)"\t1b, 4b\n\t" \
  160. STR(PTR)"\t2b, 4b\n\t" \
  161. ".previous" \
  162. : "=&r" (value), "=r" (res) \
  163. : "r" (addr), "i" (-EFAULT));
  164. #define LoadWU(addr, value, res) \
  165. __asm__ __volatile__ ( \
  166. "1:\tlwl\t%0, (%2)\n" \
  167. "2:\tlwr\t%0, 3(%2)\n\t" \
  168. "dsll\t%0, %0, 32\n\t" \
  169. "dsrl\t%0, %0, 32\n\t" \
  170. "li\t%1, 0\n" \
  171. "3:\n\t" \
  172. ".insn\n\t" \
  173. "\t.section\t.fixup,\"ax\"\n\t" \
  174. "4:\tli\t%1, %3\n\t" \
  175. "j\t3b\n\t" \
  176. ".previous\n\t" \
  177. ".section\t__ex_table,\"a\"\n\t" \
  178. STR(PTR)"\t1b, 4b\n\t" \
  179. STR(PTR)"\t2b, 4b\n\t" \
  180. ".previous" \
  181. : "=&r" (value), "=r" (res) \
  182. : "r" (addr), "i" (-EFAULT));
  183. #define LoadDW(addr, value, res) \
  184. __asm__ __volatile__ ( \
  185. "1:\tldl\t%0, (%2)\n" \
  186. "2:\tldr\t%0, 7(%2)\n\t" \
  187. "li\t%1, 0\n" \
  188. "3:\n\t" \
  189. ".insn\n\t" \
  190. "\t.section\t.fixup,\"ax\"\n\t" \
  191. "4:\tli\t%1, %3\n\t" \
  192. "j\t3b\n\t" \
  193. ".previous\n\t" \
  194. ".section\t__ex_table,\"a\"\n\t" \
  195. STR(PTR)"\t1b, 4b\n\t" \
  196. STR(PTR)"\t2b, 4b\n\t" \
  197. ".previous" \
  198. : "=&r" (value), "=r" (res) \
  199. : "r" (addr), "i" (-EFAULT));
  200. #define StoreHW(addr, value, res) \
  201. __asm__ __volatile__ ( \
  202. ".set\tnoat\n" \
  203. "1:\tsb\t%1, 1(%2)\n\t" \
  204. "srl\t$1, %1, 0x8\n" \
  205. "2:\tsb\t$1, 0(%2)\n\t" \
  206. ".set\tat\n\t" \
  207. "li\t%0, 0\n" \
  208. "3:\n\t" \
  209. ".insn\n\t" \
  210. ".section\t.fixup,\"ax\"\n\t" \
  211. "4:\tli\t%0, %3\n\t" \
  212. "j\t3b\n\t" \
  213. ".previous\n\t" \
  214. ".section\t__ex_table,\"a\"\n\t" \
  215. STR(PTR)"\t1b, 4b\n\t" \
  216. STR(PTR)"\t2b, 4b\n\t" \
  217. ".previous" \
  218. : "=r" (res) \
  219. : "r" (value), "r" (addr), "i" (-EFAULT));
  220. #define StoreW(addr, value, res) \
  221. __asm__ __volatile__ ( \
  222. "1:\tswl\t%1,(%2)\n" \
  223. "2:\tswr\t%1, 3(%2)\n\t" \
  224. "li\t%0, 0\n" \
  225. "3:\n\t" \
  226. ".insn\n\t" \
  227. ".section\t.fixup,\"ax\"\n\t" \
  228. "4:\tli\t%0, %3\n\t" \
  229. "j\t3b\n\t" \
  230. ".previous\n\t" \
  231. ".section\t__ex_table,\"a\"\n\t" \
  232. STR(PTR)"\t1b, 4b\n\t" \
  233. STR(PTR)"\t2b, 4b\n\t" \
  234. ".previous" \
  235. : "=r" (res) \
  236. : "r" (value), "r" (addr), "i" (-EFAULT));
  237. #define StoreDW(addr, value, res) \
  238. __asm__ __volatile__ ( \
  239. "1:\tsdl\t%1,(%2)\n" \
  240. "2:\tsdr\t%1, 7(%2)\n\t" \
  241. "li\t%0, 0\n" \
  242. "3:\n\t" \
  243. ".insn\n\t" \
  244. ".section\t.fixup,\"ax\"\n\t" \
  245. "4:\tli\t%0, %3\n\t" \
  246. "j\t3b\n\t" \
  247. ".previous\n\t" \
  248. ".section\t__ex_table,\"a\"\n\t" \
  249. STR(PTR)"\t1b, 4b\n\t" \
  250. STR(PTR)"\t2b, 4b\n\t" \
  251. ".previous" \
  252. : "=r" (res) \
  253. : "r" (value), "r" (addr), "i" (-EFAULT));
  254. #endif
  255. #ifdef __LITTLE_ENDIAN
  256. #define LoadHW(addr, value, res) \
  257. __asm__ __volatile__ (".set\tnoat\n" \
  258. "1:\tlb\t%0, 1(%2)\n" \
  259. "2:\tlbu\t$1, 0(%2)\n\t" \
  260. "sll\t%0, 0x8\n\t" \
  261. "or\t%0, $1\n\t" \
  262. "li\t%1, 0\n" \
  263. "3:\t.set\tat\n\t" \
  264. ".insn\n\t" \
  265. ".section\t.fixup,\"ax\"\n\t" \
  266. "4:\tli\t%1, %3\n\t" \
  267. "j\t3b\n\t" \
  268. ".previous\n\t" \
  269. ".section\t__ex_table,\"a\"\n\t" \
  270. STR(PTR)"\t1b, 4b\n\t" \
  271. STR(PTR)"\t2b, 4b\n\t" \
  272. ".previous" \
  273. : "=&r" (value), "=r" (res) \
  274. : "r" (addr), "i" (-EFAULT));
  275. #define LoadW(addr, value, res) \
  276. __asm__ __volatile__ ( \
  277. "1:\tlwl\t%0, 3(%2)\n" \
  278. "2:\tlwr\t%0, (%2)\n\t" \
  279. "li\t%1, 0\n" \
  280. "3:\n\t" \
  281. ".insn\n\t" \
  282. ".section\t.fixup,\"ax\"\n\t" \
  283. "4:\tli\t%1, %3\n\t" \
  284. "j\t3b\n\t" \
  285. ".previous\n\t" \
  286. ".section\t__ex_table,\"a\"\n\t" \
  287. STR(PTR)"\t1b, 4b\n\t" \
  288. STR(PTR)"\t2b, 4b\n\t" \
  289. ".previous" \
  290. : "=&r" (value), "=r" (res) \
  291. : "r" (addr), "i" (-EFAULT));
  292. #define LoadHWU(addr, value, res) \
  293. __asm__ __volatile__ ( \
  294. ".set\tnoat\n" \
  295. "1:\tlbu\t%0, 1(%2)\n" \
  296. "2:\tlbu\t$1, 0(%2)\n\t" \
  297. "sll\t%0, 0x8\n\t" \
  298. "or\t%0, $1\n\t" \
  299. "li\t%1, 0\n" \
  300. "3:\n\t" \
  301. ".insn\n\t" \
  302. ".set\tat\n\t" \
  303. ".section\t.fixup,\"ax\"\n\t" \
  304. "4:\tli\t%1, %3\n\t" \
  305. "j\t3b\n\t" \
  306. ".previous\n\t" \
  307. ".section\t__ex_table,\"a\"\n\t" \
  308. STR(PTR)"\t1b, 4b\n\t" \
  309. STR(PTR)"\t2b, 4b\n\t" \
  310. ".previous" \
  311. : "=&r" (value), "=r" (res) \
  312. : "r" (addr), "i" (-EFAULT));
  313. #define LoadWU(addr, value, res) \
  314. __asm__ __volatile__ ( \
  315. "1:\tlwl\t%0, 3(%2)\n" \
  316. "2:\tlwr\t%0, (%2)\n\t" \
  317. "dsll\t%0, %0, 32\n\t" \
  318. "dsrl\t%0, %0, 32\n\t" \
  319. "li\t%1, 0\n" \
  320. "3:\n\t" \
  321. ".insn\n\t" \
  322. "\t.section\t.fixup,\"ax\"\n\t" \
  323. "4:\tli\t%1, %3\n\t" \
  324. "j\t3b\n\t" \
  325. ".previous\n\t" \
  326. ".section\t__ex_table,\"a\"\n\t" \
  327. STR(PTR)"\t1b, 4b\n\t" \
  328. STR(PTR)"\t2b, 4b\n\t" \
  329. ".previous" \
  330. : "=&r" (value), "=r" (res) \
  331. : "r" (addr), "i" (-EFAULT));
  332. #define LoadDW(addr, value, res) \
  333. __asm__ __volatile__ ( \
  334. "1:\tldl\t%0, 7(%2)\n" \
  335. "2:\tldr\t%0, (%2)\n\t" \
  336. "li\t%1, 0\n" \
  337. "3:\n\t" \
  338. ".insn\n\t" \
  339. "\t.section\t.fixup,\"ax\"\n\t" \
  340. "4:\tli\t%1, %3\n\t" \
  341. "j\t3b\n\t" \
  342. ".previous\n\t" \
  343. ".section\t__ex_table,\"a\"\n\t" \
  344. STR(PTR)"\t1b, 4b\n\t" \
  345. STR(PTR)"\t2b, 4b\n\t" \
  346. ".previous" \
  347. : "=&r" (value), "=r" (res) \
  348. : "r" (addr), "i" (-EFAULT));
  349. #define StoreHW(addr, value, res) \
  350. __asm__ __volatile__ ( \
  351. ".set\tnoat\n" \
  352. "1:\tsb\t%1, 0(%2)\n\t" \
  353. "srl\t$1,%1, 0x8\n" \
  354. "2:\tsb\t$1, 1(%2)\n\t" \
  355. ".set\tat\n\t" \
  356. "li\t%0, 0\n" \
  357. "3:\n\t" \
  358. ".insn\n\t" \
  359. ".section\t.fixup,\"ax\"\n\t" \
  360. "4:\tli\t%0, %3\n\t" \
  361. "j\t3b\n\t" \
  362. ".previous\n\t" \
  363. ".section\t__ex_table,\"a\"\n\t" \
  364. STR(PTR)"\t1b, 4b\n\t" \
  365. STR(PTR)"\t2b, 4b\n\t" \
  366. ".previous" \
  367. : "=r" (res) \
  368. : "r" (value), "r" (addr), "i" (-EFAULT));
  369. #define StoreW(addr, value, res) \
  370. __asm__ __volatile__ ( \
  371. "1:\tswl\t%1, 3(%2)\n" \
  372. "2:\tswr\t%1, (%2)\n\t" \
  373. "li\t%0, 0\n" \
  374. "3:\n\t" \
  375. ".insn\n\t" \
  376. ".section\t.fixup,\"ax\"\n\t" \
  377. "4:\tli\t%0, %3\n\t" \
  378. "j\t3b\n\t" \
  379. ".previous\n\t" \
  380. ".section\t__ex_table,\"a\"\n\t" \
  381. STR(PTR)"\t1b, 4b\n\t" \
  382. STR(PTR)"\t2b, 4b\n\t" \
  383. ".previous" \
  384. : "=r" (res) \
  385. : "r" (value), "r" (addr), "i" (-EFAULT));
  386. #define StoreDW(addr, value, res) \
  387. __asm__ __volatile__ ( \
  388. "1:\tsdl\t%1, 7(%2)\n" \
  389. "2:\tsdr\t%1, (%2)\n\t" \
  390. "li\t%0, 0\n" \
  391. "3:\n\t" \
  392. ".insn\n\t" \
  393. ".section\t.fixup,\"ax\"\n\t" \
  394. "4:\tli\t%0, %3\n\t" \
  395. "j\t3b\n\t" \
  396. ".previous\n\t" \
  397. ".section\t__ex_table,\"a\"\n\t" \
  398. STR(PTR)"\t1b, 4b\n\t" \
  399. STR(PTR)"\t2b, 4b\n\t" \
  400. ".previous" \
  401. : "=r" (res) \
  402. : "r" (value), "r" (addr), "i" (-EFAULT));
  403. #endif
  404. static void emulate_load_store_insn(struct pt_regs *regs,
  405. void __user *addr, unsigned int __user *pc)
  406. {
  407. union mips_instruction insn;
  408. unsigned long value;
  409. unsigned int res;
  410. unsigned long origpc;
  411. unsigned long orig31;
  412. void __user *fault_addr = NULL;
  413. origpc = (unsigned long)pc;
  414. orig31 = regs->regs[31];
  415. perf_sw_event(PERF_COUNT_SW_EMULATION_FAULTS, 1, regs, 0);
  416. /*
  417. * This load never faults.
  418. */
  419. __get_user(insn.word, pc);
  420. switch (insn.i_format.opcode) {
  421. /*
  422. * These are instructions that a compiler doesn't generate. We
  423. * can assume therefore that the code is MIPS-aware and
  424. * really buggy. Emulating these instructions would break the
  425. * semantics anyway.
  426. */
  427. case ll_op:
  428. case lld_op:
  429. case sc_op:
  430. case scd_op:
  431. /*
  432. * For these instructions the only way to create an address
  433. * error is an attempted access to kernel/supervisor address
  434. * space.
  435. */
  436. case ldl_op:
  437. case ldr_op:
  438. case lwl_op:
  439. case lwr_op:
  440. case sdl_op:
  441. case sdr_op:
  442. case swl_op:
  443. case swr_op:
  444. case lb_op:
  445. case lbu_op:
  446. case sb_op:
  447. goto sigbus;
  448. /*
  449. * The remaining opcodes are the ones that are really of
  450. * interest.
  451. */
  452. case lh_op:
  453. if (!access_ok(VERIFY_READ, addr, 2))
  454. goto sigbus;
  455. LoadHW(addr, value, res);
  456. if (res)
  457. goto fault;
  458. compute_return_epc(regs);
  459. regs->regs[insn.i_format.rt] = value;
  460. break;
  461. case lw_op:
  462. if (!access_ok(VERIFY_READ, addr, 4))
  463. goto sigbus;
  464. LoadW(addr, value, res);
  465. if (res)
  466. goto fault;
  467. compute_return_epc(regs);
  468. regs->regs[insn.i_format.rt] = value;
  469. break;
  470. case lhu_op:
  471. if (!access_ok(VERIFY_READ, addr, 2))
  472. goto sigbus;
  473. LoadHWU(addr, value, res);
  474. if (res)
  475. goto fault;
  476. compute_return_epc(regs);
  477. regs->regs[insn.i_format.rt] = value;
  478. break;
  479. case lwu_op:
  480. #ifdef CONFIG_64BIT
  481. /*
  482. * A 32-bit kernel might be running on a 64-bit processor. But
  483. * if we're on a 32-bit processor and an i-cache incoherency
  484. * or race makes us see a 64-bit instruction here the sdl/sdr
  485. * would blow up, so for now we don't handle unaligned 64-bit
  486. * instructions on 32-bit kernels.
  487. */
  488. if (!access_ok(VERIFY_READ, addr, 4))
  489. goto sigbus;
  490. LoadWU(addr, value, res);
  491. if (res)
  492. goto fault;
  493. compute_return_epc(regs);
  494. regs->regs[insn.i_format.rt] = value;
  495. break;
  496. #endif /* CONFIG_64BIT */
  497. /* Cannot handle 64-bit instructions in 32-bit kernel */
  498. goto sigill;
  499. case ld_op:
  500. #ifdef CONFIG_64BIT
  501. /*
  502. * A 32-bit kernel might be running on a 64-bit processor. But
  503. * if we're on a 32-bit processor and an i-cache incoherency
  504. * or race makes us see a 64-bit instruction here the sdl/sdr
  505. * would blow up, so for now we don't handle unaligned 64-bit
  506. * instructions on 32-bit kernels.
  507. */
  508. if (!access_ok(VERIFY_READ, addr, 8))
  509. goto sigbus;
  510. LoadDW(addr, value, res);
  511. if (res)
  512. goto fault;
  513. compute_return_epc(regs);
  514. regs->regs[insn.i_format.rt] = value;
  515. break;
  516. #endif /* CONFIG_64BIT */
  517. /* Cannot handle 64-bit instructions in 32-bit kernel */
  518. goto sigill;
  519. case sh_op:
  520. if (!access_ok(VERIFY_WRITE, addr, 2))
  521. goto sigbus;
  522. compute_return_epc(regs);
  523. value = regs->regs[insn.i_format.rt];
  524. StoreHW(addr, value, res);
  525. if (res)
  526. goto fault;
  527. break;
  528. case sw_op:
  529. if (!access_ok(VERIFY_WRITE, addr, 4))
  530. goto sigbus;
  531. compute_return_epc(regs);
  532. value = regs->regs[insn.i_format.rt];
  533. StoreW(addr, value, res);
  534. if (res)
  535. goto fault;
  536. break;
  537. case sd_op:
  538. #ifdef CONFIG_64BIT
  539. /*
  540. * A 32-bit kernel might be running on a 64-bit processor. But
  541. * if we're on a 32-bit processor and an i-cache incoherency
  542. * or race makes us see a 64-bit instruction here the sdl/sdr
  543. * would blow up, so for now we don't handle unaligned 64-bit
  544. * instructions on 32-bit kernels.
  545. */
  546. if (!access_ok(VERIFY_WRITE, addr, 8))
  547. goto sigbus;
  548. compute_return_epc(regs);
  549. value = regs->regs[insn.i_format.rt];
  550. StoreDW(addr, value, res);
  551. if (res)
  552. goto fault;
  553. break;
  554. #endif /* CONFIG_64BIT */
  555. /* Cannot handle 64-bit instructions in 32-bit kernel */
  556. goto sigill;
  557. case lwc1_op:
  558. case ldc1_op:
  559. case swc1_op:
  560. case sdc1_op:
  561. die_if_kernel("Unaligned FP access in kernel code", regs);
  562. BUG_ON(!used_math());
  563. BUG_ON(!is_fpu_owner());
  564. lose_fpu(1); /* Save FPU state for the emulator. */
  565. res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
  566. &fault_addr);
  567. own_fpu(1); /* Restore FPU state. */
  568. /* Signal if something went wrong. */
  569. process_fpemu_return(res, fault_addr);
  570. if (res == 0)
  571. break;
  572. return;
  573. /*
  574. * COP2 is available to implementor for application specific use.
  575. * It's up to applications to register a notifier chain and do
  576. * whatever they have to do, including possible sending of signals.
  577. */
  578. case lwc2_op:
  579. cu2_notifier_call_chain(CU2_LWC2_OP, regs);
  580. break;
  581. case ldc2_op:
  582. cu2_notifier_call_chain(CU2_LDC2_OP, regs);
  583. break;
  584. case swc2_op:
  585. cu2_notifier_call_chain(CU2_SWC2_OP, regs);
  586. break;
  587. case sdc2_op:
  588. cu2_notifier_call_chain(CU2_SDC2_OP, regs);
  589. break;
  590. default:
  591. /*
  592. * Pheeee... We encountered an yet unknown instruction or
  593. * cache coherence problem. Die sucker, die ...
  594. */
  595. goto sigill;
  596. }
  597. #ifdef CONFIG_DEBUG_FS
  598. unaligned_instructions++;
  599. #endif
  600. return;
  601. fault:
  602. /* roll back jump/branch */
  603. regs->cp0_epc = origpc;
  604. regs->regs[31] = orig31;
  605. /* Did we have an exception handler installed? */
  606. if (fixup_exception(regs))
  607. return;
  608. die_if_kernel("Unhandled kernel unaligned access", regs);
  609. force_sig(SIGSEGV, current);
  610. return;
  611. sigbus:
  612. die_if_kernel("Unhandled kernel unaligned access", regs);
  613. force_sig(SIGBUS, current);
  614. return;
  615. sigill:
  616. die_if_kernel
  617. ("Unhandled kernel unaligned access or invalid instruction", regs);
  618. force_sig(SIGILL, current);
  619. }
  620. /* Recode table from 16-bit register notation to 32-bit GPR. */
  621. const int reg16to32[] = { 16, 17, 2, 3, 4, 5, 6, 7 };
  622. /* Recode table from 16-bit STORE register notation to 32-bit GPR. */
  623. const int reg16to32st[] = { 0, 17, 2, 3, 4, 5, 6, 7 };
  624. static void emulate_load_store_microMIPS(struct pt_regs *regs,
  625. void __user *addr)
  626. {
  627. unsigned long value;
  628. unsigned int res;
  629. int i;
  630. unsigned int reg = 0, rvar;
  631. unsigned long orig31;
  632. u16 __user *pc16;
  633. u16 halfword;
  634. unsigned int word;
  635. unsigned long origpc, contpc;
  636. union mips_instruction insn;
  637. struct mm_decoded_insn mminsn;
  638. void __user *fault_addr = NULL;
  639. origpc = regs->cp0_epc;
  640. orig31 = regs->regs[31];
  641. mminsn.micro_mips_mode = 1;
  642. /*
  643. * This load never faults.
  644. */
  645. pc16 = (unsigned short __user *)msk_isa16_mode(regs->cp0_epc);
  646. __get_user(halfword, pc16);
  647. pc16++;
  648. contpc = regs->cp0_epc + 2;
  649. word = ((unsigned int)halfword << 16);
  650. mminsn.pc_inc = 2;
  651. if (!mm_insn_16bit(halfword)) {
  652. __get_user(halfword, pc16);
  653. pc16++;
  654. contpc = regs->cp0_epc + 4;
  655. mminsn.pc_inc = 4;
  656. word |= halfword;
  657. }
  658. mminsn.insn = word;
  659. if (get_user(halfword, pc16))
  660. goto fault;
  661. mminsn.next_pc_inc = 2;
  662. word = ((unsigned int)halfword << 16);
  663. if (!mm_insn_16bit(halfword)) {
  664. pc16++;
  665. if (get_user(halfword, pc16))
  666. goto fault;
  667. mminsn.next_pc_inc = 4;
  668. word |= halfword;
  669. }
  670. mminsn.next_insn = word;
  671. insn = (union mips_instruction)(mminsn.insn);
  672. if (mm_isBranchInstr(regs, mminsn, &contpc))
  673. insn = (union mips_instruction)(mminsn.next_insn);
  674. /* Parse instruction to find what to do */
  675. switch (insn.mm_i_format.opcode) {
  676. case mm_pool32a_op:
  677. switch (insn.mm_x_format.func) {
  678. case mm_lwxs_op:
  679. reg = insn.mm_x_format.rd;
  680. goto loadW;
  681. }
  682. goto sigbus;
  683. case mm_pool32b_op:
  684. switch (insn.mm_m_format.func) {
  685. case mm_lwp_func:
  686. reg = insn.mm_m_format.rd;
  687. if (reg == 31)
  688. goto sigbus;
  689. if (!access_ok(VERIFY_READ, addr, 8))
  690. goto sigbus;
  691. LoadW(addr, value, res);
  692. if (res)
  693. goto fault;
  694. regs->regs[reg] = value;
  695. addr += 4;
  696. LoadW(addr, value, res);
  697. if (res)
  698. goto fault;
  699. regs->regs[reg + 1] = value;
  700. goto success;
  701. case mm_swp_func:
  702. reg = insn.mm_m_format.rd;
  703. if (reg == 31)
  704. goto sigbus;
  705. if (!access_ok(VERIFY_WRITE, addr, 8))
  706. goto sigbus;
  707. value = regs->regs[reg];
  708. StoreW(addr, value, res);
  709. if (res)
  710. goto fault;
  711. addr += 4;
  712. value = regs->regs[reg + 1];
  713. StoreW(addr, value, res);
  714. if (res)
  715. goto fault;
  716. goto success;
  717. case mm_ldp_func:
  718. #ifdef CONFIG_64BIT
  719. reg = insn.mm_m_format.rd;
  720. if (reg == 31)
  721. goto sigbus;
  722. if (!access_ok(VERIFY_READ, addr, 16))
  723. goto sigbus;
  724. LoadDW(addr, value, res);
  725. if (res)
  726. goto fault;
  727. regs->regs[reg] = value;
  728. addr += 8;
  729. LoadDW(addr, value, res);
  730. if (res)
  731. goto fault;
  732. regs->regs[reg + 1] = value;
  733. goto success;
  734. #endif /* CONFIG_64BIT */
  735. goto sigill;
  736. case mm_sdp_func:
  737. #ifdef CONFIG_64BIT
  738. reg = insn.mm_m_format.rd;
  739. if (reg == 31)
  740. goto sigbus;
  741. if (!access_ok(VERIFY_WRITE, addr, 16))
  742. goto sigbus;
  743. value = regs->regs[reg];
  744. StoreDW(addr, value, res);
  745. if (res)
  746. goto fault;
  747. addr += 8;
  748. value = regs->regs[reg + 1];
  749. StoreDW(addr, value, res);
  750. if (res)
  751. goto fault;
  752. goto success;
  753. #endif /* CONFIG_64BIT */
  754. goto sigill;
  755. case mm_lwm32_func:
  756. reg = insn.mm_m_format.rd;
  757. rvar = reg & 0xf;
  758. if ((rvar > 9) || !reg)
  759. goto sigill;
  760. if (reg & 0x10) {
  761. if (!access_ok
  762. (VERIFY_READ, addr, 4 * (rvar + 1)))
  763. goto sigbus;
  764. } else {
  765. if (!access_ok(VERIFY_READ, addr, 4 * rvar))
  766. goto sigbus;
  767. }
  768. if (rvar == 9)
  769. rvar = 8;
  770. for (i = 16; rvar; rvar--, i++) {
  771. LoadW(addr, value, res);
  772. if (res)
  773. goto fault;
  774. addr += 4;
  775. regs->regs[i] = value;
  776. }
  777. if ((reg & 0xf) == 9) {
  778. LoadW(addr, value, res);
  779. if (res)
  780. goto fault;
  781. addr += 4;
  782. regs->regs[30] = value;
  783. }
  784. if (reg & 0x10) {
  785. LoadW(addr, value, res);
  786. if (res)
  787. goto fault;
  788. regs->regs[31] = value;
  789. }
  790. goto success;
  791. case mm_swm32_func:
  792. reg = insn.mm_m_format.rd;
  793. rvar = reg & 0xf;
  794. if ((rvar > 9) || !reg)
  795. goto sigill;
  796. if (reg & 0x10) {
  797. if (!access_ok
  798. (VERIFY_WRITE, addr, 4 * (rvar + 1)))
  799. goto sigbus;
  800. } else {
  801. if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
  802. goto sigbus;
  803. }
  804. if (rvar == 9)
  805. rvar = 8;
  806. for (i = 16; rvar; rvar--, i++) {
  807. value = regs->regs[i];
  808. StoreW(addr, value, res);
  809. if (res)
  810. goto fault;
  811. addr += 4;
  812. }
  813. if ((reg & 0xf) == 9) {
  814. value = regs->regs[30];
  815. StoreW(addr, value, res);
  816. if (res)
  817. goto fault;
  818. addr += 4;
  819. }
  820. if (reg & 0x10) {
  821. value = regs->regs[31];
  822. StoreW(addr, value, res);
  823. if (res)
  824. goto fault;
  825. }
  826. goto success;
  827. case mm_ldm_func:
  828. #ifdef CONFIG_64BIT
  829. reg = insn.mm_m_format.rd;
  830. rvar = reg & 0xf;
  831. if ((rvar > 9) || !reg)
  832. goto sigill;
  833. if (reg & 0x10) {
  834. if (!access_ok
  835. (VERIFY_READ, addr, 8 * (rvar + 1)))
  836. goto sigbus;
  837. } else {
  838. if (!access_ok(VERIFY_READ, addr, 8 * rvar))
  839. goto sigbus;
  840. }
  841. if (rvar == 9)
  842. rvar = 8;
  843. for (i = 16; rvar; rvar--, i++) {
  844. LoadDW(addr, value, res);
  845. if (res)
  846. goto fault;
  847. addr += 4;
  848. regs->regs[i] = value;
  849. }
  850. if ((reg & 0xf) == 9) {
  851. LoadDW(addr, value, res);
  852. if (res)
  853. goto fault;
  854. addr += 8;
  855. regs->regs[30] = value;
  856. }
  857. if (reg & 0x10) {
  858. LoadDW(addr, value, res);
  859. if (res)
  860. goto fault;
  861. regs->regs[31] = value;
  862. }
  863. goto success;
  864. #endif /* CONFIG_64BIT */
  865. goto sigill;
  866. case mm_sdm_func:
  867. #ifdef CONFIG_64BIT
  868. reg = insn.mm_m_format.rd;
  869. rvar = reg & 0xf;
  870. if ((rvar > 9) || !reg)
  871. goto sigill;
  872. if (reg & 0x10) {
  873. if (!access_ok
  874. (VERIFY_WRITE, addr, 8 * (rvar + 1)))
  875. goto sigbus;
  876. } else {
  877. if (!access_ok(VERIFY_WRITE, addr, 8 * rvar))
  878. goto sigbus;
  879. }
  880. if (rvar == 9)
  881. rvar = 8;
  882. for (i = 16; rvar; rvar--, i++) {
  883. value = regs->regs[i];
  884. StoreDW(addr, value, res);
  885. if (res)
  886. goto fault;
  887. addr += 8;
  888. }
  889. if ((reg & 0xf) == 9) {
  890. value = regs->regs[30];
  891. StoreDW(addr, value, res);
  892. if (res)
  893. goto fault;
  894. addr += 8;
  895. }
  896. if (reg & 0x10) {
  897. value = regs->regs[31];
  898. StoreDW(addr, value, res);
  899. if (res)
  900. goto fault;
  901. }
  902. goto success;
  903. #endif /* CONFIG_64BIT */
  904. goto sigill;
  905. /* LWC2, SWC2, LDC2, SDC2 are not serviced */
  906. }
  907. goto sigbus;
  908. case mm_pool32c_op:
  909. switch (insn.mm_m_format.func) {
  910. case mm_lwu_func:
  911. reg = insn.mm_m_format.rd;
  912. goto loadWU;
  913. }
  914. /* LL,SC,LLD,SCD are not serviced */
  915. goto sigbus;
  916. case mm_pool32f_op:
  917. switch (insn.mm_x_format.func) {
  918. case mm_lwxc1_func:
  919. case mm_swxc1_func:
  920. case mm_ldxc1_func:
  921. case mm_sdxc1_func:
  922. goto fpu_emul;
  923. }
  924. goto sigbus;
  925. case mm_ldc132_op:
  926. case mm_sdc132_op:
  927. case mm_lwc132_op:
  928. case mm_swc132_op:
  929. fpu_emul:
  930. /* roll back jump/branch */
  931. regs->cp0_epc = origpc;
  932. regs->regs[31] = orig31;
  933. die_if_kernel("Unaligned FP access in kernel code", regs);
  934. BUG_ON(!used_math());
  935. BUG_ON(!is_fpu_owner());
  936. lose_fpu(1); /* save the FPU state for the emulator */
  937. res = fpu_emulator_cop1Handler(regs, &current->thread.fpu, 1,
  938. &fault_addr);
  939. own_fpu(1); /* restore FPU state */
  940. /* If something went wrong, signal */
  941. process_fpemu_return(res, fault_addr);
  942. if (res == 0)
  943. goto success;
  944. return;
  945. case mm_lh32_op:
  946. reg = insn.mm_i_format.rt;
  947. goto loadHW;
  948. case mm_lhu32_op:
  949. reg = insn.mm_i_format.rt;
  950. goto loadHWU;
  951. case mm_lw32_op:
  952. reg = insn.mm_i_format.rt;
  953. goto loadW;
  954. case mm_sh32_op:
  955. reg = insn.mm_i_format.rt;
  956. goto storeHW;
  957. case mm_sw32_op:
  958. reg = insn.mm_i_format.rt;
  959. goto storeW;
  960. case mm_ld32_op:
  961. reg = insn.mm_i_format.rt;
  962. goto loadDW;
  963. case mm_sd32_op:
  964. reg = insn.mm_i_format.rt;
  965. goto storeDW;
  966. case mm_pool16c_op:
  967. switch (insn.mm16_m_format.func) {
  968. case mm_lwm16_op:
  969. reg = insn.mm16_m_format.rlist;
  970. rvar = reg + 1;
  971. if (!access_ok(VERIFY_READ, addr, 4 * rvar))
  972. goto sigbus;
  973. for (i = 16; rvar; rvar--, i++) {
  974. LoadW(addr, value, res);
  975. if (res)
  976. goto fault;
  977. addr += 4;
  978. regs->regs[i] = value;
  979. }
  980. LoadW(addr, value, res);
  981. if (res)
  982. goto fault;
  983. regs->regs[31] = value;
  984. goto success;
  985. case mm_swm16_op:
  986. reg = insn.mm16_m_format.rlist;
  987. rvar = reg + 1;
  988. if (!access_ok(VERIFY_WRITE, addr, 4 * rvar))
  989. goto sigbus;
  990. for (i = 16; rvar; rvar--, i++) {
  991. value = regs->regs[i];
  992. StoreW(addr, value, res);
  993. if (res)
  994. goto fault;
  995. addr += 4;
  996. }
  997. value = regs->regs[31];
  998. StoreW(addr, value, res);
  999. if (res)
  1000. goto fault;
  1001. goto success;
  1002. }
  1003. goto sigbus;
  1004. case mm_lhu16_op:
  1005. reg = reg16to32[insn.mm16_rb_format.rt];
  1006. goto loadHWU;
  1007. case mm_lw16_op:
  1008. reg = reg16to32[insn.mm16_rb_format.rt];
  1009. goto loadW;
  1010. case mm_sh16_op:
  1011. reg = reg16to32st[insn.mm16_rb_format.rt];
  1012. goto storeHW;
  1013. case mm_sw16_op:
  1014. reg = reg16to32st[insn.mm16_rb_format.rt];
  1015. goto storeW;
  1016. case mm_lwsp16_op:
  1017. reg = insn.mm16_r5_format.rt;
  1018. goto loadW;
  1019. case mm_swsp16_op:
  1020. reg = insn.mm16_r5_format.rt;
  1021. goto storeW;
  1022. case mm_lwgp16_op:
  1023. reg = reg16to32[insn.mm16_r3_format.rt];
  1024. goto loadW;
  1025. default:
  1026. goto sigill;
  1027. }
  1028. loadHW:
  1029. if (!access_ok(VERIFY_READ, addr, 2))
  1030. goto sigbus;
  1031. LoadHW(addr, value, res);
  1032. if (res)
  1033. goto fault;
  1034. regs->regs[reg] = value;
  1035. goto success;
  1036. loadHWU:
  1037. if (!access_ok(VERIFY_READ, addr, 2))
  1038. goto sigbus;
  1039. LoadHWU(addr, value, res);
  1040. if (res)
  1041. goto fault;
  1042. regs->regs[reg] = value;
  1043. goto success;
  1044. loadW:
  1045. if (!access_ok(VERIFY_READ, addr, 4))
  1046. goto sigbus;
  1047. LoadW(addr, value, res);
  1048. if (res)
  1049. goto fault;
  1050. regs->regs[reg] = value;
  1051. goto success;
  1052. loadWU:
  1053. #ifdef CONFIG_64BIT
  1054. /*
  1055. * A 32-bit kernel might be running on a 64-bit processor. But
  1056. * if we're on a 32-bit processor and an i-cache incoherency
  1057. * or race makes us see a 64-bit instruction here the sdl/sdr
  1058. * would blow up, so for now we don't handle unaligned 64-bit
  1059. * instructions on 32-bit kernels.
  1060. */
  1061. if (!access_ok(VERIFY_READ, addr, 4))
  1062. goto sigbus;
  1063. LoadWU(addr, value, res);
  1064. if (res)
  1065. goto fault;
  1066. regs->regs[reg] = value;
  1067. goto success;
  1068. #endif /* CONFIG_64BIT */
  1069. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1070. goto sigill;
  1071. loadDW:
  1072. #ifdef CONFIG_64BIT
  1073. /*
  1074. * A 32-bit kernel might be running on a 64-bit processor. But
  1075. * if we're on a 32-bit processor and an i-cache incoherency
  1076. * or race makes us see a 64-bit instruction here the sdl/sdr
  1077. * would blow up, so for now we don't handle unaligned 64-bit
  1078. * instructions on 32-bit kernels.
  1079. */
  1080. if (!access_ok(VERIFY_READ, addr, 8))
  1081. goto sigbus;
  1082. LoadDW(addr, value, res);
  1083. if (res)
  1084. goto fault;
  1085. regs->regs[reg] = value;
  1086. goto success;
  1087. #endif /* CONFIG_64BIT */
  1088. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1089. goto sigill;
  1090. storeHW:
  1091. if (!access_ok(VERIFY_WRITE, addr, 2))
  1092. goto sigbus;
  1093. value = regs->regs[reg];
  1094. StoreHW(addr, value, res);
  1095. if (res)
  1096. goto fault;
  1097. goto success;
  1098. storeW:
  1099. if (!access_ok(VERIFY_WRITE, addr, 4))
  1100. goto sigbus;
  1101. value = regs->regs[reg];
  1102. StoreW(addr, value, res);
  1103. if (res)
  1104. goto fault;
  1105. goto success;
  1106. storeDW:
  1107. #ifdef CONFIG_64BIT
  1108. /*
  1109. * A 32-bit kernel might be running on a 64-bit processor. But
  1110. * if we're on a 32-bit processor and an i-cache incoherency
  1111. * or race makes us see a 64-bit instruction here the sdl/sdr
  1112. * would blow up, so for now we don't handle unaligned 64-bit
  1113. * instructions on 32-bit kernels.
  1114. */
  1115. if (!access_ok(VERIFY_WRITE, addr, 8))
  1116. goto sigbus;
  1117. value = regs->regs[reg];
  1118. StoreDW(addr, value, res);
  1119. if (res)
  1120. goto fault;
  1121. goto success;
  1122. #endif /* CONFIG_64BIT */
  1123. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1124. goto sigill;
  1125. success:
  1126. regs->cp0_epc = contpc; /* advance or branch */
  1127. #ifdef CONFIG_DEBUG_FS
  1128. unaligned_instructions++;
  1129. #endif
  1130. return;
  1131. fault:
  1132. /* roll back jump/branch */
  1133. regs->cp0_epc = origpc;
  1134. regs->regs[31] = orig31;
  1135. /* Did we have an exception handler installed? */
  1136. if (fixup_exception(regs))
  1137. return;
  1138. die_if_kernel("Unhandled kernel unaligned access", regs);
  1139. force_sig(SIGSEGV, current);
  1140. return;
  1141. sigbus:
  1142. die_if_kernel("Unhandled kernel unaligned access", regs);
  1143. force_sig(SIGBUS, current);
  1144. return;
  1145. sigill:
  1146. die_if_kernel
  1147. ("Unhandled kernel unaligned access or invalid instruction", regs);
  1148. force_sig(SIGILL, current);
  1149. }
  1150. static void emulate_load_store_MIPS16e(struct pt_regs *regs, void __user * addr)
  1151. {
  1152. unsigned long value;
  1153. unsigned int res;
  1154. int reg;
  1155. unsigned long orig31;
  1156. u16 __user *pc16;
  1157. unsigned long origpc;
  1158. union mips16e_instruction mips16inst, oldinst;
  1159. origpc = regs->cp0_epc;
  1160. orig31 = regs->regs[31];
  1161. pc16 = (unsigned short __user *)msk_isa16_mode(origpc);
  1162. /*
  1163. * This load never faults.
  1164. */
  1165. __get_user(mips16inst.full, pc16);
  1166. oldinst = mips16inst;
  1167. /* skip EXTEND instruction */
  1168. if (mips16inst.ri.opcode == MIPS16e_extend_op) {
  1169. pc16++;
  1170. __get_user(mips16inst.full, pc16);
  1171. } else if (delay_slot(regs)) {
  1172. /* skip jump instructions */
  1173. /* JAL/JALX are 32 bits but have OPCODE in first short int */
  1174. if (mips16inst.ri.opcode == MIPS16e_jal_op)
  1175. pc16++;
  1176. pc16++;
  1177. if (get_user(mips16inst.full, pc16))
  1178. goto sigbus;
  1179. }
  1180. switch (mips16inst.ri.opcode) {
  1181. case MIPS16e_i64_op: /* I64 or RI64 instruction */
  1182. switch (mips16inst.i64.func) { /* I64/RI64 func field check */
  1183. case MIPS16e_ldpc_func:
  1184. case MIPS16e_ldsp_func:
  1185. reg = reg16to32[mips16inst.ri64.ry];
  1186. goto loadDW;
  1187. case MIPS16e_sdsp_func:
  1188. reg = reg16to32[mips16inst.ri64.ry];
  1189. goto writeDW;
  1190. case MIPS16e_sdrasp_func:
  1191. reg = 29; /* GPRSP */
  1192. goto writeDW;
  1193. }
  1194. goto sigbus;
  1195. case MIPS16e_swsp_op:
  1196. case MIPS16e_lwpc_op:
  1197. case MIPS16e_lwsp_op:
  1198. reg = reg16to32[mips16inst.ri.rx];
  1199. break;
  1200. case MIPS16e_i8_op:
  1201. if (mips16inst.i8.func != MIPS16e_swrasp_func)
  1202. goto sigbus;
  1203. reg = 29; /* GPRSP */
  1204. break;
  1205. default:
  1206. reg = reg16to32[mips16inst.rri.ry];
  1207. break;
  1208. }
  1209. switch (mips16inst.ri.opcode) {
  1210. case MIPS16e_lb_op:
  1211. case MIPS16e_lbu_op:
  1212. case MIPS16e_sb_op:
  1213. goto sigbus;
  1214. case MIPS16e_lh_op:
  1215. if (!access_ok(VERIFY_READ, addr, 2))
  1216. goto sigbus;
  1217. LoadHW(addr, value, res);
  1218. if (res)
  1219. goto fault;
  1220. MIPS16e_compute_return_epc(regs, &oldinst);
  1221. regs->regs[reg] = value;
  1222. break;
  1223. case MIPS16e_lhu_op:
  1224. if (!access_ok(VERIFY_READ, addr, 2))
  1225. goto sigbus;
  1226. LoadHWU(addr, value, res);
  1227. if (res)
  1228. goto fault;
  1229. MIPS16e_compute_return_epc(regs, &oldinst);
  1230. regs->regs[reg] = value;
  1231. break;
  1232. case MIPS16e_lw_op:
  1233. case MIPS16e_lwpc_op:
  1234. case MIPS16e_lwsp_op:
  1235. if (!access_ok(VERIFY_READ, addr, 4))
  1236. goto sigbus;
  1237. LoadW(addr, value, res);
  1238. if (res)
  1239. goto fault;
  1240. MIPS16e_compute_return_epc(regs, &oldinst);
  1241. regs->regs[reg] = value;
  1242. break;
  1243. case MIPS16e_lwu_op:
  1244. #ifdef CONFIG_64BIT
  1245. /*
  1246. * A 32-bit kernel might be running on a 64-bit processor. But
  1247. * if we're on a 32-bit processor and an i-cache incoherency
  1248. * or race makes us see a 64-bit instruction here the sdl/sdr
  1249. * would blow up, so for now we don't handle unaligned 64-bit
  1250. * instructions on 32-bit kernels.
  1251. */
  1252. if (!access_ok(VERIFY_READ, addr, 4))
  1253. goto sigbus;
  1254. LoadWU(addr, value, res);
  1255. if (res)
  1256. goto fault;
  1257. MIPS16e_compute_return_epc(regs, &oldinst);
  1258. regs->regs[reg] = value;
  1259. break;
  1260. #endif /* CONFIG_64BIT */
  1261. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1262. goto sigill;
  1263. case MIPS16e_ld_op:
  1264. loadDW:
  1265. #ifdef CONFIG_64BIT
  1266. /*
  1267. * A 32-bit kernel might be running on a 64-bit processor. But
  1268. * if we're on a 32-bit processor and an i-cache incoherency
  1269. * or race makes us see a 64-bit instruction here the sdl/sdr
  1270. * would blow up, so for now we don't handle unaligned 64-bit
  1271. * instructions on 32-bit kernels.
  1272. */
  1273. if (!access_ok(VERIFY_READ, addr, 8))
  1274. goto sigbus;
  1275. LoadDW(addr, value, res);
  1276. if (res)
  1277. goto fault;
  1278. MIPS16e_compute_return_epc(regs, &oldinst);
  1279. regs->regs[reg] = value;
  1280. break;
  1281. #endif /* CONFIG_64BIT */
  1282. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1283. goto sigill;
  1284. case MIPS16e_sh_op:
  1285. if (!access_ok(VERIFY_WRITE, addr, 2))
  1286. goto sigbus;
  1287. MIPS16e_compute_return_epc(regs, &oldinst);
  1288. value = regs->regs[reg];
  1289. StoreHW(addr, value, res);
  1290. if (res)
  1291. goto fault;
  1292. break;
  1293. case MIPS16e_sw_op:
  1294. case MIPS16e_swsp_op:
  1295. case MIPS16e_i8_op: /* actually - MIPS16e_swrasp_func */
  1296. if (!access_ok(VERIFY_WRITE, addr, 4))
  1297. goto sigbus;
  1298. MIPS16e_compute_return_epc(regs, &oldinst);
  1299. value = regs->regs[reg];
  1300. StoreW(addr, value, res);
  1301. if (res)
  1302. goto fault;
  1303. break;
  1304. case MIPS16e_sd_op:
  1305. writeDW:
  1306. #ifdef CONFIG_64BIT
  1307. /*
  1308. * A 32-bit kernel might be running on a 64-bit processor. But
  1309. * if we're on a 32-bit processor and an i-cache incoherency
  1310. * or race makes us see a 64-bit instruction here the sdl/sdr
  1311. * would blow up, so for now we don't handle unaligned 64-bit
  1312. * instructions on 32-bit kernels.
  1313. */
  1314. if (!access_ok(VERIFY_WRITE, addr, 8))
  1315. goto sigbus;
  1316. MIPS16e_compute_return_epc(regs, &oldinst);
  1317. value = regs->regs[reg];
  1318. StoreDW(addr, value, res);
  1319. if (res)
  1320. goto fault;
  1321. break;
  1322. #endif /* CONFIG_64BIT */
  1323. /* Cannot handle 64-bit instructions in 32-bit kernel */
  1324. goto sigill;
  1325. default:
  1326. /*
  1327. * Pheeee... We encountered an yet unknown instruction or
  1328. * cache coherence problem. Die sucker, die ...
  1329. */
  1330. goto sigill;
  1331. }
  1332. #ifdef CONFIG_DEBUG_FS
  1333. unaligned_instructions++;
  1334. #endif
  1335. return;
  1336. fault:
  1337. /* roll back jump/branch */
  1338. regs->cp0_epc = origpc;
  1339. regs->regs[31] = orig31;
  1340. /* Did we have an exception handler installed? */
  1341. if (fixup_exception(regs))
  1342. return;
  1343. die_if_kernel("Unhandled kernel unaligned access", regs);
  1344. force_sig(SIGSEGV, current);
  1345. return;
  1346. sigbus:
  1347. die_if_kernel("Unhandled kernel unaligned access", regs);
  1348. force_sig(SIGBUS, current);
  1349. return;
  1350. sigill:
  1351. die_if_kernel
  1352. ("Unhandled kernel unaligned access or invalid instruction", regs);
  1353. force_sig(SIGILL, current);
  1354. }
  1355. asmlinkage void do_ade(struct pt_regs *regs)
  1356. {
  1357. enum ctx_state prev_state;
  1358. unsigned int __user *pc;
  1359. mm_segment_t seg;
  1360. prev_state = exception_enter();
  1361. perf_sw_event(PERF_COUNT_SW_ALIGNMENT_FAULTS,
  1362. 1, regs, regs->cp0_badvaddr);
  1363. /*
  1364. * Did we catch a fault trying to load an instruction?
  1365. */
  1366. if (regs->cp0_badvaddr == regs->cp0_epc)
  1367. goto sigbus;
  1368. if (user_mode(regs) && !test_thread_flag(TIF_FIXADE))
  1369. goto sigbus;
  1370. if (unaligned_action == UNALIGNED_ACTION_SIGNAL)
  1371. goto sigbus;
  1372. /*
  1373. * Do branch emulation only if we didn't forward the exception.
  1374. * This is all so but ugly ...
  1375. */
  1376. /*
  1377. * Are we running in microMIPS mode?
  1378. */
  1379. if (get_isa16_mode(regs->cp0_epc)) {
  1380. /*
  1381. * Did we catch a fault trying to load an instruction in
  1382. * 16-bit mode?
  1383. */
  1384. if (regs->cp0_badvaddr == msk_isa16_mode(regs->cp0_epc))
  1385. goto sigbus;
  1386. if (unaligned_action == UNALIGNED_ACTION_SHOW)
  1387. show_registers(regs);
  1388. if (cpu_has_mmips) {
  1389. seg = get_fs();
  1390. if (!user_mode(regs))
  1391. set_fs(KERNEL_DS);
  1392. emulate_load_store_microMIPS(regs,
  1393. (void __user *)regs->cp0_badvaddr);
  1394. set_fs(seg);
  1395. return;
  1396. }
  1397. if (cpu_has_mips16) {
  1398. seg = get_fs();
  1399. if (!user_mode(regs))
  1400. set_fs(KERNEL_DS);
  1401. emulate_load_store_MIPS16e(regs,
  1402. (void __user *)regs->cp0_badvaddr);
  1403. set_fs(seg);
  1404. return;
  1405. }
  1406. goto sigbus;
  1407. }
  1408. if (unaligned_action == UNALIGNED_ACTION_SHOW)
  1409. show_registers(regs);
  1410. pc = (unsigned int __user *)exception_epc(regs);
  1411. seg = get_fs();
  1412. if (!user_mode(regs))
  1413. set_fs(KERNEL_DS);
  1414. emulate_load_store_insn(regs, (void __user *)regs->cp0_badvaddr, pc);
  1415. set_fs(seg);
  1416. return;
  1417. sigbus:
  1418. die_if_kernel("Kernel unaligned instruction access", regs);
  1419. force_sig(SIGBUS, current);
  1420. /*
  1421. * XXX On return from the signal handler we should advance the epc
  1422. */
  1423. exception_exit(prev_state);
  1424. }
  1425. #ifdef CONFIG_DEBUG_FS
  1426. extern struct dentry *mips_debugfs_dir;
  1427. static int __init debugfs_unaligned(void)
  1428. {
  1429. struct dentry *d;
  1430. if (!mips_debugfs_dir)
  1431. return -ENODEV;
  1432. d = debugfs_create_u32("unaligned_instructions", S_IRUGO,
  1433. mips_debugfs_dir, &unaligned_instructions);
  1434. if (!d)
  1435. return -ENOMEM;
  1436. d = debugfs_create_u32("unaligned_action", S_IRUGO | S_IWUSR,
  1437. mips_debugfs_dir, &unaligned_action);
  1438. if (!d)
  1439. return -ENOMEM;
  1440. return 0;
  1441. }
  1442. __initcall(debugfs_unaligned);
  1443. #endif