smp-bmips.c 12 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
  7. *
  8. * SMP support for BMIPS
  9. */
  10. #include <linux/init.h>
  11. #include <linux/sched.h>
  12. #include <linux/mm.h>
  13. #include <linux/delay.h>
  14. #include <linux/smp.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/spinlock.h>
  17. #include <linux/cpu.h>
  18. #include <linux/cpumask.h>
  19. #include <linux/reboot.h>
  20. #include <linux/io.h>
  21. #include <linux/compiler.h>
  22. #include <linux/linkage.h>
  23. #include <linux/bug.h>
  24. #include <linux/kernel.h>
  25. #include <asm/time.h>
  26. #include <asm/pgtable.h>
  27. #include <asm/processor.h>
  28. #include <asm/bootinfo.h>
  29. #include <asm/pmon.h>
  30. #include <asm/cacheflush.h>
  31. #include <asm/tlbflush.h>
  32. #include <asm/mipsregs.h>
  33. #include <asm/bmips.h>
  34. #include <asm/traps.h>
  35. #include <asm/barrier.h>
  36. static int __maybe_unused max_cpus = 1;
  37. /* these may be configured by the platform code */
  38. int bmips_smp_enabled = 1;
  39. int bmips_cpu_offset;
  40. cpumask_t bmips_booted_mask;
  41. #ifdef CONFIG_SMP
  42. /* initial $sp, $gp - used by arch/mips/kernel/bmips_vec.S */
  43. unsigned long bmips_smp_boot_sp;
  44. unsigned long bmips_smp_boot_gp;
  45. static void bmips_send_ipi_single(int cpu, unsigned int action);
  46. static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id);
  47. /* SW interrupts 0,1 are used for interprocessor signaling */
  48. #define IPI0_IRQ (MIPS_CPU_IRQ_BASE + 0)
  49. #define IPI1_IRQ (MIPS_CPU_IRQ_BASE + 1)
  50. #define CPUNUM(cpu, shift) (((cpu) + bmips_cpu_offset) << (shift))
  51. #define ACTION_CLR_IPI(cpu, ipi) (0x2000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  52. #define ACTION_SET_IPI(cpu, ipi) (0x3000 | CPUNUM(cpu, 9) | ((ipi) << 8))
  53. #define ACTION_BOOT_THREAD(cpu) (0x08 | CPUNUM(cpu, 0))
  54. static void __init bmips_smp_setup(void)
  55. {
  56. int i, cpu = 1, boot_cpu = 0;
  57. #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
  58. /* arbitration priority */
  59. clear_c0_brcm_cmt_ctrl(0x30);
  60. /* NBK and weak order flags */
  61. set_c0_brcm_config_0(0x30000);
  62. /* Find out if we are running on TP0 or TP1 */
  63. boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  64. /*
  65. * MIPS interrupts 0,1 (SW INT 0,1) cross over to the other thread
  66. * MIPS interrupt 2 (HW INT 0) is the CPU0 L1 controller output
  67. * MIPS interrupt 3 (HW INT 1) is the CPU1 L1 controller output
  68. */
  69. change_c0_brcm_cmt_intr(0xf8018000,
  70. (0x02 << 27) | (0x03 << 15));
  71. /* single core, 2 threads (2 pipelines) */
  72. max_cpus = 2;
  73. #elif defined(CONFIG_CPU_BMIPS5000)
  74. /* enable raceless SW interrupts */
  75. set_c0_brcm_config(0x03 << 22);
  76. /* route HW interrupt 0 to CPU0, HW interrupt 1 to CPU1 */
  77. change_c0_brcm_mode(0x1f << 27, 0x02 << 27);
  78. /* N cores, 2 threads per core */
  79. max_cpus = (((read_c0_brcm_config() >> 6) & 0x03) + 1) << 1;
  80. /* clear any pending SW interrupts */
  81. for (i = 0; i < max_cpus; i++) {
  82. write_c0_brcm_action(ACTION_CLR_IPI(i, 0));
  83. write_c0_brcm_action(ACTION_CLR_IPI(i, 1));
  84. }
  85. #endif
  86. if (!bmips_smp_enabled)
  87. max_cpus = 1;
  88. /* this can be overridden by the BSP */
  89. if (!board_ebase_setup)
  90. board_ebase_setup = &bmips_ebase_setup;
  91. __cpu_number_map[boot_cpu] = 0;
  92. __cpu_logical_map[0] = boot_cpu;
  93. for (i = 0; i < max_cpus; i++) {
  94. if (i != boot_cpu) {
  95. __cpu_number_map[i] = cpu;
  96. __cpu_logical_map[cpu] = i;
  97. cpu++;
  98. }
  99. set_cpu_possible(i, 1);
  100. set_cpu_present(i, 1);
  101. }
  102. }
  103. /*
  104. * IPI IRQ setup - runs on CPU0
  105. */
  106. static void bmips_prepare_cpus(unsigned int max_cpus)
  107. {
  108. if (request_irq(IPI0_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
  109. "smp_ipi0", NULL))
  110. panic("Can't request IPI0 interrupt\n");
  111. if (request_irq(IPI1_IRQ, bmips_ipi_interrupt, IRQF_PERCPU,
  112. "smp_ipi1", NULL))
  113. panic("Can't request IPI1 interrupt\n");
  114. }
  115. /*
  116. * Tell the hardware to boot CPUx - runs on CPU0
  117. */
  118. static void bmips_boot_secondary(int cpu, struct task_struct *idle)
  119. {
  120. bmips_smp_boot_sp = __KSTK_TOS(idle);
  121. bmips_smp_boot_gp = (unsigned long)task_thread_info(idle);
  122. mb();
  123. /*
  124. * Initial boot sequence for secondary CPU:
  125. * bmips_reset_nmi_vec @ a000_0000 ->
  126. * bmips_smp_entry ->
  127. * plat_wired_tlb_setup (cached function call; optional) ->
  128. * start_secondary (cached jump)
  129. *
  130. * Warm restart sequence:
  131. * play_dead WAIT loop ->
  132. * bmips_smp_int_vec @ BMIPS_WARM_RESTART_VEC ->
  133. * eret to play_dead ->
  134. * bmips_secondary_reentry ->
  135. * start_secondary
  136. */
  137. pr_info("SMP: Booting CPU%d...\n", cpu);
  138. if (cpumask_test_cpu(cpu, &bmips_booted_mask))
  139. bmips_send_ipi_single(cpu, 0);
  140. else {
  141. #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
  142. /* Reset slave TP1 if booting from TP0 */
  143. if (cpu_logical_map(cpu) == 1)
  144. set_c0_brcm_cmt_ctrl(0x01);
  145. #elif defined(CONFIG_CPU_BMIPS5000)
  146. if (cpu & 0x01)
  147. write_c0_brcm_action(ACTION_BOOT_THREAD(cpu));
  148. else {
  149. /*
  150. * core N thread 0 was already booted; just
  151. * pulse the NMI line
  152. */
  153. bmips_write_zscm_reg(0x210, 0xc0000000);
  154. udelay(10);
  155. bmips_write_zscm_reg(0x210, 0x00);
  156. }
  157. #endif
  158. cpumask_set_cpu(cpu, &bmips_booted_mask);
  159. }
  160. }
  161. /*
  162. * Early setup - runs on secondary CPU after cache probe
  163. */
  164. static void bmips_init_secondary(void)
  165. {
  166. /* move NMI vector to kseg0, in case XKS01 is enabled */
  167. #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
  168. void __iomem *cbr = BMIPS_GET_CBR();
  169. unsigned long old_vec;
  170. unsigned long relo_vector;
  171. int boot_cpu;
  172. boot_cpu = !!(read_c0_brcm_cmt_local() & (1 << 31));
  173. relo_vector = boot_cpu ? BMIPS_RELO_VECTOR_CONTROL_0 :
  174. BMIPS_RELO_VECTOR_CONTROL_1;
  175. old_vec = __raw_readl(cbr + relo_vector);
  176. __raw_writel(old_vec & ~0x20000000, cbr + relo_vector);
  177. clear_c0_cause(smp_processor_id() ? C_SW1 : C_SW0);
  178. #elif defined(CONFIG_CPU_BMIPS5000)
  179. write_c0_brcm_bootvec(read_c0_brcm_bootvec() &
  180. (smp_processor_id() & 0x01 ? ~0x20000000 : ~0x2000));
  181. write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), 0));
  182. #endif
  183. }
  184. /*
  185. * Late setup - runs on secondary CPU before entering the idle loop
  186. */
  187. static void bmips_smp_finish(void)
  188. {
  189. pr_info("SMP: CPU%d is running\n", smp_processor_id());
  190. /* make sure there won't be a timer interrupt for a little while */
  191. write_c0_compare(read_c0_count() + mips_hpt_frequency / HZ);
  192. irq_enable_hazard();
  193. set_c0_status(IE_SW0 | IE_SW1 | IE_IRQ1 | IE_IRQ5 | ST0_IE);
  194. irq_enable_hazard();
  195. }
  196. /*
  197. * Runs on CPU0 after all CPUs have been booted
  198. */
  199. static void bmips_cpus_done(void)
  200. {
  201. }
  202. #if defined(CONFIG_CPU_BMIPS5000)
  203. /*
  204. * BMIPS5000 raceless IPIs
  205. *
  206. * Each CPU has two inbound SW IRQs which are independent of all other CPUs.
  207. * IPI0 is used for SMP_RESCHEDULE_YOURSELF
  208. * IPI1 is used for SMP_CALL_FUNCTION
  209. */
  210. static void bmips_send_ipi_single(int cpu, unsigned int action)
  211. {
  212. write_c0_brcm_action(ACTION_SET_IPI(cpu, action == SMP_CALL_FUNCTION));
  213. }
  214. static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
  215. {
  216. int action = irq - IPI0_IRQ;
  217. write_c0_brcm_action(ACTION_CLR_IPI(smp_processor_id(), action));
  218. if (action == 0)
  219. scheduler_ipi();
  220. else
  221. smp_call_function_interrupt();
  222. return IRQ_HANDLED;
  223. }
  224. #else
  225. /*
  226. * BMIPS43xx racey IPIs
  227. *
  228. * We use one inbound SW IRQ for each CPU.
  229. *
  230. * A spinlock must be held in order to keep CPUx from accidentally clearing
  231. * an incoming IPI when it writes CP0 CAUSE to raise an IPI on CPUy. The
  232. * same spinlock is used to protect the action masks.
  233. */
  234. static DEFINE_SPINLOCK(ipi_lock);
  235. static DEFINE_PER_CPU(int, ipi_action_mask);
  236. static void bmips_send_ipi_single(int cpu, unsigned int action)
  237. {
  238. unsigned long flags;
  239. spin_lock_irqsave(&ipi_lock, flags);
  240. set_c0_cause(cpu ? C_SW1 : C_SW0);
  241. per_cpu(ipi_action_mask, cpu) |= action;
  242. irq_enable_hazard();
  243. spin_unlock_irqrestore(&ipi_lock, flags);
  244. }
  245. static irqreturn_t bmips_ipi_interrupt(int irq, void *dev_id)
  246. {
  247. unsigned long flags;
  248. int action, cpu = irq - IPI0_IRQ;
  249. spin_lock_irqsave(&ipi_lock, flags);
  250. action = __get_cpu_var(ipi_action_mask);
  251. per_cpu(ipi_action_mask, cpu) = 0;
  252. clear_c0_cause(cpu ? C_SW1 : C_SW0);
  253. spin_unlock_irqrestore(&ipi_lock, flags);
  254. if (action & SMP_RESCHEDULE_YOURSELF)
  255. scheduler_ipi();
  256. if (action & SMP_CALL_FUNCTION)
  257. smp_call_function_interrupt();
  258. return IRQ_HANDLED;
  259. }
  260. #endif /* BMIPS type */
  261. static void bmips_send_ipi_mask(const struct cpumask *mask,
  262. unsigned int action)
  263. {
  264. unsigned int i;
  265. for_each_cpu(i, mask)
  266. bmips_send_ipi_single(i, action);
  267. }
  268. #ifdef CONFIG_HOTPLUG_CPU
  269. static int bmips_cpu_disable(void)
  270. {
  271. unsigned int cpu = smp_processor_id();
  272. if (cpu == 0)
  273. return -EBUSY;
  274. pr_info("SMP: CPU%d is offline\n", cpu);
  275. set_cpu_online(cpu, false);
  276. cpu_clear(cpu, cpu_callin_map);
  277. local_flush_tlb_all();
  278. local_flush_icache_range(0, ~0);
  279. return 0;
  280. }
  281. static void bmips_cpu_die(unsigned int cpu)
  282. {
  283. }
  284. void __ref play_dead(void)
  285. {
  286. idle_task_exit();
  287. /* flush data cache */
  288. _dma_cache_wback_inv(0, ~0);
  289. /*
  290. * Wakeup is on SW0 or SW1; disable everything else
  291. * Use BEV !IV (BMIPS_WARM_RESTART_VEC) to avoid the regular Linux
  292. * IRQ handlers; this clears ST0_IE and returns immediately.
  293. */
  294. clear_c0_cause(CAUSEF_IV | C_SW0 | C_SW1);
  295. change_c0_status(IE_IRQ5 | IE_IRQ1 | IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV,
  296. IE_SW0 | IE_SW1 | ST0_IE | ST0_BEV);
  297. irq_disable_hazard();
  298. /*
  299. * wait for SW interrupt from bmips_boot_secondary(), then jump
  300. * back to start_secondary()
  301. */
  302. __asm__ __volatile__(
  303. " wait\n"
  304. " j bmips_secondary_reentry\n"
  305. : : : "memory");
  306. }
  307. #endif /* CONFIG_HOTPLUG_CPU */
  308. struct plat_smp_ops bmips_smp_ops = {
  309. .smp_setup = bmips_smp_setup,
  310. .prepare_cpus = bmips_prepare_cpus,
  311. .boot_secondary = bmips_boot_secondary,
  312. .smp_finish = bmips_smp_finish,
  313. .init_secondary = bmips_init_secondary,
  314. .cpus_done = bmips_cpus_done,
  315. .send_ipi_single = bmips_send_ipi_single,
  316. .send_ipi_mask = bmips_send_ipi_mask,
  317. #ifdef CONFIG_HOTPLUG_CPU
  318. .cpu_disable = bmips_cpu_disable,
  319. .cpu_die = bmips_cpu_die,
  320. #endif
  321. };
  322. #endif /* CONFIG_SMP */
  323. /***********************************************************************
  324. * BMIPS vector relocation
  325. * This is primarily used for SMP boot, but it is applicable to some
  326. * UP BMIPS systems as well.
  327. ***********************************************************************/
  328. static void bmips_wr_vec(unsigned long dst, char *start, char *end)
  329. {
  330. memcpy((void *)dst, start, end - start);
  331. dma_cache_wback((unsigned long)start, end - start);
  332. local_flush_icache_range(dst, dst + (end - start));
  333. instruction_hazard();
  334. }
  335. static inline void bmips_nmi_handler_setup(void)
  336. {
  337. bmips_wr_vec(BMIPS_NMI_RESET_VEC, &bmips_reset_nmi_vec,
  338. &bmips_reset_nmi_vec_end);
  339. bmips_wr_vec(BMIPS_WARM_RESTART_VEC, &bmips_smp_int_vec,
  340. &bmips_smp_int_vec_end);
  341. }
  342. void bmips_ebase_setup(void)
  343. {
  344. unsigned long new_ebase = ebase;
  345. void __iomem __maybe_unused *cbr;
  346. BUG_ON(ebase != CKSEG0);
  347. #if defined(CONFIG_CPU_BMIPS4350)
  348. /*
  349. * BMIPS4350 cannot relocate the normal vectors, but it
  350. * can relocate the BEV=1 vectors. So CPU1 starts up at
  351. * the relocated BEV=1, IV=0 general exception vector @
  352. * 0xa000_0380.
  353. *
  354. * set_uncached_handler() is used here because:
  355. * - CPU1 will run this from uncached space
  356. * - None of the cacheflush functions are set up yet
  357. */
  358. set_uncached_handler(BMIPS_WARM_RESTART_VEC - CKSEG0,
  359. &bmips_smp_int_vec, 0x80);
  360. __sync();
  361. return;
  362. #elif defined(CONFIG_CPU_BMIPS4380)
  363. /*
  364. * 0x8000_0000: reset/NMI (initially in kseg1)
  365. * 0x8000_0400: normal vectors
  366. */
  367. new_ebase = 0x80000400;
  368. cbr = BMIPS_GET_CBR();
  369. __raw_writel(0x80080800, cbr + BMIPS_RELO_VECTOR_CONTROL_0);
  370. __raw_writel(0xa0080800, cbr + BMIPS_RELO_VECTOR_CONTROL_1);
  371. #elif defined(CONFIG_CPU_BMIPS5000)
  372. /*
  373. * 0x8000_0000: reset/NMI (initially in kseg1)
  374. * 0x8000_1000: normal vectors
  375. */
  376. new_ebase = 0x80001000;
  377. write_c0_brcm_bootvec(0xa0088008);
  378. write_c0_ebase(new_ebase);
  379. if (max_cpus > 2)
  380. bmips_write_zscm_reg(0xa0, 0xa008a008);
  381. #else
  382. return;
  383. #endif
  384. board_nmi_handler_setup = &bmips_nmi_handler_setup;
  385. ebase = new_ebase;
  386. }
  387. asmlinkage void __weak plat_wired_tlb_setup(void)
  388. {
  389. /*
  390. * Called when starting/restarting a secondary CPU.
  391. * Kernel stacks and other important data might only be accessible
  392. * once the wired entries are present.
  393. */
  394. }