r4k_switch.S 5.1 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
  7. * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  8. * Copyright (C) 1994, 1995, 1996, by Andreas Busse
  9. * Copyright (C) 1999 Silicon Graphics, Inc.
  10. * Copyright (C) 2000 MIPS Technologies, Inc.
  11. * written by Carsten Langgaard, carstenl@mips.com
  12. */
  13. #include <asm/asm.h>
  14. #include <asm/cachectl.h>
  15. #include <asm/fpregdef.h>
  16. #include <asm/mipsregs.h>
  17. #include <asm/asm-offsets.h>
  18. #include <asm/pgtable-bits.h>
  19. #include <asm/regdef.h>
  20. #include <asm/stackframe.h>
  21. #include <asm/thread_info.h>
  22. #include <asm/asmmacro.h>
  23. /*
  24. * Offset to the current process status flags, the first 32 bytes of the
  25. * stack are not used.
  26. */
  27. #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
  28. /*
  29. * FPU context is saved iff the process has used it's FPU in the current
  30. * time slice as indicated by _TIF_USEDFPU. In any case, the CU1 bit for user
  31. * space STATUS register should be 0, so that a process *always* starts its
  32. * userland with FPU disabled after each context switch.
  33. *
  34. * FPU will be enabled as soon as the process accesses FPU again, through
  35. * do_cpu() trap.
  36. */
  37. /*
  38. * task_struct *resume(task_struct *prev, task_struct *next,
  39. * struct thread_info *next_ti, int usedfpu)
  40. */
  41. .align 5
  42. LEAF(resume)
  43. mfc0 t1, CP0_STATUS
  44. LONG_S t1, THREAD_STATUS(a0)
  45. cpu_save_nonscratch a0
  46. LONG_S ra, THREAD_REG31(a0)
  47. /*
  48. * check if we need to save FPU registers
  49. */
  50. beqz a3, 1f
  51. PTR_L t3, TASK_THREAD_INFO(a0)
  52. /*
  53. * clear saved user stack CU1 bit
  54. */
  55. LONG_L t0, ST_OFF(t3)
  56. li t1, ~ST0_CU1
  57. and t0, t0, t1
  58. LONG_S t0, ST_OFF(t3)
  59. fpu_save_double a0 t0 t1 # c0_status passed in t0
  60. # clobbers t1
  61. 1:
  62. #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
  63. PTR_L t8, __stack_chk_guard
  64. LONG_L t9, TASK_STACK_CANARY(a1)
  65. LONG_S t9, 0(t8)
  66. #endif
  67. /*
  68. * The order of restoring the registers takes care of the race
  69. * updating $28, $29 and kernelsp without disabling ints.
  70. */
  71. move $28, a2
  72. cpu_restore_nonscratch a1
  73. PTR_ADDU t0, $28, _THREAD_SIZE - 32
  74. set_saved_sp t0, t1, t2
  75. #ifdef CONFIG_MIPS_MT_SMTC
  76. /* Read-modify-writes of Status must be atomic on a VPE */
  77. mfc0 t2, CP0_TCSTATUS
  78. ori t1, t2, TCSTATUS_IXMT
  79. mtc0 t1, CP0_TCSTATUS
  80. andi t2, t2, TCSTATUS_IXMT
  81. _ehb
  82. DMT 8 # dmt t0
  83. move t1,ra
  84. jal mips_ihb
  85. move ra,t1
  86. #endif /* CONFIG_MIPS_MT_SMTC */
  87. mfc0 t1, CP0_STATUS /* Do we really need this? */
  88. li a3, 0xff01
  89. and t1, a3
  90. LONG_L a2, THREAD_STATUS(a1)
  91. nor a3, $0, a3
  92. and a2, a3
  93. or a2, t1
  94. mtc0 a2, CP0_STATUS
  95. #ifdef CONFIG_MIPS_MT_SMTC
  96. _ehb
  97. andi t0, t0, VPECONTROL_TE
  98. beqz t0, 1f
  99. emt
  100. 1:
  101. mfc0 t1, CP0_TCSTATUS
  102. xori t1, t1, TCSTATUS_IXMT
  103. or t1, t1, t2
  104. mtc0 t1, CP0_TCSTATUS
  105. _ehb
  106. #endif /* CONFIG_MIPS_MT_SMTC */
  107. move v0, a0
  108. jr ra
  109. END(resume)
  110. /*
  111. * Save a thread's fp context.
  112. */
  113. LEAF(_save_fp)
  114. #ifdef CONFIG_64BIT
  115. mfc0 t0, CP0_STATUS
  116. #endif
  117. fpu_save_double a0 t0 t1 # clobbers t1
  118. jr ra
  119. END(_save_fp)
  120. /*
  121. * Restore a thread's fp context.
  122. */
  123. LEAF(_restore_fp)
  124. #ifdef CONFIG_64BIT
  125. mfc0 t0, CP0_STATUS
  126. #endif
  127. fpu_restore_double a0 t0 t1 # clobbers t1
  128. jr ra
  129. END(_restore_fp)
  130. /*
  131. * Load the FPU with signalling NANS. This bit pattern we're using has
  132. * the property that no matter whether considered as single or as double
  133. * precision represents signaling NANS.
  134. *
  135. * We initialize fcr31 to rounding to nearest, no exceptions.
  136. */
  137. #define FPU_DEFAULT 0x00000000
  138. LEAF(_init_fpu)
  139. #ifdef CONFIG_MIPS_MT_SMTC
  140. /* Rather than manipulate per-VPE Status, set per-TC bit in TCStatus */
  141. mfc0 t0, CP0_TCSTATUS
  142. /* Bit position is the same for Status, TCStatus */
  143. li t1, ST0_CU1
  144. or t0, t1
  145. mtc0 t0, CP0_TCSTATUS
  146. #else /* Normal MIPS CU1 enable */
  147. mfc0 t0, CP0_STATUS
  148. li t1, ST0_CU1
  149. or t0, t1
  150. mtc0 t0, CP0_STATUS
  151. #endif /* CONFIG_MIPS_MT_SMTC */
  152. enable_fpu_hazard
  153. li t1, FPU_DEFAULT
  154. ctc1 t1, fcr31
  155. li t1, -1 # SNaN
  156. #ifdef CONFIG_64BIT
  157. sll t0, t0, 5
  158. bgez t0, 1f # 16 / 32 register mode?
  159. dmtc1 t1, $f1
  160. dmtc1 t1, $f3
  161. dmtc1 t1, $f5
  162. dmtc1 t1, $f7
  163. dmtc1 t1, $f9
  164. dmtc1 t1, $f11
  165. dmtc1 t1, $f13
  166. dmtc1 t1, $f15
  167. dmtc1 t1, $f17
  168. dmtc1 t1, $f19
  169. dmtc1 t1, $f21
  170. dmtc1 t1, $f23
  171. dmtc1 t1, $f25
  172. dmtc1 t1, $f27
  173. dmtc1 t1, $f29
  174. dmtc1 t1, $f31
  175. 1:
  176. #endif
  177. #ifdef CONFIG_CPU_MIPS32
  178. mtc1 t1, $f0
  179. mtc1 t1, $f1
  180. mtc1 t1, $f2
  181. mtc1 t1, $f3
  182. mtc1 t1, $f4
  183. mtc1 t1, $f5
  184. mtc1 t1, $f6
  185. mtc1 t1, $f7
  186. mtc1 t1, $f8
  187. mtc1 t1, $f9
  188. mtc1 t1, $f10
  189. mtc1 t1, $f11
  190. mtc1 t1, $f12
  191. mtc1 t1, $f13
  192. mtc1 t1, $f14
  193. mtc1 t1, $f15
  194. mtc1 t1, $f16
  195. mtc1 t1, $f17
  196. mtc1 t1, $f18
  197. mtc1 t1, $f19
  198. mtc1 t1, $f20
  199. mtc1 t1, $f21
  200. mtc1 t1, $f22
  201. mtc1 t1, $f23
  202. mtc1 t1, $f24
  203. mtc1 t1, $f25
  204. mtc1 t1, $f26
  205. mtc1 t1, $f27
  206. mtc1 t1, $f28
  207. mtc1 t1, $f29
  208. mtc1 t1, $f30
  209. mtc1 t1, $f31
  210. #else
  211. .set mips3
  212. dmtc1 t1, $f0
  213. dmtc1 t1, $f2
  214. dmtc1 t1, $f4
  215. dmtc1 t1, $f6
  216. dmtc1 t1, $f8
  217. dmtc1 t1, $f10
  218. dmtc1 t1, $f12
  219. dmtc1 t1, $f14
  220. dmtc1 t1, $f16
  221. dmtc1 t1, $f18
  222. dmtc1 t1, $f20
  223. dmtc1 t1, $f22
  224. dmtc1 t1, $f24
  225. dmtc1 t1, $f26
  226. dmtc1 t1, $f28
  227. dmtc1 t1, $f30
  228. #endif
  229. jr ra
  230. END(_init_fpu)