octeon_switch.S 12 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 1995, 1996, 1998, 1999, 2002, 2003 Ralf Baechle
  7. * Copyright (C) 1996 David S. Miller (davem@davemloft.net)
  8. * Copyright (C) 1994, 1995, 1996, by Andreas Busse
  9. * Copyright (C) 1999 Silicon Graphics, Inc.
  10. * Copyright (C) 2000 MIPS Technologies, Inc.
  11. * written by Carsten Langgaard, carstenl@mips.com
  12. */
  13. #include <asm/asm.h>
  14. #include <asm/cachectl.h>
  15. #include <asm/fpregdef.h>
  16. #include <asm/mipsregs.h>
  17. #include <asm/asm-offsets.h>
  18. #include <asm/pgtable-bits.h>
  19. #include <asm/regdef.h>
  20. #include <asm/stackframe.h>
  21. #include <asm/thread_info.h>
  22. #include <asm/asmmacro.h>
  23. /*
  24. * Offset to the current process status flags, the first 32 bytes of the
  25. * stack are not used.
  26. */
  27. #define ST_OFF (_THREAD_SIZE - 32 - PT_SIZE + PT_STATUS)
  28. /*
  29. * task_struct *resume(task_struct *prev, task_struct *next,
  30. * struct thread_info *next_ti, int usedfpu)
  31. */
  32. .align 7
  33. LEAF(resume)
  34. .set arch=octeon
  35. mfc0 t1, CP0_STATUS
  36. LONG_S t1, THREAD_STATUS(a0)
  37. cpu_save_nonscratch a0
  38. LONG_S ra, THREAD_REG31(a0)
  39. #if CONFIG_CAVIUM_OCTEON_CVMSEG_SIZE > 0
  40. /* Check if we need to store CVMSEG state */
  41. mfc0 t0, $11,7 /* CvmMemCtl */
  42. bbit0 t0, 6, 3f /* Is user access enabled? */
  43. /* Store the CVMSEG state */
  44. /* Extract the size of CVMSEG */
  45. andi t0, 0x3f
  46. /* Multiply * (cache line size/sizeof(long)/2) */
  47. sll t0, 7-LONGLOG-1
  48. li t1, -32768 /* Base address of CVMSEG */
  49. LONG_ADDI t2, a0, THREAD_CVMSEG /* Where to store CVMSEG to */
  50. synciobdma
  51. 2:
  52. .set noreorder
  53. LONG_L t8, 0(t1) /* Load from CVMSEG */
  54. subu t0, 1 /* Decrement loop var */
  55. LONG_L t9, LONGSIZE(t1)/* Load from CVMSEG */
  56. LONG_ADDU t1, LONGSIZE*2 /* Increment loc in CVMSEG */
  57. LONG_S t8, 0(t2) /* Store CVMSEG to thread storage */
  58. LONG_ADDU t2, LONGSIZE*2 /* Increment loc in thread storage */
  59. bnez t0, 2b /* Loop until we've copied it all */
  60. LONG_S t9, -LONGSIZE(t2)/* Store CVMSEG to thread storage */
  61. .set reorder
  62. /* Disable access to CVMSEG */
  63. mfc0 t0, $11,7 /* CvmMemCtl */
  64. xori t0, t0, 0x40 /* Bit 6 is CVMSEG user enable */
  65. mtc0 t0, $11,7 /* CvmMemCtl */
  66. #endif
  67. 3:
  68. #if defined(CONFIG_CC_STACKPROTECTOR) && !defined(CONFIG_SMP)
  69. PTR_L t8, __stack_chk_guard
  70. LONG_L t9, TASK_STACK_CANARY(a1)
  71. LONG_S t9, 0(t8)
  72. #endif
  73. /*
  74. * The order of restoring the registers takes care of the race
  75. * updating $28, $29 and kernelsp without disabling ints.
  76. */
  77. move $28, a2
  78. cpu_restore_nonscratch a1
  79. #if (_THREAD_SIZE - 32) < 0x8000
  80. PTR_ADDIU t0, $28, _THREAD_SIZE - 32
  81. #else
  82. PTR_LI t0, _THREAD_SIZE - 32
  83. PTR_ADDU t0, $28
  84. #endif
  85. set_saved_sp t0, t1, t2
  86. mfc0 t1, CP0_STATUS /* Do we really need this? */
  87. li a3, 0xff01
  88. and t1, a3
  89. LONG_L a2, THREAD_STATUS(a1)
  90. nor a3, $0, a3
  91. and a2, a3
  92. or a2, t1
  93. mtc0 a2, CP0_STATUS
  94. move v0, a0
  95. jr ra
  96. END(resume)
  97. /*
  98. * void octeon_cop2_save(struct octeon_cop2_state *a0)
  99. */
  100. .align 7
  101. LEAF(octeon_cop2_save)
  102. dmfc0 t9, $9,7 /* CvmCtl register. */
  103. /* Save the COP2 CRC state */
  104. dmfc2 t0, 0x0201
  105. dmfc2 t1, 0x0202
  106. dmfc2 t2, 0x0200
  107. sd t0, OCTEON_CP2_CRC_IV(a0)
  108. sd t1, OCTEON_CP2_CRC_LENGTH(a0)
  109. sd t2, OCTEON_CP2_CRC_POLY(a0)
  110. /* Skip next instructions if CvmCtl[NODFA_CP2] set */
  111. bbit1 t9, 28, 1f
  112. /* Save the LLM state */
  113. dmfc2 t0, 0x0402
  114. dmfc2 t1, 0x040A
  115. sd t0, OCTEON_CP2_LLM_DAT(a0)
  116. sd t1, OCTEON_CP2_LLM_DAT+8(a0)
  117. 1: bbit1 t9, 26, 3f /* done if CvmCtl[NOCRYPTO] set */
  118. /* Save the COP2 crypto state */
  119. /* this part is mostly common to both pass 1 and later revisions */
  120. dmfc2 t0, 0x0084
  121. dmfc2 t1, 0x0080
  122. dmfc2 t2, 0x0081
  123. dmfc2 t3, 0x0082
  124. sd t0, OCTEON_CP2_3DES_IV(a0)
  125. dmfc2 t0, 0x0088
  126. sd t1, OCTEON_CP2_3DES_KEY(a0)
  127. dmfc2 t1, 0x0111 /* only necessary for pass 1 */
  128. sd t2, OCTEON_CP2_3DES_KEY+8(a0)
  129. dmfc2 t2, 0x0102
  130. sd t3, OCTEON_CP2_3DES_KEY+16(a0)
  131. dmfc2 t3, 0x0103
  132. sd t0, OCTEON_CP2_3DES_RESULT(a0)
  133. dmfc2 t0, 0x0104
  134. sd t1, OCTEON_CP2_AES_INP0(a0) /* only necessary for pass 1 */
  135. dmfc2 t1, 0x0105
  136. sd t2, OCTEON_CP2_AES_IV(a0)
  137. dmfc2 t2, 0x0106
  138. sd t3, OCTEON_CP2_AES_IV+8(a0)
  139. dmfc2 t3, 0x0107
  140. sd t0, OCTEON_CP2_AES_KEY(a0)
  141. dmfc2 t0, 0x0110
  142. sd t1, OCTEON_CP2_AES_KEY+8(a0)
  143. dmfc2 t1, 0x0100
  144. sd t2, OCTEON_CP2_AES_KEY+16(a0)
  145. dmfc2 t2, 0x0101
  146. sd t3, OCTEON_CP2_AES_KEY+24(a0)
  147. mfc0 t3, $15,0 /* Get the processor ID register */
  148. sd t0, OCTEON_CP2_AES_KEYLEN(a0)
  149. li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
  150. sd t1, OCTEON_CP2_AES_RESULT(a0)
  151. sd t2, OCTEON_CP2_AES_RESULT+8(a0)
  152. /* Skip to the Pass1 version of the remainder of the COP2 state */
  153. beq t3, t0, 2f
  154. /* the non-pass1 state when !CvmCtl[NOCRYPTO] */
  155. dmfc2 t1, 0x0240
  156. dmfc2 t2, 0x0241
  157. dmfc2 t3, 0x0242
  158. dmfc2 t0, 0x0243
  159. sd t1, OCTEON_CP2_HSH_DATW(a0)
  160. dmfc2 t1, 0x0244
  161. sd t2, OCTEON_CP2_HSH_DATW+8(a0)
  162. dmfc2 t2, 0x0245
  163. sd t3, OCTEON_CP2_HSH_DATW+16(a0)
  164. dmfc2 t3, 0x0246
  165. sd t0, OCTEON_CP2_HSH_DATW+24(a0)
  166. dmfc2 t0, 0x0247
  167. sd t1, OCTEON_CP2_HSH_DATW+32(a0)
  168. dmfc2 t1, 0x0248
  169. sd t2, OCTEON_CP2_HSH_DATW+40(a0)
  170. dmfc2 t2, 0x0249
  171. sd t3, OCTEON_CP2_HSH_DATW+48(a0)
  172. dmfc2 t3, 0x024A
  173. sd t0, OCTEON_CP2_HSH_DATW+56(a0)
  174. dmfc2 t0, 0x024B
  175. sd t1, OCTEON_CP2_HSH_DATW+64(a0)
  176. dmfc2 t1, 0x024C
  177. sd t2, OCTEON_CP2_HSH_DATW+72(a0)
  178. dmfc2 t2, 0x024D
  179. sd t3, OCTEON_CP2_HSH_DATW+80(a0)
  180. dmfc2 t3, 0x024E
  181. sd t0, OCTEON_CP2_HSH_DATW+88(a0)
  182. dmfc2 t0, 0x0250
  183. sd t1, OCTEON_CP2_HSH_DATW+96(a0)
  184. dmfc2 t1, 0x0251
  185. sd t2, OCTEON_CP2_HSH_DATW+104(a0)
  186. dmfc2 t2, 0x0252
  187. sd t3, OCTEON_CP2_HSH_DATW+112(a0)
  188. dmfc2 t3, 0x0253
  189. sd t0, OCTEON_CP2_HSH_IVW(a0)
  190. dmfc2 t0, 0x0254
  191. sd t1, OCTEON_CP2_HSH_IVW+8(a0)
  192. dmfc2 t1, 0x0255
  193. sd t2, OCTEON_CP2_HSH_IVW+16(a0)
  194. dmfc2 t2, 0x0256
  195. sd t3, OCTEON_CP2_HSH_IVW+24(a0)
  196. dmfc2 t3, 0x0257
  197. sd t0, OCTEON_CP2_HSH_IVW+32(a0)
  198. dmfc2 t0, 0x0258
  199. sd t1, OCTEON_CP2_HSH_IVW+40(a0)
  200. dmfc2 t1, 0x0259
  201. sd t2, OCTEON_CP2_HSH_IVW+48(a0)
  202. dmfc2 t2, 0x025E
  203. sd t3, OCTEON_CP2_HSH_IVW+56(a0)
  204. dmfc2 t3, 0x025A
  205. sd t0, OCTEON_CP2_GFM_MULT(a0)
  206. dmfc2 t0, 0x025B
  207. sd t1, OCTEON_CP2_GFM_MULT+8(a0)
  208. sd t2, OCTEON_CP2_GFM_POLY(a0)
  209. sd t3, OCTEON_CP2_GFM_RESULT(a0)
  210. sd t0, OCTEON_CP2_GFM_RESULT+8(a0)
  211. jr ra
  212. 2: /* pass 1 special stuff when !CvmCtl[NOCRYPTO] */
  213. dmfc2 t3, 0x0040
  214. dmfc2 t0, 0x0041
  215. dmfc2 t1, 0x0042
  216. dmfc2 t2, 0x0043
  217. sd t3, OCTEON_CP2_HSH_DATW(a0)
  218. dmfc2 t3, 0x0044
  219. sd t0, OCTEON_CP2_HSH_DATW+8(a0)
  220. dmfc2 t0, 0x0045
  221. sd t1, OCTEON_CP2_HSH_DATW+16(a0)
  222. dmfc2 t1, 0x0046
  223. sd t2, OCTEON_CP2_HSH_DATW+24(a0)
  224. dmfc2 t2, 0x0048
  225. sd t3, OCTEON_CP2_HSH_DATW+32(a0)
  226. dmfc2 t3, 0x0049
  227. sd t0, OCTEON_CP2_HSH_DATW+40(a0)
  228. dmfc2 t0, 0x004A
  229. sd t1, OCTEON_CP2_HSH_DATW+48(a0)
  230. sd t2, OCTEON_CP2_HSH_IVW(a0)
  231. sd t3, OCTEON_CP2_HSH_IVW+8(a0)
  232. sd t0, OCTEON_CP2_HSH_IVW+16(a0)
  233. 3: /* pass 1 or CvmCtl[NOCRYPTO] set */
  234. jr ra
  235. END(octeon_cop2_save)
  236. /*
  237. * void octeon_cop2_restore(struct octeon_cop2_state *a0)
  238. */
  239. .align 7
  240. .set push
  241. .set noreorder
  242. LEAF(octeon_cop2_restore)
  243. /* First cache line was prefetched before the call */
  244. pref 4, 128(a0)
  245. dmfc0 t9, $9,7 /* CvmCtl register. */
  246. pref 4, 256(a0)
  247. ld t0, OCTEON_CP2_CRC_IV(a0)
  248. pref 4, 384(a0)
  249. ld t1, OCTEON_CP2_CRC_LENGTH(a0)
  250. ld t2, OCTEON_CP2_CRC_POLY(a0)
  251. /* Restore the COP2 CRC state */
  252. dmtc2 t0, 0x0201
  253. dmtc2 t1, 0x1202
  254. bbit1 t9, 28, 2f /* Skip LLM if CvmCtl[NODFA_CP2] is set */
  255. dmtc2 t2, 0x4200
  256. /* Restore the LLM state */
  257. ld t0, OCTEON_CP2_LLM_DAT(a0)
  258. ld t1, OCTEON_CP2_LLM_DAT+8(a0)
  259. dmtc2 t0, 0x0402
  260. dmtc2 t1, 0x040A
  261. 2:
  262. bbit1 t9, 26, done_restore /* done if CvmCtl[NOCRYPTO] set */
  263. nop
  264. /* Restore the COP2 crypto state common to pass 1 and pass 2 */
  265. ld t0, OCTEON_CP2_3DES_IV(a0)
  266. ld t1, OCTEON_CP2_3DES_KEY(a0)
  267. ld t2, OCTEON_CP2_3DES_KEY+8(a0)
  268. dmtc2 t0, 0x0084
  269. ld t0, OCTEON_CP2_3DES_KEY+16(a0)
  270. dmtc2 t1, 0x0080
  271. ld t1, OCTEON_CP2_3DES_RESULT(a0)
  272. dmtc2 t2, 0x0081
  273. ld t2, OCTEON_CP2_AES_INP0(a0) /* only really needed for pass 1 */
  274. dmtc2 t0, 0x0082
  275. ld t0, OCTEON_CP2_AES_IV(a0)
  276. dmtc2 t1, 0x0098
  277. ld t1, OCTEON_CP2_AES_IV+8(a0)
  278. dmtc2 t2, 0x010A /* only really needed for pass 1 */
  279. ld t2, OCTEON_CP2_AES_KEY(a0)
  280. dmtc2 t0, 0x0102
  281. ld t0, OCTEON_CP2_AES_KEY+8(a0)
  282. dmtc2 t1, 0x0103
  283. ld t1, OCTEON_CP2_AES_KEY+16(a0)
  284. dmtc2 t2, 0x0104
  285. ld t2, OCTEON_CP2_AES_KEY+24(a0)
  286. dmtc2 t0, 0x0105
  287. ld t0, OCTEON_CP2_AES_KEYLEN(a0)
  288. dmtc2 t1, 0x0106
  289. ld t1, OCTEON_CP2_AES_RESULT(a0)
  290. dmtc2 t2, 0x0107
  291. ld t2, OCTEON_CP2_AES_RESULT+8(a0)
  292. mfc0 t3, $15,0 /* Get the processor ID register */
  293. dmtc2 t0, 0x0110
  294. li t0, 0x000d0000 /* This is the processor ID of Octeon Pass1 */
  295. dmtc2 t1, 0x0100
  296. bne t0, t3, 3f /* Skip the next stuff for non-pass1 */
  297. dmtc2 t2, 0x0101
  298. /* this code is specific for pass 1 */
  299. ld t0, OCTEON_CP2_HSH_DATW(a0)
  300. ld t1, OCTEON_CP2_HSH_DATW+8(a0)
  301. ld t2, OCTEON_CP2_HSH_DATW+16(a0)
  302. dmtc2 t0, 0x0040
  303. ld t0, OCTEON_CP2_HSH_DATW+24(a0)
  304. dmtc2 t1, 0x0041
  305. ld t1, OCTEON_CP2_HSH_DATW+32(a0)
  306. dmtc2 t2, 0x0042
  307. ld t2, OCTEON_CP2_HSH_DATW+40(a0)
  308. dmtc2 t0, 0x0043
  309. ld t0, OCTEON_CP2_HSH_DATW+48(a0)
  310. dmtc2 t1, 0x0044
  311. ld t1, OCTEON_CP2_HSH_IVW(a0)
  312. dmtc2 t2, 0x0045
  313. ld t2, OCTEON_CP2_HSH_IVW+8(a0)
  314. dmtc2 t0, 0x0046
  315. ld t0, OCTEON_CP2_HSH_IVW+16(a0)
  316. dmtc2 t1, 0x0048
  317. dmtc2 t2, 0x0049
  318. b done_restore /* unconditional branch */
  319. dmtc2 t0, 0x004A
  320. 3: /* this is post-pass1 code */
  321. ld t2, OCTEON_CP2_HSH_DATW(a0)
  322. ld t0, OCTEON_CP2_HSH_DATW+8(a0)
  323. ld t1, OCTEON_CP2_HSH_DATW+16(a0)
  324. dmtc2 t2, 0x0240
  325. ld t2, OCTEON_CP2_HSH_DATW+24(a0)
  326. dmtc2 t0, 0x0241
  327. ld t0, OCTEON_CP2_HSH_DATW+32(a0)
  328. dmtc2 t1, 0x0242
  329. ld t1, OCTEON_CP2_HSH_DATW+40(a0)
  330. dmtc2 t2, 0x0243
  331. ld t2, OCTEON_CP2_HSH_DATW+48(a0)
  332. dmtc2 t0, 0x0244
  333. ld t0, OCTEON_CP2_HSH_DATW+56(a0)
  334. dmtc2 t1, 0x0245
  335. ld t1, OCTEON_CP2_HSH_DATW+64(a0)
  336. dmtc2 t2, 0x0246
  337. ld t2, OCTEON_CP2_HSH_DATW+72(a0)
  338. dmtc2 t0, 0x0247
  339. ld t0, OCTEON_CP2_HSH_DATW+80(a0)
  340. dmtc2 t1, 0x0248
  341. ld t1, OCTEON_CP2_HSH_DATW+88(a0)
  342. dmtc2 t2, 0x0249
  343. ld t2, OCTEON_CP2_HSH_DATW+96(a0)
  344. dmtc2 t0, 0x024A
  345. ld t0, OCTEON_CP2_HSH_DATW+104(a0)
  346. dmtc2 t1, 0x024B
  347. ld t1, OCTEON_CP2_HSH_DATW+112(a0)
  348. dmtc2 t2, 0x024C
  349. ld t2, OCTEON_CP2_HSH_IVW(a0)
  350. dmtc2 t0, 0x024D
  351. ld t0, OCTEON_CP2_HSH_IVW+8(a0)
  352. dmtc2 t1, 0x024E
  353. ld t1, OCTEON_CP2_HSH_IVW+16(a0)
  354. dmtc2 t2, 0x0250
  355. ld t2, OCTEON_CP2_HSH_IVW+24(a0)
  356. dmtc2 t0, 0x0251
  357. ld t0, OCTEON_CP2_HSH_IVW+32(a0)
  358. dmtc2 t1, 0x0252
  359. ld t1, OCTEON_CP2_HSH_IVW+40(a0)
  360. dmtc2 t2, 0x0253
  361. ld t2, OCTEON_CP2_HSH_IVW+48(a0)
  362. dmtc2 t0, 0x0254
  363. ld t0, OCTEON_CP2_HSH_IVW+56(a0)
  364. dmtc2 t1, 0x0255
  365. ld t1, OCTEON_CP2_GFM_MULT(a0)
  366. dmtc2 t2, 0x0256
  367. ld t2, OCTEON_CP2_GFM_MULT+8(a0)
  368. dmtc2 t0, 0x0257
  369. ld t0, OCTEON_CP2_GFM_POLY(a0)
  370. dmtc2 t1, 0x0258
  371. ld t1, OCTEON_CP2_GFM_RESULT(a0)
  372. dmtc2 t2, 0x0259
  373. ld t2, OCTEON_CP2_GFM_RESULT+8(a0)
  374. dmtc2 t0, 0x025E
  375. dmtc2 t1, 0x025A
  376. dmtc2 t2, 0x025B
  377. done_restore:
  378. jr ra
  379. nop
  380. END(octeon_cop2_restore)
  381. .set pop
  382. /*
  383. * void octeon_mult_save()
  384. * sp is assumed to point to a struct pt_regs
  385. *
  386. * NOTE: This is called in SAVE_SOME in stackframe.h. It can only
  387. * safely modify k0 and k1.
  388. */
  389. .align 7
  390. .set push
  391. .set noreorder
  392. LEAF(octeon_mult_save)
  393. dmfc0 k0, $9,7 /* CvmCtl register. */
  394. bbit1 k0, 27, 1f /* Skip CvmCtl[NOMUL] */
  395. nop
  396. /* Save the multiplier state */
  397. v3mulu k0, $0, $0
  398. v3mulu k1, $0, $0
  399. sd k0, PT_MTP(sp) /* PT_MTP has P0 */
  400. v3mulu k0, $0, $0
  401. sd k1, PT_MTP+8(sp) /* PT_MTP+8 has P1 */
  402. ori k1, $0, 1
  403. v3mulu k1, k1, $0
  404. sd k0, PT_MTP+16(sp) /* PT_MTP+16 has P2 */
  405. v3mulu k0, $0, $0
  406. sd k1, PT_MPL(sp) /* PT_MPL has MPL0 */
  407. v3mulu k1, $0, $0
  408. sd k0, PT_MPL+8(sp) /* PT_MPL+8 has MPL1 */
  409. jr ra
  410. sd k1, PT_MPL+16(sp) /* PT_MPL+16 has MPL2 */
  411. 1: /* Resume here if CvmCtl[NOMUL] */
  412. jr ra
  413. END(octeon_mult_save)
  414. .set pop
  415. /*
  416. * void octeon_mult_restore()
  417. * sp is assumed to point to a struct pt_regs
  418. *
  419. * NOTE: This is called in RESTORE_SOME in stackframe.h.
  420. */
  421. .align 7
  422. .set push
  423. .set noreorder
  424. LEAF(octeon_mult_restore)
  425. dmfc0 k1, $9,7 /* CvmCtl register. */
  426. ld v0, PT_MPL(sp) /* MPL0 */
  427. ld v1, PT_MPL+8(sp) /* MPL1 */
  428. ld k0, PT_MPL+16(sp) /* MPL2 */
  429. bbit1 k1, 27, 1f /* Skip CvmCtl[NOMUL] */
  430. /* Normally falls through, so no time wasted here */
  431. nop
  432. /* Restore the multiplier state */
  433. ld k1, PT_MTP+16(sp) /* P2 */
  434. MTM0 v0 /* MPL0 */
  435. ld v0, PT_MTP+8(sp) /* P1 */
  436. MTM1 v1 /* MPL1 */
  437. ld v1, PT_MTP(sp) /* P0 */
  438. MTM2 k0 /* MPL2 */
  439. MTP2 k1 /* P2 */
  440. MTP1 v0 /* P1 */
  441. jr ra
  442. MTP0 v1 /* P0 */
  443. 1: /* Resume here if CvmCtl[NOMUL] */
  444. jr ra
  445. nop
  446. END(octeon_mult_restore)
  447. .set pop