irq-gic.c 9.5 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2008 Ralf Baechle (ralf@linux-mips.org)
  7. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  8. */
  9. #include <linux/bitmap.h>
  10. #include <linux/init.h>
  11. #include <linux/smp.h>
  12. #include <linux/irq.h>
  13. #include <linux/clocksource.h>
  14. #include <asm/io.h>
  15. #include <asm/gic.h>
  16. #include <asm/setup.h>
  17. #include <asm/traps.h>
  18. #include <asm/gcmpregs.h>
  19. #include <linux/hardirq.h>
  20. #include <asm-generic/bitops/find.h>
  21. unsigned int gic_frequency;
  22. unsigned int gic_present;
  23. unsigned long _gic_base;
  24. unsigned int gic_irq_base;
  25. unsigned int gic_irq_flags[GIC_NUM_INTRS];
  26. /* The index into this array is the vector # of the interrupt. */
  27. struct gic_shared_intr_map gic_shared_intr_map[GIC_NUM_INTRS];
  28. static struct gic_pcpu_mask pcpu_masks[NR_CPUS];
  29. static struct gic_pending_regs pending_regs[NR_CPUS];
  30. static struct gic_intrmask_regs intrmask_regs[NR_CPUS];
  31. #if defined(CONFIG_CSRC_GIC) || defined(CONFIG_CEVT_GIC)
  32. cycle_t gic_read_count(void)
  33. {
  34. unsigned int hi, hi2, lo;
  35. do {
  36. GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi);
  37. GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_31_00), lo);
  38. GICREAD(GIC_REG(SHARED, GIC_SH_COUNTER_63_32), hi2);
  39. } while (hi2 != hi);
  40. return (((cycle_t) hi) << 32) + lo;
  41. }
  42. void gic_write_compare(cycle_t cnt)
  43. {
  44. GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI),
  45. (int)(cnt >> 32));
  46. GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO),
  47. (int)(cnt & 0xffffffff));
  48. }
  49. cycle_t gic_read_compare(void)
  50. {
  51. unsigned int hi, lo;
  52. GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_HI), hi);
  53. GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_COMPARE_LO), lo);
  54. return (((cycle_t) hi) << 32) + lo;
  55. }
  56. #endif
  57. unsigned int gic_get_timer_pending(void)
  58. {
  59. unsigned int vpe_pending;
  60. GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), 0);
  61. GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_PEND), vpe_pending);
  62. return (vpe_pending & GIC_VPE_PEND_TIMER_MSK);
  63. }
  64. void gic_bind_eic_interrupt(int irq, int set)
  65. {
  66. /* Convert irq vector # to hw int # */
  67. irq -= GIC_PIN_TO_VEC_OFFSET;
  68. /* Set irq to use shadow set */
  69. GICWRITE(GIC_REG_ADDR(VPE_LOCAL, GIC_VPE_EIC_SS(irq)), set);
  70. }
  71. void gic_send_ipi(unsigned int intr)
  72. {
  73. GICWRITE(GIC_REG(SHARED, GIC_SH_WEDGE), 0x80000000 | intr);
  74. }
  75. static void gic_eic_irq_dispatch(void)
  76. {
  77. unsigned int cause = read_c0_cause();
  78. int irq;
  79. irq = (cause & ST0_IM) >> STATUSB_IP2;
  80. if (irq == 0)
  81. irq = -1;
  82. if (irq >= 0)
  83. do_IRQ(gic_irq_base + irq);
  84. else
  85. spurious_interrupt();
  86. }
  87. static void __init vpe_local_setup(unsigned int numvpes)
  88. {
  89. unsigned long timer_intr = GIC_INT_TMR;
  90. unsigned long perf_intr = GIC_INT_PERFCTR;
  91. unsigned int vpe_ctl;
  92. int i;
  93. if (cpu_has_veic) {
  94. /*
  95. * GIC timer interrupt -> CPU HW Int X (vector X+2) ->
  96. * map to pin X+2-1 (since GIC adds 1)
  97. */
  98. timer_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  99. /*
  100. * GIC perfcnt interrupt -> CPU HW Int X (vector X+2) ->
  101. * map to pin X+2-1 (since GIC adds 1)
  102. */
  103. perf_intr += (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  104. }
  105. /*
  106. * Setup the default performance counter timer interrupts
  107. * for all VPEs
  108. */
  109. for (i = 0; i < numvpes; i++) {
  110. GICWRITE(GIC_REG(VPE_LOCAL, GIC_VPE_OTHER_ADDR), i);
  111. /* Are Interrupts locally routable? */
  112. GICREAD(GIC_REG(VPE_OTHER, GIC_VPE_CTL), vpe_ctl);
  113. if (vpe_ctl & GIC_VPE_CTL_TIMER_RTBL_MSK)
  114. GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_TIMER_MAP),
  115. GIC_MAP_TO_PIN_MSK | timer_intr);
  116. if (cpu_has_veic) {
  117. set_vi_handler(timer_intr + GIC_PIN_TO_VEC_OFFSET,
  118. gic_eic_irq_dispatch);
  119. gic_shared_intr_map[timer_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_TIMER_MSK;
  120. }
  121. if (vpe_ctl & GIC_VPE_CTL_PERFCNT_RTBL_MSK)
  122. GICWRITE(GIC_REG(VPE_OTHER, GIC_VPE_PERFCTR_MAP),
  123. GIC_MAP_TO_PIN_MSK | perf_intr);
  124. if (cpu_has_veic) {
  125. set_vi_handler(perf_intr + GIC_PIN_TO_VEC_OFFSET, gic_eic_irq_dispatch);
  126. gic_shared_intr_map[perf_intr + GIC_PIN_TO_VEC_OFFSET].local_intr_mask |= GIC_VPE_RMASK_PERFCNT_MSK;
  127. }
  128. }
  129. }
  130. unsigned int gic_compare_int(void)
  131. {
  132. unsigned int pending;
  133. GICREAD(GIC_REG(VPE_LOCAL, GIC_VPE_PEND), pending);
  134. if (pending & GIC_VPE_PEND_CMP_MSK)
  135. return 1;
  136. else
  137. return 0;
  138. }
  139. unsigned int gic_get_int(void)
  140. {
  141. unsigned int i;
  142. unsigned long *pending, *intrmask, *pcpu_mask;
  143. unsigned long *pending_abs, *intrmask_abs;
  144. /* Get per-cpu bitmaps */
  145. pending = pending_regs[smp_processor_id()].pending;
  146. intrmask = intrmask_regs[smp_processor_id()].intrmask;
  147. pcpu_mask = pcpu_masks[smp_processor_id()].pcpu_mask;
  148. pending_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
  149. GIC_SH_PEND_31_0_OFS);
  150. intrmask_abs = (unsigned long *) GIC_REG_ABS_ADDR(SHARED,
  151. GIC_SH_MASK_31_0_OFS);
  152. for (i = 0; i < BITS_TO_LONGS(GIC_NUM_INTRS); i++) {
  153. GICREAD(*pending_abs, pending[i]);
  154. GICREAD(*intrmask_abs, intrmask[i]);
  155. pending_abs++;
  156. intrmask_abs++;
  157. }
  158. bitmap_and(pending, pending, intrmask, GIC_NUM_INTRS);
  159. bitmap_and(pending, pending, pcpu_mask, GIC_NUM_INTRS);
  160. return find_first_bit(pending, GIC_NUM_INTRS);
  161. }
  162. static void gic_mask_irq(struct irq_data *d)
  163. {
  164. GIC_CLR_INTR_MASK(d->irq - gic_irq_base);
  165. }
  166. static void gic_unmask_irq(struct irq_data *d)
  167. {
  168. GIC_SET_INTR_MASK(d->irq - gic_irq_base);
  169. }
  170. #ifdef CONFIG_SMP
  171. static DEFINE_SPINLOCK(gic_lock);
  172. static int gic_set_affinity(struct irq_data *d, const struct cpumask *cpumask,
  173. bool force)
  174. {
  175. unsigned int irq = (d->irq - gic_irq_base);
  176. cpumask_t tmp = CPU_MASK_NONE;
  177. unsigned long flags;
  178. int i;
  179. cpumask_and(&tmp, cpumask, cpu_online_mask);
  180. if (cpus_empty(tmp))
  181. return -1;
  182. /* Assumption : cpumask refers to a single CPU */
  183. spin_lock_irqsave(&gic_lock, flags);
  184. /* Re-route this IRQ */
  185. GIC_SH_MAP_TO_VPE_SMASK(irq, first_cpu(tmp));
  186. /* Update the pcpu_masks */
  187. for (i = 0; i < NR_CPUS; i++)
  188. clear_bit(irq, pcpu_masks[i].pcpu_mask);
  189. set_bit(irq, pcpu_masks[first_cpu(tmp)].pcpu_mask);
  190. cpumask_copy(d->affinity, cpumask);
  191. spin_unlock_irqrestore(&gic_lock, flags);
  192. return IRQ_SET_MASK_OK_NOCOPY;
  193. }
  194. #endif
  195. static struct irq_chip gic_irq_controller = {
  196. .name = "MIPS GIC",
  197. .irq_ack = gic_irq_ack,
  198. .irq_mask = gic_mask_irq,
  199. .irq_mask_ack = gic_mask_irq,
  200. .irq_unmask = gic_unmask_irq,
  201. .irq_eoi = gic_finish_irq,
  202. #ifdef CONFIG_SMP
  203. .irq_set_affinity = gic_set_affinity,
  204. #endif
  205. };
  206. static void __init gic_setup_intr(unsigned int intr, unsigned int cpu,
  207. unsigned int pin, unsigned int polarity, unsigned int trigtype,
  208. unsigned int flags)
  209. {
  210. struct gic_shared_intr_map *map_ptr;
  211. /* Setup Intr to Pin mapping */
  212. if (pin & GIC_MAP_TO_NMI_MSK) {
  213. GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)), pin);
  214. /* FIXME: hack to route NMI to all cpu's */
  215. for (cpu = 0; cpu < NR_CPUS; cpu += 32) {
  216. GICWRITE(GIC_REG_ADDR(SHARED,
  217. GIC_SH_MAP_TO_VPE_REG_OFF(intr, cpu)),
  218. 0xffffffff);
  219. }
  220. } else {
  221. GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_PIN(intr)),
  222. GIC_MAP_TO_PIN_MSK | pin);
  223. /* Setup Intr to CPU mapping */
  224. GIC_SH_MAP_TO_VPE_SMASK(intr, cpu);
  225. if (cpu_has_veic) {
  226. set_vi_handler(pin + GIC_PIN_TO_VEC_OFFSET,
  227. gic_eic_irq_dispatch);
  228. map_ptr = &gic_shared_intr_map[pin + GIC_PIN_TO_VEC_OFFSET];
  229. if (map_ptr->num_shared_intr >= GIC_MAX_SHARED_INTR)
  230. BUG();
  231. map_ptr->intr_list[map_ptr->num_shared_intr++] = intr;
  232. }
  233. }
  234. /* Setup Intr Polarity */
  235. GIC_SET_POLARITY(intr, polarity);
  236. /* Setup Intr Trigger Type */
  237. GIC_SET_TRIGGER(intr, trigtype);
  238. /* Init Intr Masks */
  239. GIC_CLR_INTR_MASK(intr);
  240. /* Initialise per-cpu Interrupt software masks */
  241. if (flags & GIC_FLAG_IPI)
  242. set_bit(intr, pcpu_masks[cpu].pcpu_mask);
  243. if ((flags & GIC_FLAG_TRANSPARENT) && (cpu_has_veic == 0))
  244. GIC_SET_INTR_MASK(intr);
  245. if (trigtype == GIC_TRIG_EDGE)
  246. gic_irq_flags[intr] |= GIC_TRIG_EDGE;
  247. }
  248. static void __init gic_basic_init(int numintrs, int numvpes,
  249. struct gic_intr_map *intrmap, int mapsize)
  250. {
  251. unsigned int i, cpu;
  252. unsigned int pin_offset = 0;
  253. board_bind_eic_interrupt = &gic_bind_eic_interrupt;
  254. /* Setup defaults */
  255. for (i = 0; i < numintrs; i++) {
  256. GIC_SET_POLARITY(i, GIC_POL_POS);
  257. GIC_SET_TRIGGER(i, GIC_TRIG_LEVEL);
  258. GIC_CLR_INTR_MASK(i);
  259. if (i < GIC_NUM_INTRS) {
  260. gic_irq_flags[i] = 0;
  261. gic_shared_intr_map[i].num_shared_intr = 0;
  262. gic_shared_intr_map[i].local_intr_mask = 0;
  263. }
  264. }
  265. /*
  266. * In EIC mode, the HW_INT# is offset by (2-1). Need to subtract
  267. * one because the GIC will add one (since 0=no intr).
  268. */
  269. if (cpu_has_veic)
  270. pin_offset = (GIC_CPU_TO_VEC_OFFSET - GIC_PIN_TO_VEC_OFFSET);
  271. /* Setup specifics */
  272. for (i = 0; i < mapsize; i++) {
  273. cpu = intrmap[i].cpunum;
  274. if (cpu == GIC_UNUSED)
  275. continue;
  276. if (cpu == 0 && i != 0 && intrmap[i].flags == 0)
  277. continue;
  278. gic_setup_intr(i,
  279. intrmap[i].cpunum,
  280. intrmap[i].pin + pin_offset,
  281. intrmap[i].polarity,
  282. intrmap[i].trigtype,
  283. intrmap[i].flags);
  284. }
  285. vpe_local_setup(numvpes);
  286. }
  287. void __init gic_init(unsigned long gic_base_addr,
  288. unsigned long gic_addrspace_size,
  289. struct gic_intr_map *intr_map, unsigned int intr_map_size,
  290. unsigned int irqbase)
  291. {
  292. unsigned int gicconfig;
  293. int numvpes, numintrs;
  294. _gic_base = (unsigned long) ioremap_nocache(gic_base_addr,
  295. gic_addrspace_size);
  296. gic_irq_base = irqbase;
  297. GICREAD(GIC_REG(SHARED, GIC_SH_CONFIG), gicconfig);
  298. numintrs = (gicconfig & GIC_SH_CONFIG_NUMINTRS_MSK) >>
  299. GIC_SH_CONFIG_NUMINTRS_SHF;
  300. numintrs = ((numintrs + 1) * 8);
  301. numvpes = (gicconfig & GIC_SH_CONFIG_NUMVPES_MSK) >>
  302. GIC_SH_CONFIG_NUMVPES_SHF;
  303. numvpes = numvpes + 1;
  304. gic_basic_init(numintrs, numvpes, intr_map, intr_map_size);
  305. gic_platform_init(numintrs, &gic_irq_controller);
  306. }