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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 1994, 1995 Waldorf Electronics
  7. * Written by Ralf Baechle and Andreas Busse
  8. * Copyright (C) 1994 - 99, 2003, 06 Ralf Baechle
  9. * Copyright (C) 1996 Paul M. Antoine
  10. * Modified for DECStation and hence R3000 support by Paul M. Antoine
  11. * Further modifications by David S. Miller and Harald Koerfgen
  12. * Copyright (C) 1999 Silicon Graphics, Inc.
  13. * Kevin Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
  14. * Copyright (C) 2000 MIPS Technologies, Inc. All rights reserved.
  15. */
  16. #include <linux/init.h>
  17. #include <linux/threads.h>
  18. #include <asm/addrspace.h>
  19. #include <asm/asm.h>
  20. #include <asm/asmmacro.h>
  21. #include <asm/irqflags.h>
  22. #include <asm/regdef.h>
  23. #include <asm/pgtable-bits.h>
  24. #include <asm/mipsregs.h>
  25. #include <asm/stackframe.h>
  26. #include <kernel-entry-init.h>
  27. /*
  28. * For the moment disable interrupts, mark the kernel mode and
  29. * set ST0_KX so that the CPU does not spit fire when using
  30. * 64-bit addresses. A full initialization of the CPU's status
  31. * register is done later in per_cpu_trap_init().
  32. */
  33. .macro setup_c0_status set clr
  34. .set push
  35. #ifdef CONFIG_MIPS_MT_SMTC
  36. /*
  37. * For SMTC, we need to set privilege and disable interrupts only for
  38. * the current TC, using the TCStatus register.
  39. */
  40. mfc0 t0, CP0_TCSTATUS
  41. /* Fortunately CU 0 is in the same place in both registers */
  42. /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
  43. li t1, ST0_CU0 | 0x08001c00
  44. or t0, t1
  45. /* Clear TKSU, leave IXMT */
  46. xori t0, 0x00001800
  47. mtc0 t0, CP0_TCSTATUS
  48. _ehb
  49. /* We need to leave the global IE bit set, but clear EXL...*/
  50. mfc0 t0, CP0_STATUS
  51. or t0, ST0_CU0 | ST0_EXL | ST0_ERL | \set | \clr
  52. xor t0, ST0_EXL | ST0_ERL | \clr
  53. mtc0 t0, CP0_STATUS
  54. #else
  55. mfc0 t0, CP0_STATUS
  56. or t0, ST0_CU0|\set|0x1f|\clr
  57. xor t0, 0x1f|\clr
  58. mtc0 t0, CP0_STATUS
  59. .set noreorder
  60. sll zero,3 # ehb
  61. #endif
  62. .set pop
  63. .endm
  64. .macro setup_c0_status_pri
  65. #ifdef CONFIG_64BIT
  66. setup_c0_status ST0_KX 0
  67. #else
  68. setup_c0_status 0 0
  69. #endif
  70. .endm
  71. .macro setup_c0_status_sec
  72. #ifdef CONFIG_64BIT
  73. setup_c0_status ST0_KX ST0_BEV
  74. #else
  75. setup_c0_status 0 ST0_BEV
  76. #endif
  77. .endm
  78. #ifndef CONFIG_NO_EXCEPT_FILL
  79. /*
  80. * Reserved space for exception handlers.
  81. * Necessary for machines which link their kernels at KSEG0.
  82. */
  83. .fill 0x400
  84. #endif
  85. EXPORT(_stext)
  86. #ifdef CONFIG_BOOT_RAW
  87. /*
  88. * Give us a fighting chance of running if execution beings at the
  89. * kernel load address. This is needed because this platform does
  90. * not have a ELF loader yet.
  91. */
  92. FEXPORT(__kernel_entry)
  93. j kernel_entry
  94. #endif
  95. __REF
  96. NESTED(kernel_entry, 16, sp) # kernel entry point
  97. kernel_entry_setup # cpu specific setup
  98. setup_c0_status_pri
  99. /* We might not get launched at the address the kernel is linked to,
  100. so we jump there. */
  101. PTR_LA t0, 0f
  102. jr t0
  103. 0:
  104. #ifdef CONFIG_MIPS_MT_SMTC
  105. /*
  106. * In SMTC kernel, "CLI" is thread-specific, in TCStatus.
  107. * We still need to enable interrupts globally in Status,
  108. * and clear EXL/ERL.
  109. *
  110. * TCContext is used to track interrupt levels under
  111. * service in SMTC kernel. Clear for boot TC before
  112. * allowing any interrupts.
  113. */
  114. mtc0 zero, CP0_TCCONTEXT
  115. mfc0 t0, CP0_STATUS
  116. ori t0, t0, 0xff1f
  117. xori t0, t0, 0x001e
  118. mtc0 t0, CP0_STATUS
  119. #endif /* CONFIG_MIPS_MT_SMTC */
  120. PTR_LA t0, __bss_start # clear .bss
  121. LONG_S zero, (t0)
  122. PTR_LA t1, __bss_stop - LONGSIZE
  123. 1:
  124. PTR_ADDIU t0, LONGSIZE
  125. LONG_S zero, (t0)
  126. bne t0, t1, 1b
  127. LONG_S a0, fw_arg0 # firmware arguments
  128. LONG_S a1, fw_arg1
  129. LONG_S a2, fw_arg2
  130. LONG_S a3, fw_arg3
  131. MTC0 zero, CP0_CONTEXT # clear context register
  132. PTR_LA $28, init_thread_union
  133. /* Set the SP after an empty pt_regs. */
  134. PTR_LI sp, _THREAD_SIZE - 32 - PT_SIZE
  135. PTR_ADDU sp, $28
  136. back_to_back_c0_hazard
  137. set_saved_sp sp, t0, t1
  138. PTR_SUBU sp, 4 * SZREG # init stack pointer
  139. j start_kernel
  140. END(kernel_entry)
  141. #ifdef CONFIG_SMP
  142. /*
  143. * SMP slave cpus entry point. Board specific code for bootstrap calls this
  144. * function after setting up the stack and gp registers.
  145. */
  146. NESTED(smp_bootstrap, 16, sp)
  147. #ifdef CONFIG_MIPS_MT_SMTC
  148. /*
  149. * Read-modify-writes of Status must be atomic, and this
  150. * is one case where CLI is invoked without EXL being
  151. * necessarily set. The CLI and setup_c0_status will
  152. * in fact be redundant for all but the first TC of
  153. * each VPE being booted.
  154. */
  155. DMT 10 # dmt t2 /* t0, t1 are used by CLI and setup_c0_status() */
  156. jal mips_ihb
  157. #endif /* CONFIG_MIPS_MT_SMTC */
  158. setup_c0_status_sec
  159. smp_slave_setup
  160. #ifdef CONFIG_MIPS_MT_SMTC
  161. andi t2, t2, VPECONTROL_TE
  162. beqz t2, 2f
  163. EMT # emt
  164. 2:
  165. #endif /* CONFIG_MIPS_MT_SMTC */
  166. j start_secondary
  167. END(smp_bootstrap)
  168. #endif /* CONFIG_SMP */