cpu-probe.c 25 KB

12345678910111213141516171819202122232425262728293031323334353637383940414243444546474849505152535455565758596061626364656667686970717273747576777879808182838485868788899091929394959697989910010110210310410510610710810911011111211311411511611711811912012112212312412512612712812913013113213313413513613713813914014114214314414514614714814915015115215315415515615715815916016116216316416516616716816917017117217317417517617717817918018118218318418518618718818919019119219319419519619719819920020120220320420520620720820921021121221321421521621721821922022122222322422522622722822923023123223323423523623723823924024124224324424524624724824925025125225325425525625725825926026126226326426526626726826927027127227327427527627727827928028128228328428528628728828929029129229329429529629729829930030130230330430530630730830931031131231331431531631731831932032132232332432532632732832933033133233333433533633733833934034134234334434534634734834935035135235335435535635735835936036136236336436536636736836937037137237337437537637737837938038138238338438538638738838939039139239339439539639739839940040140240340440540640740840941041141241341441541641741841942042142242342442542642742842943043143243343443543643743843944044144244344444544644744844945045145245345445545645745845946046146246346446546646746846947047147247347447547647747847948048148248348448548648748848949049149249349449549649749849950050150250350450550650750850951051151251351451551651751851952052152252352452552652752852953053153253353453553653753853954054154254354454554654754854955055155255355455555655755855956056156256356456556656756856957057157257357457557657757857958058158258358458558658758858959059159259359459559659759859960060160260360460560660760860961061161261361461561661761861962062162262362462562662762862963063163263363463563663763863964064164264364464564664764864965065165265365465565665765865966066166266366466566666766866967067167267367467567667767867968068168268368468568668768868969069169269369469569669769869970070170270370470570670770870971071171271371471571671771871972072172272372472572672772872973073173273373473573673773873974074174274374474574674774874975075175275375475575675775875976076176276376476576676776876977077177277377477577677777877978078178278378478578678778878979079179279379479579679779879980080180280380480580680780880981081181281381481581681781881982082182282382482582682782882983083183283383483583683783883984084184284384484584684784884985085185285385485585685785885986086186286386486586686786886987087187287387487587687787887988088188288388488588688788888989089189289389489589689789889990090190290390490590690790890991091191291391491591691791891992092192292392492592692792892993093193293393493593693793893994094194294394494594694794894995095195295395495595695795895996096196296396496596696796896997097197297397497597697797897998098198298398498598698798898999099199299399499599699799899910001001100210031004100510061007100810091010101110121013101410151016101710181019102010211022102310241025102610271028102910301031103210331034103510361037103810391040104110421043104410451046104710481049105010511052105310541055105610571058
  1. /*
  2. * Processor capabilities determination functions.
  3. *
  4. * Copyright (C) xxxx the Anonymous
  5. * Copyright (C) 1994 - 2006 Ralf Baechle
  6. * Copyright (C) 2003, 2004 Maciej W. Rozycki
  7. * Copyright (C) 2001, 2004, 2011, 2012 MIPS Technologies, Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License
  11. * as published by the Free Software Foundation; either version
  12. * 2 of the License, or (at your option) any later version.
  13. */
  14. #include <linux/init.h>
  15. #include <linux/kernel.h>
  16. #include <linux/ptrace.h>
  17. #include <linux/smp.h>
  18. #include <linux/stddef.h>
  19. #include <linux/export.h>
  20. #include <asm/bugs.h>
  21. #include <asm/cpu.h>
  22. #include <asm/fpu.h>
  23. #include <asm/mipsregs.h>
  24. #include <asm/watch.h>
  25. #include <asm/elf.h>
  26. #include <asm/spram.h>
  27. #include <asm/uaccess.h>
  28. static int mips_fpu_disabled;
  29. static int __init fpu_disable(char *s)
  30. {
  31. cpu_data[0].options &= ~MIPS_CPU_FPU;
  32. mips_fpu_disabled = 1;
  33. return 1;
  34. }
  35. __setup("nofpu", fpu_disable);
  36. int mips_dsp_disabled;
  37. static int __init dsp_disable(char *s)
  38. {
  39. cpu_data[0].ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  40. mips_dsp_disabled = 1;
  41. return 1;
  42. }
  43. __setup("nodsp", dsp_disable);
  44. static inline void check_errata(void)
  45. {
  46. struct cpuinfo_mips *c = &current_cpu_data;
  47. switch (c->cputype) {
  48. case CPU_34K:
  49. /*
  50. * Erratum "RPS May Cause Incorrect Instruction Execution"
  51. * This code only handles VPE0, any SMP/SMTC/RTOS code
  52. * making use of VPE1 will be responsable for that VPE.
  53. */
  54. if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2)
  55. write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS);
  56. break;
  57. default:
  58. break;
  59. }
  60. }
  61. void __init check_bugs32(void)
  62. {
  63. check_errata();
  64. }
  65. /*
  66. * Probe whether cpu has config register by trying to play with
  67. * alternate cache bit and see whether it matters.
  68. * It's used by cpu_probe to distinguish between R3000A and R3081.
  69. */
  70. static inline int cpu_has_confreg(void)
  71. {
  72. #ifdef CONFIG_CPU_R3000
  73. extern unsigned long r3k_cache_size(unsigned long);
  74. unsigned long size1, size2;
  75. unsigned long cfg = read_c0_conf();
  76. size1 = r3k_cache_size(ST0_ISC);
  77. write_c0_conf(cfg ^ R30XX_CONF_AC);
  78. size2 = r3k_cache_size(ST0_ISC);
  79. write_c0_conf(cfg);
  80. return size1 != size2;
  81. #else
  82. return 0;
  83. #endif
  84. }
  85. static inline void set_elf_platform(int cpu, const char *plat)
  86. {
  87. if (cpu == 0)
  88. __elf_platform = plat;
  89. }
  90. /*
  91. * Get the FPU Implementation/Revision.
  92. */
  93. static inline unsigned long cpu_get_fpu_id(void)
  94. {
  95. unsigned long tmp, fpu_id;
  96. tmp = read_c0_status();
  97. __enable_fpu();
  98. fpu_id = read_32bit_cp1_register(CP1_REVISION);
  99. write_c0_status(tmp);
  100. return fpu_id;
  101. }
  102. /*
  103. * Check the CPU has an FPU the official way.
  104. */
  105. static inline int __cpu_has_fpu(void)
  106. {
  107. return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE);
  108. }
  109. static inline void cpu_probe_vmbits(struct cpuinfo_mips *c)
  110. {
  111. #ifdef __NEED_VMBITS_PROBE
  112. write_c0_entryhi(0x3fffffffffffe000ULL);
  113. back_to_back_c0_hazard();
  114. c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL);
  115. #endif
  116. }
  117. static void set_isa(struct cpuinfo_mips *c, unsigned int isa)
  118. {
  119. switch (isa) {
  120. case MIPS_CPU_ISA_M64R2:
  121. c->isa_level |= MIPS_CPU_ISA_M32R2 | MIPS_CPU_ISA_M64R2;
  122. case MIPS_CPU_ISA_M64R1:
  123. c->isa_level |= MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M64R1;
  124. case MIPS_CPU_ISA_V:
  125. c->isa_level |= MIPS_CPU_ISA_V;
  126. case MIPS_CPU_ISA_IV:
  127. c->isa_level |= MIPS_CPU_ISA_IV;
  128. case MIPS_CPU_ISA_III:
  129. c->isa_level |= MIPS_CPU_ISA_II | MIPS_CPU_ISA_III;
  130. break;
  131. case MIPS_CPU_ISA_M32R2:
  132. c->isa_level |= MIPS_CPU_ISA_M32R2;
  133. case MIPS_CPU_ISA_M32R1:
  134. c->isa_level |= MIPS_CPU_ISA_M32R1;
  135. case MIPS_CPU_ISA_II:
  136. c->isa_level |= MIPS_CPU_ISA_II;
  137. break;
  138. }
  139. }
  140. static char unknown_isa[] = KERN_ERR \
  141. "Unsupported ISA type, c0.config0: %d.";
  142. static inline unsigned int decode_config0(struct cpuinfo_mips *c)
  143. {
  144. unsigned int config0;
  145. int isa;
  146. config0 = read_c0_config();
  147. if (((config0 & MIPS_CONF_MT) >> 7) == 1)
  148. c->options |= MIPS_CPU_TLB;
  149. isa = (config0 & MIPS_CONF_AT) >> 13;
  150. switch (isa) {
  151. case 0:
  152. switch ((config0 & MIPS_CONF_AR) >> 10) {
  153. case 0:
  154. set_isa(c, MIPS_CPU_ISA_M32R1);
  155. break;
  156. case 1:
  157. set_isa(c, MIPS_CPU_ISA_M32R2);
  158. break;
  159. default:
  160. goto unknown;
  161. }
  162. break;
  163. case 2:
  164. switch ((config0 & MIPS_CONF_AR) >> 10) {
  165. case 0:
  166. set_isa(c, MIPS_CPU_ISA_M64R1);
  167. break;
  168. case 1:
  169. set_isa(c, MIPS_CPU_ISA_M64R2);
  170. break;
  171. default:
  172. goto unknown;
  173. }
  174. break;
  175. default:
  176. goto unknown;
  177. }
  178. return config0 & MIPS_CONF_M;
  179. unknown:
  180. panic(unknown_isa, config0);
  181. }
  182. static inline unsigned int decode_config1(struct cpuinfo_mips *c)
  183. {
  184. unsigned int config1;
  185. config1 = read_c0_config1();
  186. if (config1 & MIPS_CONF1_MD)
  187. c->ases |= MIPS_ASE_MDMX;
  188. if (config1 & MIPS_CONF1_WR)
  189. c->options |= MIPS_CPU_WATCH;
  190. if (config1 & MIPS_CONF1_CA)
  191. c->ases |= MIPS_ASE_MIPS16;
  192. if (config1 & MIPS_CONF1_EP)
  193. c->options |= MIPS_CPU_EJTAG;
  194. if (config1 & MIPS_CONF1_FP) {
  195. c->options |= MIPS_CPU_FPU;
  196. c->options |= MIPS_CPU_32FPR;
  197. }
  198. if (cpu_has_tlb)
  199. c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1;
  200. return config1 & MIPS_CONF_M;
  201. }
  202. static inline unsigned int decode_config2(struct cpuinfo_mips *c)
  203. {
  204. unsigned int config2;
  205. config2 = read_c0_config2();
  206. if (config2 & MIPS_CONF2_SL)
  207. c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT;
  208. return config2 & MIPS_CONF_M;
  209. }
  210. static inline unsigned int decode_config3(struct cpuinfo_mips *c)
  211. {
  212. unsigned int config3;
  213. config3 = read_c0_config3();
  214. if (config3 & MIPS_CONF3_SM) {
  215. c->ases |= MIPS_ASE_SMARTMIPS;
  216. c->options |= MIPS_CPU_RIXI;
  217. }
  218. if (config3 & MIPS_CONF3_RXI)
  219. c->options |= MIPS_CPU_RIXI;
  220. if (config3 & MIPS_CONF3_DSP)
  221. c->ases |= MIPS_ASE_DSP;
  222. if (config3 & MIPS_CONF3_DSP2P)
  223. c->ases |= MIPS_ASE_DSP2P;
  224. if (config3 & MIPS_CONF3_VINT)
  225. c->options |= MIPS_CPU_VINT;
  226. if (config3 & MIPS_CONF3_VEIC)
  227. c->options |= MIPS_CPU_VEIC;
  228. if (config3 & MIPS_CONF3_MT)
  229. c->ases |= MIPS_ASE_MIPSMT;
  230. if (config3 & MIPS_CONF3_ULRI)
  231. c->options |= MIPS_CPU_ULRI;
  232. if (config3 & MIPS_CONF3_ISA)
  233. c->options |= MIPS_CPU_MICROMIPS;
  234. if (config3 & MIPS_CONF3_VZ)
  235. c->ases |= MIPS_ASE_VZ;
  236. return config3 & MIPS_CONF_M;
  237. }
  238. static inline unsigned int decode_config4(struct cpuinfo_mips *c)
  239. {
  240. unsigned int config4;
  241. config4 = read_c0_config4();
  242. if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT
  243. && cpu_has_tlb)
  244. c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40;
  245. c->kscratch_mask = (config4 >> 16) & 0xff;
  246. return config4 & MIPS_CONF_M;
  247. }
  248. static void decode_configs(struct cpuinfo_mips *c)
  249. {
  250. int ok;
  251. /* MIPS32 or MIPS64 compliant CPU. */
  252. c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER |
  253. MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK;
  254. c->scache.flags = MIPS_CACHE_NOT_PRESENT;
  255. ok = decode_config0(c); /* Read Config registers. */
  256. BUG_ON(!ok); /* Arch spec violation! */
  257. if (ok)
  258. ok = decode_config1(c);
  259. if (ok)
  260. ok = decode_config2(c);
  261. if (ok)
  262. ok = decode_config3(c);
  263. if (ok)
  264. ok = decode_config4(c);
  265. mips_probe_watch_registers(c);
  266. if (cpu_has_mips_r2)
  267. c->core = read_c0_ebase() & 0x3ff;
  268. }
  269. #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \
  270. | MIPS_CPU_COUNTER)
  271. static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu)
  272. {
  273. switch (c->processor_id & 0xff00) {
  274. case PRID_IMP_R2000:
  275. c->cputype = CPU_R2000;
  276. __cpu_name[cpu] = "R2000";
  277. c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
  278. MIPS_CPU_NOFPUEX;
  279. if (__cpu_has_fpu())
  280. c->options |= MIPS_CPU_FPU;
  281. c->tlbsize = 64;
  282. break;
  283. case PRID_IMP_R3000:
  284. if ((c->processor_id & 0xff) == PRID_REV_R3000A) {
  285. if (cpu_has_confreg()) {
  286. c->cputype = CPU_R3081E;
  287. __cpu_name[cpu] = "R3081";
  288. } else {
  289. c->cputype = CPU_R3000A;
  290. __cpu_name[cpu] = "R3000A";
  291. }
  292. } else {
  293. c->cputype = CPU_R3000;
  294. __cpu_name[cpu] = "R3000";
  295. }
  296. c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE |
  297. MIPS_CPU_NOFPUEX;
  298. if (__cpu_has_fpu())
  299. c->options |= MIPS_CPU_FPU;
  300. c->tlbsize = 64;
  301. break;
  302. case PRID_IMP_R4000:
  303. if (read_c0_config() & CONF_SC) {
  304. if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
  305. c->cputype = CPU_R4400PC;
  306. __cpu_name[cpu] = "R4400PC";
  307. } else {
  308. c->cputype = CPU_R4000PC;
  309. __cpu_name[cpu] = "R4000PC";
  310. }
  311. } else {
  312. if ((c->processor_id & 0xff) >= PRID_REV_R4400) {
  313. c->cputype = CPU_R4400SC;
  314. __cpu_name[cpu] = "R4400SC";
  315. } else {
  316. c->cputype = CPU_R4000SC;
  317. __cpu_name[cpu] = "R4000SC";
  318. }
  319. }
  320. set_isa(c, MIPS_CPU_ISA_III);
  321. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  322. MIPS_CPU_WATCH | MIPS_CPU_VCE |
  323. MIPS_CPU_LLSC;
  324. c->tlbsize = 48;
  325. break;
  326. case PRID_IMP_VR41XX:
  327. set_isa(c, MIPS_CPU_ISA_III);
  328. c->options = R4K_OPTS;
  329. c->tlbsize = 32;
  330. switch (c->processor_id & 0xf0) {
  331. case PRID_REV_VR4111:
  332. c->cputype = CPU_VR4111;
  333. __cpu_name[cpu] = "NEC VR4111";
  334. break;
  335. case PRID_REV_VR4121:
  336. c->cputype = CPU_VR4121;
  337. __cpu_name[cpu] = "NEC VR4121";
  338. break;
  339. case PRID_REV_VR4122:
  340. if ((c->processor_id & 0xf) < 0x3) {
  341. c->cputype = CPU_VR4122;
  342. __cpu_name[cpu] = "NEC VR4122";
  343. } else {
  344. c->cputype = CPU_VR4181A;
  345. __cpu_name[cpu] = "NEC VR4181A";
  346. }
  347. break;
  348. case PRID_REV_VR4130:
  349. if ((c->processor_id & 0xf) < 0x4) {
  350. c->cputype = CPU_VR4131;
  351. __cpu_name[cpu] = "NEC VR4131";
  352. } else {
  353. c->cputype = CPU_VR4133;
  354. c->options |= MIPS_CPU_LLSC;
  355. __cpu_name[cpu] = "NEC VR4133";
  356. }
  357. break;
  358. default:
  359. printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n");
  360. c->cputype = CPU_VR41XX;
  361. __cpu_name[cpu] = "NEC Vr41xx";
  362. break;
  363. }
  364. break;
  365. case PRID_IMP_R4300:
  366. c->cputype = CPU_R4300;
  367. __cpu_name[cpu] = "R4300";
  368. set_isa(c, MIPS_CPU_ISA_III);
  369. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  370. MIPS_CPU_LLSC;
  371. c->tlbsize = 32;
  372. break;
  373. case PRID_IMP_R4600:
  374. c->cputype = CPU_R4600;
  375. __cpu_name[cpu] = "R4600";
  376. set_isa(c, MIPS_CPU_ISA_III);
  377. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  378. MIPS_CPU_LLSC;
  379. c->tlbsize = 48;
  380. break;
  381. #if 0
  382. case PRID_IMP_R4650:
  383. /*
  384. * This processor doesn't have an MMU, so it's not
  385. * "real easy" to run Linux on it. It is left purely
  386. * for documentation. Commented out because it shares
  387. * it's c0_prid id number with the TX3900.
  388. */
  389. c->cputype = CPU_R4650;
  390. __cpu_name[cpu] = "R4650";
  391. set_isa(c, MIPS_CPU_ISA_III);
  392. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC;
  393. c->tlbsize = 48;
  394. break;
  395. #endif
  396. case PRID_IMP_TX39:
  397. c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE;
  398. if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) {
  399. c->cputype = CPU_TX3927;
  400. __cpu_name[cpu] = "TX3927";
  401. c->tlbsize = 64;
  402. } else {
  403. switch (c->processor_id & 0xff) {
  404. case PRID_REV_TX3912:
  405. c->cputype = CPU_TX3912;
  406. __cpu_name[cpu] = "TX3912";
  407. c->tlbsize = 32;
  408. break;
  409. case PRID_REV_TX3922:
  410. c->cputype = CPU_TX3922;
  411. __cpu_name[cpu] = "TX3922";
  412. c->tlbsize = 64;
  413. break;
  414. }
  415. }
  416. break;
  417. case PRID_IMP_R4700:
  418. c->cputype = CPU_R4700;
  419. __cpu_name[cpu] = "R4700";
  420. set_isa(c, MIPS_CPU_ISA_III);
  421. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  422. MIPS_CPU_LLSC;
  423. c->tlbsize = 48;
  424. break;
  425. case PRID_IMP_TX49:
  426. c->cputype = CPU_TX49XX;
  427. __cpu_name[cpu] = "R49XX";
  428. set_isa(c, MIPS_CPU_ISA_III);
  429. c->options = R4K_OPTS | MIPS_CPU_LLSC;
  430. if (!(c->processor_id & 0x08))
  431. c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR;
  432. c->tlbsize = 48;
  433. break;
  434. case PRID_IMP_R5000:
  435. c->cputype = CPU_R5000;
  436. __cpu_name[cpu] = "R5000";
  437. set_isa(c, MIPS_CPU_ISA_IV);
  438. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  439. MIPS_CPU_LLSC;
  440. c->tlbsize = 48;
  441. break;
  442. case PRID_IMP_R5432:
  443. c->cputype = CPU_R5432;
  444. __cpu_name[cpu] = "R5432";
  445. set_isa(c, MIPS_CPU_ISA_IV);
  446. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  447. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  448. c->tlbsize = 48;
  449. break;
  450. case PRID_IMP_R5500:
  451. c->cputype = CPU_R5500;
  452. __cpu_name[cpu] = "R5500";
  453. set_isa(c, MIPS_CPU_ISA_IV);
  454. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  455. MIPS_CPU_WATCH | MIPS_CPU_LLSC;
  456. c->tlbsize = 48;
  457. break;
  458. case PRID_IMP_NEVADA:
  459. c->cputype = CPU_NEVADA;
  460. __cpu_name[cpu] = "Nevada";
  461. set_isa(c, MIPS_CPU_ISA_IV);
  462. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  463. MIPS_CPU_DIVEC | MIPS_CPU_LLSC;
  464. c->tlbsize = 48;
  465. break;
  466. case PRID_IMP_R6000:
  467. c->cputype = CPU_R6000;
  468. __cpu_name[cpu] = "R6000";
  469. set_isa(c, MIPS_CPU_ISA_II);
  470. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  471. MIPS_CPU_LLSC;
  472. c->tlbsize = 32;
  473. break;
  474. case PRID_IMP_R6000A:
  475. c->cputype = CPU_R6000A;
  476. __cpu_name[cpu] = "R6000A";
  477. set_isa(c, MIPS_CPU_ISA_II);
  478. c->options = MIPS_CPU_TLB | MIPS_CPU_FPU |
  479. MIPS_CPU_LLSC;
  480. c->tlbsize = 32;
  481. break;
  482. case PRID_IMP_RM7000:
  483. c->cputype = CPU_RM7000;
  484. __cpu_name[cpu] = "RM7000";
  485. set_isa(c, MIPS_CPU_ISA_IV);
  486. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  487. MIPS_CPU_LLSC;
  488. /*
  489. * Undocumented RM7000: Bit 29 in the info register of
  490. * the RM7000 v2.0 indicates if the TLB has 48 or 64
  491. * entries.
  492. *
  493. * 29 1 => 64 entry JTLB
  494. * 0 => 48 entry JTLB
  495. */
  496. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  497. break;
  498. case PRID_IMP_RM9000:
  499. c->cputype = CPU_RM9000;
  500. __cpu_name[cpu] = "RM9000";
  501. set_isa(c, MIPS_CPU_ISA_IV);
  502. c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR |
  503. MIPS_CPU_LLSC;
  504. /*
  505. * Bit 29 in the info register of the RM9000
  506. * indicates if the TLB has 48 or 64 entries.
  507. *
  508. * 29 1 => 64 entry JTLB
  509. * 0 => 48 entry JTLB
  510. */
  511. c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48;
  512. break;
  513. case PRID_IMP_R8000:
  514. c->cputype = CPU_R8000;
  515. __cpu_name[cpu] = "RM8000";
  516. set_isa(c, MIPS_CPU_ISA_IV);
  517. c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX |
  518. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  519. MIPS_CPU_LLSC;
  520. c->tlbsize = 384; /* has weird TLB: 3-way x 128 */
  521. break;
  522. case PRID_IMP_R10000:
  523. c->cputype = CPU_R10000;
  524. __cpu_name[cpu] = "R10000";
  525. set_isa(c, MIPS_CPU_ISA_IV);
  526. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  527. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  528. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  529. MIPS_CPU_LLSC;
  530. c->tlbsize = 64;
  531. break;
  532. case PRID_IMP_R12000:
  533. c->cputype = CPU_R12000;
  534. __cpu_name[cpu] = "R12000";
  535. set_isa(c, MIPS_CPU_ISA_IV);
  536. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  537. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  538. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  539. MIPS_CPU_LLSC;
  540. c->tlbsize = 64;
  541. break;
  542. case PRID_IMP_R14000:
  543. c->cputype = CPU_R14000;
  544. __cpu_name[cpu] = "R14000";
  545. set_isa(c, MIPS_CPU_ISA_IV);
  546. c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX |
  547. MIPS_CPU_FPU | MIPS_CPU_32FPR |
  548. MIPS_CPU_COUNTER | MIPS_CPU_WATCH |
  549. MIPS_CPU_LLSC;
  550. c->tlbsize = 64;
  551. break;
  552. case PRID_IMP_LOONGSON2:
  553. c->cputype = CPU_LOONGSON2;
  554. __cpu_name[cpu] = "ICT Loongson-2";
  555. switch (c->processor_id & PRID_REV_MASK) {
  556. case PRID_REV_LOONGSON2E:
  557. set_elf_platform(cpu, "loongson2e");
  558. break;
  559. case PRID_REV_LOONGSON2F:
  560. set_elf_platform(cpu, "loongson2f");
  561. break;
  562. }
  563. set_isa(c, MIPS_CPU_ISA_III);
  564. c->options = R4K_OPTS |
  565. MIPS_CPU_FPU | MIPS_CPU_LLSC |
  566. MIPS_CPU_32FPR;
  567. c->tlbsize = 64;
  568. break;
  569. case PRID_IMP_LOONGSON1:
  570. decode_configs(c);
  571. c->cputype = CPU_LOONGSON1;
  572. switch (c->processor_id & PRID_REV_MASK) {
  573. case PRID_REV_LOONGSON1B:
  574. __cpu_name[cpu] = "Loongson 1B";
  575. break;
  576. }
  577. break;
  578. }
  579. }
  580. static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu)
  581. {
  582. decode_configs(c);
  583. switch (c->processor_id & 0xff00) {
  584. case PRID_IMP_4KC:
  585. c->cputype = CPU_4KC;
  586. __cpu_name[cpu] = "MIPS 4Kc";
  587. break;
  588. case PRID_IMP_4KEC:
  589. case PRID_IMP_4KECR2:
  590. c->cputype = CPU_4KEC;
  591. __cpu_name[cpu] = "MIPS 4KEc";
  592. break;
  593. case PRID_IMP_4KSC:
  594. case PRID_IMP_4KSD:
  595. c->cputype = CPU_4KSC;
  596. __cpu_name[cpu] = "MIPS 4KSc";
  597. break;
  598. case PRID_IMP_5KC:
  599. c->cputype = CPU_5KC;
  600. __cpu_name[cpu] = "MIPS 5Kc";
  601. break;
  602. case PRID_IMP_5KE:
  603. c->cputype = CPU_5KE;
  604. __cpu_name[cpu] = "MIPS 5KE";
  605. break;
  606. case PRID_IMP_20KC:
  607. c->cputype = CPU_20KC;
  608. __cpu_name[cpu] = "MIPS 20Kc";
  609. break;
  610. case PRID_IMP_24K:
  611. c->cputype = CPU_24K;
  612. __cpu_name[cpu] = "MIPS 24Kc";
  613. break;
  614. case PRID_IMP_24KE:
  615. c->cputype = CPU_24K;
  616. __cpu_name[cpu] = "MIPS 24KEc";
  617. break;
  618. case PRID_IMP_25KF:
  619. c->cputype = CPU_25KF;
  620. __cpu_name[cpu] = "MIPS 25Kc";
  621. break;
  622. case PRID_IMP_34K:
  623. c->cputype = CPU_34K;
  624. __cpu_name[cpu] = "MIPS 34Kc";
  625. break;
  626. case PRID_IMP_74K:
  627. c->cputype = CPU_74K;
  628. __cpu_name[cpu] = "MIPS 74Kc";
  629. break;
  630. case PRID_IMP_M14KC:
  631. c->cputype = CPU_M14KC;
  632. __cpu_name[cpu] = "MIPS M14Kc";
  633. break;
  634. case PRID_IMP_M14KEC:
  635. c->cputype = CPU_M14KEC;
  636. __cpu_name[cpu] = "MIPS M14KEc";
  637. break;
  638. case PRID_IMP_1004K:
  639. c->cputype = CPU_1004K;
  640. __cpu_name[cpu] = "MIPS 1004Kc";
  641. break;
  642. case PRID_IMP_1074K:
  643. c->cputype = CPU_74K;
  644. __cpu_name[cpu] = "MIPS 1074Kc";
  645. break;
  646. }
  647. spram_config();
  648. }
  649. static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
  650. {
  651. decode_configs(c);
  652. switch (c->processor_id & 0xff00) {
  653. case PRID_IMP_AU1_REV1:
  654. case PRID_IMP_AU1_REV2:
  655. c->cputype = CPU_ALCHEMY;
  656. switch ((c->processor_id >> 24) & 0xff) {
  657. case 0:
  658. __cpu_name[cpu] = "Au1000";
  659. break;
  660. case 1:
  661. __cpu_name[cpu] = "Au1500";
  662. break;
  663. case 2:
  664. __cpu_name[cpu] = "Au1100";
  665. break;
  666. case 3:
  667. __cpu_name[cpu] = "Au1550";
  668. break;
  669. case 4:
  670. __cpu_name[cpu] = "Au1200";
  671. if ((c->processor_id & 0xff) == 2)
  672. __cpu_name[cpu] = "Au1250";
  673. break;
  674. case 5:
  675. __cpu_name[cpu] = "Au1210";
  676. break;
  677. default:
  678. __cpu_name[cpu] = "Au1xxx";
  679. break;
  680. }
  681. break;
  682. }
  683. }
  684. static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu)
  685. {
  686. decode_configs(c);
  687. switch (c->processor_id & 0xff00) {
  688. case PRID_IMP_SB1:
  689. c->cputype = CPU_SB1;
  690. __cpu_name[cpu] = "SiByte SB1";
  691. /* FPU in pass1 is known to have issues. */
  692. if ((c->processor_id & 0xff) < 0x02)
  693. c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR);
  694. break;
  695. case PRID_IMP_SB1A:
  696. c->cputype = CPU_SB1A;
  697. __cpu_name[cpu] = "SiByte SB1A";
  698. break;
  699. }
  700. }
  701. static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu)
  702. {
  703. decode_configs(c);
  704. switch (c->processor_id & 0xff00) {
  705. case PRID_IMP_SR71000:
  706. c->cputype = CPU_SR71000;
  707. __cpu_name[cpu] = "Sandcraft SR71000";
  708. c->scache.ways = 8;
  709. c->tlbsize = 64;
  710. break;
  711. }
  712. }
  713. static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu)
  714. {
  715. decode_configs(c);
  716. switch (c->processor_id & 0xff00) {
  717. case PRID_IMP_PR4450:
  718. c->cputype = CPU_PR4450;
  719. __cpu_name[cpu] = "Philips PR4450";
  720. set_isa(c, MIPS_CPU_ISA_M32R1);
  721. break;
  722. }
  723. }
  724. static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
  725. {
  726. decode_configs(c);
  727. switch (c->processor_id & 0xff00) {
  728. case PRID_IMP_BMIPS32_REV4:
  729. case PRID_IMP_BMIPS32_REV8:
  730. c->cputype = CPU_BMIPS32;
  731. __cpu_name[cpu] = "Broadcom BMIPS32";
  732. set_elf_platform(cpu, "bmips32");
  733. break;
  734. case PRID_IMP_BMIPS3300:
  735. case PRID_IMP_BMIPS3300_ALT:
  736. case PRID_IMP_BMIPS3300_BUG:
  737. c->cputype = CPU_BMIPS3300;
  738. __cpu_name[cpu] = "Broadcom BMIPS3300";
  739. set_elf_platform(cpu, "bmips3300");
  740. break;
  741. case PRID_IMP_BMIPS43XX: {
  742. int rev = c->processor_id & 0xff;
  743. if (rev >= PRID_REV_BMIPS4380_LO &&
  744. rev <= PRID_REV_BMIPS4380_HI) {
  745. c->cputype = CPU_BMIPS4380;
  746. __cpu_name[cpu] = "Broadcom BMIPS4380";
  747. set_elf_platform(cpu, "bmips4380");
  748. } else {
  749. c->cputype = CPU_BMIPS4350;
  750. __cpu_name[cpu] = "Broadcom BMIPS4350";
  751. set_elf_platform(cpu, "bmips4350");
  752. }
  753. break;
  754. }
  755. case PRID_IMP_BMIPS5000:
  756. c->cputype = CPU_BMIPS5000;
  757. __cpu_name[cpu] = "Broadcom BMIPS5000";
  758. set_elf_platform(cpu, "bmips5000");
  759. c->options |= MIPS_CPU_ULRI;
  760. break;
  761. }
  762. }
  763. static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu)
  764. {
  765. decode_configs(c);
  766. switch (c->processor_id & 0xff00) {
  767. case PRID_IMP_CAVIUM_CN38XX:
  768. case PRID_IMP_CAVIUM_CN31XX:
  769. case PRID_IMP_CAVIUM_CN30XX:
  770. c->cputype = CPU_CAVIUM_OCTEON;
  771. __cpu_name[cpu] = "Cavium Octeon";
  772. goto platform;
  773. case PRID_IMP_CAVIUM_CN58XX:
  774. case PRID_IMP_CAVIUM_CN56XX:
  775. case PRID_IMP_CAVIUM_CN50XX:
  776. case PRID_IMP_CAVIUM_CN52XX:
  777. c->cputype = CPU_CAVIUM_OCTEON_PLUS;
  778. __cpu_name[cpu] = "Cavium Octeon+";
  779. platform:
  780. set_elf_platform(cpu, "octeon");
  781. break;
  782. case PRID_IMP_CAVIUM_CN61XX:
  783. case PRID_IMP_CAVIUM_CN63XX:
  784. case PRID_IMP_CAVIUM_CN66XX:
  785. case PRID_IMP_CAVIUM_CN68XX:
  786. c->cputype = CPU_CAVIUM_OCTEON2;
  787. __cpu_name[cpu] = "Cavium Octeon II";
  788. set_elf_platform(cpu, "octeon2");
  789. break;
  790. default:
  791. printk(KERN_INFO "Unknown Octeon chip!\n");
  792. c->cputype = CPU_UNKNOWN;
  793. break;
  794. }
  795. }
  796. static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu)
  797. {
  798. decode_configs(c);
  799. /* JZRISC does not implement the CP0 counter. */
  800. c->options &= ~MIPS_CPU_COUNTER;
  801. switch (c->processor_id & 0xff00) {
  802. case PRID_IMP_JZRISC:
  803. c->cputype = CPU_JZRISC;
  804. __cpu_name[cpu] = "Ingenic JZRISC";
  805. break;
  806. default:
  807. panic("Unknown Ingenic Processor ID!");
  808. break;
  809. }
  810. }
  811. static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu)
  812. {
  813. decode_configs(c);
  814. if ((c->processor_id & 0xff00) == PRID_IMP_NETLOGIC_AU13XX) {
  815. c->cputype = CPU_ALCHEMY;
  816. __cpu_name[cpu] = "Au1300";
  817. /* following stuff is not for Alchemy */
  818. return;
  819. }
  820. c->options = (MIPS_CPU_TLB |
  821. MIPS_CPU_4KEX |
  822. MIPS_CPU_COUNTER |
  823. MIPS_CPU_DIVEC |
  824. MIPS_CPU_WATCH |
  825. MIPS_CPU_EJTAG |
  826. MIPS_CPU_LLSC);
  827. switch (c->processor_id & 0xff00) {
  828. case PRID_IMP_NETLOGIC_XLP8XX:
  829. case PRID_IMP_NETLOGIC_XLP3XX:
  830. c->cputype = CPU_XLP;
  831. __cpu_name[cpu] = "Netlogic XLP";
  832. break;
  833. case PRID_IMP_NETLOGIC_XLR732:
  834. case PRID_IMP_NETLOGIC_XLR716:
  835. case PRID_IMP_NETLOGIC_XLR532:
  836. case PRID_IMP_NETLOGIC_XLR308:
  837. case PRID_IMP_NETLOGIC_XLR532C:
  838. case PRID_IMP_NETLOGIC_XLR516C:
  839. case PRID_IMP_NETLOGIC_XLR508C:
  840. case PRID_IMP_NETLOGIC_XLR308C:
  841. c->cputype = CPU_XLR;
  842. __cpu_name[cpu] = "Netlogic XLR";
  843. break;
  844. case PRID_IMP_NETLOGIC_XLS608:
  845. case PRID_IMP_NETLOGIC_XLS408:
  846. case PRID_IMP_NETLOGIC_XLS404:
  847. case PRID_IMP_NETLOGIC_XLS208:
  848. case PRID_IMP_NETLOGIC_XLS204:
  849. case PRID_IMP_NETLOGIC_XLS108:
  850. case PRID_IMP_NETLOGIC_XLS104:
  851. case PRID_IMP_NETLOGIC_XLS616B:
  852. case PRID_IMP_NETLOGIC_XLS608B:
  853. case PRID_IMP_NETLOGIC_XLS416B:
  854. case PRID_IMP_NETLOGIC_XLS412B:
  855. case PRID_IMP_NETLOGIC_XLS408B:
  856. case PRID_IMP_NETLOGIC_XLS404B:
  857. c->cputype = CPU_XLR;
  858. __cpu_name[cpu] = "Netlogic XLS";
  859. break;
  860. default:
  861. pr_info("Unknown Netlogic chip id [%02x]!\n",
  862. c->processor_id);
  863. c->cputype = CPU_XLR;
  864. break;
  865. }
  866. if (c->cputype == CPU_XLP) {
  867. set_isa(c, MIPS_CPU_ISA_M64R2);
  868. c->options |= (MIPS_CPU_FPU | MIPS_CPU_ULRI | MIPS_CPU_MCHECK);
  869. /* This will be updated again after all threads are woken up */
  870. c->tlbsize = ((read_c0_config6() >> 16) & 0xffff) + 1;
  871. } else {
  872. set_isa(c, MIPS_CPU_ISA_M64R1);
  873. c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1;
  874. }
  875. c->kscratch_mask = 0xf;
  876. }
  877. #ifdef CONFIG_64BIT
  878. /* For use by uaccess.h */
  879. u64 __ua_limit;
  880. EXPORT_SYMBOL(__ua_limit);
  881. #endif
  882. const char *__cpu_name[NR_CPUS];
  883. const char *__elf_platform;
  884. void cpu_probe(void)
  885. {
  886. struct cpuinfo_mips *c = &current_cpu_data;
  887. unsigned int cpu = smp_processor_id();
  888. c->processor_id = PRID_IMP_UNKNOWN;
  889. c->fpu_id = FPIR_IMP_NONE;
  890. c->cputype = CPU_UNKNOWN;
  891. c->processor_id = read_c0_prid();
  892. switch (c->processor_id & 0xff0000) {
  893. case PRID_COMP_LEGACY:
  894. cpu_probe_legacy(c, cpu);
  895. break;
  896. case PRID_COMP_MIPS:
  897. cpu_probe_mips(c, cpu);
  898. break;
  899. case PRID_COMP_ALCHEMY:
  900. cpu_probe_alchemy(c, cpu);
  901. break;
  902. case PRID_COMP_SIBYTE:
  903. cpu_probe_sibyte(c, cpu);
  904. break;
  905. case PRID_COMP_BROADCOM:
  906. cpu_probe_broadcom(c, cpu);
  907. break;
  908. case PRID_COMP_SANDCRAFT:
  909. cpu_probe_sandcraft(c, cpu);
  910. break;
  911. case PRID_COMP_NXP:
  912. cpu_probe_nxp(c, cpu);
  913. break;
  914. case PRID_COMP_CAVIUM:
  915. cpu_probe_cavium(c, cpu);
  916. break;
  917. case PRID_COMP_INGENIC:
  918. cpu_probe_ingenic(c, cpu);
  919. break;
  920. case PRID_COMP_NETLOGIC:
  921. cpu_probe_netlogic(c, cpu);
  922. break;
  923. }
  924. BUG_ON(!__cpu_name[cpu]);
  925. BUG_ON(c->cputype == CPU_UNKNOWN);
  926. /*
  927. * Platform code can force the cpu type to optimize code
  928. * generation. In that case be sure the cpu type is correctly
  929. * manually setup otherwise it could trigger some nasty bugs.
  930. */
  931. BUG_ON(current_cpu_type() != c->cputype);
  932. if (mips_fpu_disabled)
  933. c->options &= ~MIPS_CPU_FPU;
  934. if (mips_dsp_disabled)
  935. c->ases &= ~(MIPS_ASE_DSP | MIPS_ASE_DSP2P);
  936. if (c->options & MIPS_CPU_FPU) {
  937. c->fpu_id = cpu_get_fpu_id();
  938. if (c->isa_level & (MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 |
  939. MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)) {
  940. if (c->fpu_id & MIPS_FPIR_3D)
  941. c->ases |= MIPS_ASE_MIPS3D;
  942. }
  943. }
  944. if (cpu_has_mips_r2) {
  945. c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1;
  946. /* R2 has Performance Counter Interrupt indicator */
  947. c->options |= MIPS_CPU_PCI;
  948. }
  949. else
  950. c->srsets = 1;
  951. cpu_probe_vmbits(c);
  952. #ifdef CONFIG_64BIT
  953. if (cpu == 0)
  954. __ua_limit = ~((1ull << cpu_vmbits) - 1);
  955. #endif
  956. }
  957. void cpu_report(void)
  958. {
  959. struct cpuinfo_mips *c = &current_cpu_data;
  960. printk(KERN_INFO "CPU revision is: %08x (%s)\n",
  961. c->processor_id, cpu_name_string());
  962. if (c->options & MIPS_CPU_FPU)
  963. printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id);
  964. }