bmips_vec.S 5.4 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2011 by Kevin Cernekee (cernekee@gmail.com)
  7. *
  8. * Reset/NMI/re-entry vectors for BMIPS processors
  9. */
  10. #include <linux/init.h>
  11. #include <asm/asm.h>
  12. #include <asm/asmmacro.h>
  13. #include <asm/cacheops.h>
  14. #include <asm/regdef.h>
  15. #include <asm/mipsregs.h>
  16. #include <asm/stackframe.h>
  17. #include <asm/addrspace.h>
  18. #include <asm/hazards.h>
  19. #include <asm/bmips.h>
  20. .macro BARRIER
  21. .set mips32
  22. _ssnop
  23. _ssnop
  24. _ssnop
  25. .set mips0
  26. .endm
  27. /***********************************************************************
  28. * Alternate CPU1 startup vector for BMIPS4350
  29. *
  30. * On some systems the bootloader has already started CPU1 and configured
  31. * it to resume execution at 0x8000_0200 (!BEV IV vector) when it is
  32. * triggered by the SW1 interrupt. If that is the case we try to move
  33. * it to a more convenient place: BMIPS_WARM_RESTART_VEC @ 0x8000_0380.
  34. ***********************************************************************/
  35. LEAF(bmips_smp_movevec)
  36. la k0, 1f
  37. li k1, CKSEG1
  38. or k0, k1
  39. jr k0
  40. 1:
  41. /* clear IV, pending IPIs */
  42. mtc0 zero, CP0_CAUSE
  43. /* re-enable IRQs to wait for SW1 */
  44. li k0, ST0_IE | ST0_BEV | STATUSF_IP1
  45. mtc0 k0, CP0_STATUS
  46. /* set up CPU1 CBR; move BASE to 0xa000_0000 */
  47. li k0, 0xff400000
  48. mtc0 k0, $22, 6
  49. /* set up relocation vector address based on thread ID */
  50. mfc0 k1, $22, 3
  51. srl k1, 16
  52. andi k1, 0x8000
  53. or k1, CKSEG1 | BMIPS_RELO_VECTOR_CONTROL_0
  54. or k0, k1
  55. li k1, 0xa0080000
  56. sw k1, 0(k0)
  57. /* wait here for SW1 interrupt from bmips_boot_secondary() */
  58. wait
  59. la k0, bmips_reset_nmi_vec
  60. li k1, CKSEG1
  61. or k0, k1
  62. jr k0
  63. END(bmips_smp_movevec)
  64. /***********************************************************************
  65. * Reset/NMI vector
  66. * For BMIPS processors that can relocate their exception vectors, this
  67. * entire function gets copied to 0x8000_0000.
  68. ***********************************************************************/
  69. NESTED(bmips_reset_nmi_vec, PT_SIZE, sp)
  70. .set push
  71. .set noat
  72. .align 4
  73. #ifdef CONFIG_SMP
  74. /* if the NMI bit is clear, assume this is a CPU1 reset instead */
  75. li k1, (1 << 19)
  76. mfc0 k0, CP0_STATUS
  77. and k0, k1
  78. beqz k0, bmips_smp_entry
  79. #if defined(CONFIG_CPU_BMIPS5000)
  80. /* if we're not on core 0, this must be the SMP boot signal */
  81. li k1, (3 << 25)
  82. mfc0 k0, $22
  83. and k0, k1
  84. bnez k0, bmips_smp_entry
  85. #endif
  86. #endif /* CONFIG_SMP */
  87. /* nope, it's just a regular NMI */
  88. SAVE_ALL
  89. move a0, sp
  90. /* clear EXL, ERL, BEV so that TLB refills still work */
  91. mfc0 k0, CP0_STATUS
  92. li k1, ST0_ERL | ST0_EXL | ST0_BEV | ST0_IE
  93. or k0, k1
  94. xor k0, k1
  95. mtc0 k0, CP0_STATUS
  96. BARRIER
  97. /* jump to the NMI handler function */
  98. la k0, nmi_handler
  99. jr k0
  100. RESTORE_ALL
  101. .set mips3
  102. eret
  103. /***********************************************************************
  104. * CPU1 reset vector (used for the initial boot only)
  105. * This is still part of bmips_reset_nmi_vec().
  106. ***********************************************************************/
  107. #ifdef CONFIG_SMP
  108. bmips_smp_entry:
  109. /* set up CP0 STATUS; enable FPU */
  110. li k0, 0x30000000
  111. mtc0 k0, CP0_STATUS
  112. BARRIER
  113. /* set local CP0 CONFIG to make kseg0 cacheable, write-back */
  114. mfc0 k0, CP0_CONFIG
  115. ori k0, 0x07
  116. xori k0, 0x04
  117. mtc0 k0, CP0_CONFIG
  118. #if defined(CONFIG_CPU_BMIPS4350) || defined(CONFIG_CPU_BMIPS4380)
  119. /* initialize CPU1's local I-cache */
  120. li k0, 0x80000000
  121. li k1, 0x80010000
  122. mtc0 zero, $28
  123. mtc0 zero, $28, 1
  124. BARRIER
  125. 1: cache Index_Store_Tag_I, 0(k0)
  126. addiu k0, 16
  127. bne k0, k1, 1b
  128. #elif defined(CONFIG_CPU_BMIPS5000)
  129. /* set exception vector base */
  130. la k0, ebase
  131. lw k0, 0(k0)
  132. mtc0 k0, $15, 1
  133. BARRIER
  134. #endif
  135. /* jump back to kseg0 in case we need to remap the kseg1 area */
  136. la k0, 1f
  137. jr k0
  138. 1:
  139. la k0, bmips_enable_xks01
  140. jalr k0
  141. /* use temporary stack to set up upper memory TLB */
  142. li sp, BMIPS_WARM_RESTART_VEC
  143. la k0, plat_wired_tlb_setup
  144. jalr k0
  145. /* switch to permanent stack and continue booting */
  146. .global bmips_secondary_reentry
  147. bmips_secondary_reentry:
  148. la k0, bmips_smp_boot_sp
  149. lw sp, 0(k0)
  150. la k0, bmips_smp_boot_gp
  151. lw gp, 0(k0)
  152. la k0, start_secondary
  153. jr k0
  154. #endif /* CONFIG_SMP */
  155. .align 4
  156. .global bmips_reset_nmi_vec_end
  157. bmips_reset_nmi_vec_end:
  158. END(bmips_reset_nmi_vec)
  159. .set pop
  160. .previous
  161. /***********************************************************************
  162. * CPU1 warm restart vector (used for second and subsequent boots).
  163. * Also used for S2 standby recovery (PM).
  164. * This entire function gets copied to (BMIPS_WARM_RESTART_VEC)
  165. ***********************************************************************/
  166. LEAF(bmips_smp_int_vec)
  167. .align 4
  168. mfc0 k0, CP0_STATUS
  169. ori k0, 0x01
  170. xori k0, 0x01
  171. mtc0 k0, CP0_STATUS
  172. eret
  173. .align 4
  174. .global bmips_smp_int_vec_end
  175. bmips_smp_int_vec_end:
  176. END(bmips_smp_int_vec)
  177. /***********************************************************************
  178. * XKS01 support
  179. * Certain CPUs support extending kseg0 to 1024MB.
  180. ***********************************************************************/
  181. LEAF(bmips_enable_xks01)
  182. #if defined(CONFIG_XKS01)
  183. #if defined(CONFIG_CPU_BMIPS4380)
  184. mfc0 t0, $22, 3
  185. li t1, 0x1ff0
  186. li t2, (1 << 12) | (1 << 9)
  187. or t0, t1
  188. xor t0, t1
  189. or t0, t2
  190. mtc0 t0, $22, 3
  191. BARRIER
  192. #elif defined(CONFIG_CPU_BMIPS5000)
  193. mfc0 t0, $22, 5
  194. li t1, 0x01ff
  195. li t2, (1 << 8) | (1 << 5)
  196. or t0, t1
  197. xor t0, t1
  198. or t0, t2
  199. mtc0 t0, $22, 5
  200. BARRIER
  201. #else
  202. #error Missing XKS01 setup
  203. #endif
  204. #endif /* defined(CONFIG_XKS01) */
  205. jr ra
  206. END(bmips_enable_xks01)
  207. .previous