kvm_host.h 23 KB

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  1. /*
  2. * This file is subject to the terms and conditions of the GNU General Public
  3. * License. See the file "COPYING" in the main directory of this archive
  4. * for more details.
  5. *
  6. * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
  7. * Authors: Sanjay Lal <sanjayl@kymasys.com>
  8. */
  9. #ifndef __MIPS_KVM_HOST_H__
  10. #define __MIPS_KVM_HOST_H__
  11. #include <linux/mutex.h>
  12. #include <linux/hrtimer.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/types.h>
  15. #include <linux/kvm.h>
  16. #include <linux/kvm_types.h>
  17. #include <linux/threads.h>
  18. #include <linux/spinlock.h>
  19. #define KVM_MAX_VCPUS 1
  20. #define KVM_USER_MEM_SLOTS 8
  21. /* memory slots that does not exposed to userspace */
  22. #define KVM_PRIVATE_MEM_SLOTS 0
  23. #define KVM_COALESCED_MMIO_PAGE_OFFSET 1
  24. /* Don't support huge pages */
  25. #define KVM_HPAGE_GFN_SHIFT(x) 0
  26. /* We don't currently support large pages. */
  27. #define KVM_NR_PAGE_SIZES 1
  28. #define KVM_PAGES_PER_HPAGE(x) 1
  29. /* Special address that contains the comm page, used for reducing # of traps */
  30. #define KVM_GUEST_COMMPAGE_ADDR 0x0
  31. #define KVM_GUEST_KERNEL_MODE(vcpu) ((kvm_read_c0_guest_status(vcpu->arch.cop0) & (ST0_EXL | ST0_ERL)) || \
  32. ((kvm_read_c0_guest_status(vcpu->arch.cop0) & KSU_USER) == 0))
  33. #define KVM_GUEST_KUSEG 0x00000000UL
  34. #define KVM_GUEST_KSEG0 0x40000000UL
  35. #define KVM_GUEST_KSEG23 0x60000000UL
  36. #define KVM_GUEST_KSEGX(a) ((_ACAST32_(a)) & 0x60000000)
  37. #define KVM_GUEST_CPHYSADDR(a) ((_ACAST32_(a)) & 0x1fffffff)
  38. #define KVM_GUEST_CKSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  39. #define KVM_GUEST_CKSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  40. #define KVM_GUEST_CKSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  41. /*
  42. * Map an address to a certain kernel segment
  43. */
  44. #define KVM_GUEST_KSEG0ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG0)
  45. #define KVM_GUEST_KSEG1ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG1)
  46. #define KVM_GUEST_KSEG23ADDR(a) (KVM_GUEST_CPHYSADDR(a) | KVM_GUEST_KSEG23)
  47. #define KVM_INVALID_PAGE 0xdeadbeef
  48. #define KVM_INVALID_INST 0xdeadbeef
  49. #define KVM_INVALID_ADDR 0xdeadbeef
  50. #define KVM_MALTA_GUEST_RTC_ADDR 0xb8000070UL
  51. #define GUEST_TICKS_PER_JIFFY (40000000/HZ)
  52. #define MS_TO_NS(x) (x * 1E6L)
  53. #define CAUSEB_DC 27
  54. #define CAUSEF_DC (_ULCAST_(1) << 27)
  55. struct kvm;
  56. struct kvm_run;
  57. struct kvm_vcpu;
  58. struct kvm_interrupt;
  59. extern atomic_t kvm_mips_instance;
  60. extern pfn_t(*kvm_mips_gfn_to_pfn) (struct kvm *kvm, gfn_t gfn);
  61. extern void (*kvm_mips_release_pfn_clean) (pfn_t pfn);
  62. extern bool(*kvm_mips_is_error_pfn) (pfn_t pfn);
  63. struct kvm_vm_stat {
  64. u32 remote_tlb_flush;
  65. };
  66. struct kvm_vcpu_stat {
  67. u32 wait_exits;
  68. u32 cache_exits;
  69. u32 signal_exits;
  70. u32 int_exits;
  71. u32 cop_unusable_exits;
  72. u32 tlbmod_exits;
  73. u32 tlbmiss_ld_exits;
  74. u32 tlbmiss_st_exits;
  75. u32 addrerr_st_exits;
  76. u32 addrerr_ld_exits;
  77. u32 syscall_exits;
  78. u32 resvd_inst_exits;
  79. u32 break_inst_exits;
  80. u32 flush_dcache_exits;
  81. u32 halt_wakeup;
  82. };
  83. enum kvm_mips_exit_types {
  84. WAIT_EXITS,
  85. CACHE_EXITS,
  86. SIGNAL_EXITS,
  87. INT_EXITS,
  88. COP_UNUSABLE_EXITS,
  89. TLBMOD_EXITS,
  90. TLBMISS_LD_EXITS,
  91. TLBMISS_ST_EXITS,
  92. ADDRERR_ST_EXITS,
  93. ADDRERR_LD_EXITS,
  94. SYSCALL_EXITS,
  95. RESVD_INST_EXITS,
  96. BREAK_INST_EXITS,
  97. FLUSH_DCACHE_EXITS,
  98. MAX_KVM_MIPS_EXIT_TYPES
  99. };
  100. struct kvm_arch_memory_slot {
  101. };
  102. struct kvm_arch {
  103. /* Guest GVA->HPA page table */
  104. unsigned long *guest_pmap;
  105. unsigned long guest_pmap_npages;
  106. /* Wired host TLB used for the commpage */
  107. int commpage_tlb;
  108. };
  109. #define N_MIPS_COPROC_REGS 32
  110. #define N_MIPS_COPROC_SEL 8
  111. struct mips_coproc {
  112. unsigned long reg[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
  113. #ifdef CONFIG_KVM_MIPS_DEBUG_COP0_COUNTERS
  114. unsigned long stat[N_MIPS_COPROC_REGS][N_MIPS_COPROC_SEL];
  115. #endif
  116. };
  117. /*
  118. * Coprocessor 0 register names
  119. */
  120. #define MIPS_CP0_TLB_INDEX 0
  121. #define MIPS_CP0_TLB_RANDOM 1
  122. #define MIPS_CP0_TLB_LOW 2
  123. #define MIPS_CP0_TLB_LO0 2
  124. #define MIPS_CP0_TLB_LO1 3
  125. #define MIPS_CP0_TLB_CONTEXT 4
  126. #define MIPS_CP0_TLB_PG_MASK 5
  127. #define MIPS_CP0_TLB_WIRED 6
  128. #define MIPS_CP0_HWRENA 7
  129. #define MIPS_CP0_BAD_VADDR 8
  130. #define MIPS_CP0_COUNT 9
  131. #define MIPS_CP0_TLB_HI 10
  132. #define MIPS_CP0_COMPARE 11
  133. #define MIPS_CP0_STATUS 12
  134. #define MIPS_CP0_CAUSE 13
  135. #define MIPS_CP0_EXC_PC 14
  136. #define MIPS_CP0_PRID 15
  137. #define MIPS_CP0_CONFIG 16
  138. #define MIPS_CP0_LLADDR 17
  139. #define MIPS_CP0_WATCH_LO 18
  140. #define MIPS_CP0_WATCH_HI 19
  141. #define MIPS_CP0_TLB_XCONTEXT 20
  142. #define MIPS_CP0_ECC 26
  143. #define MIPS_CP0_CACHE_ERR 27
  144. #define MIPS_CP0_TAG_LO 28
  145. #define MIPS_CP0_TAG_HI 29
  146. #define MIPS_CP0_ERROR_PC 30
  147. #define MIPS_CP0_DEBUG 23
  148. #define MIPS_CP0_DEPC 24
  149. #define MIPS_CP0_PERFCNT 25
  150. #define MIPS_CP0_ERRCTL 26
  151. #define MIPS_CP0_DATA_LO 28
  152. #define MIPS_CP0_DATA_HI 29
  153. #define MIPS_CP0_DESAVE 31
  154. #define MIPS_CP0_CONFIG_SEL 0
  155. #define MIPS_CP0_CONFIG1_SEL 1
  156. #define MIPS_CP0_CONFIG2_SEL 2
  157. #define MIPS_CP0_CONFIG3_SEL 3
  158. /* Config0 register bits */
  159. #define CP0C0_M 31
  160. #define CP0C0_K23 28
  161. #define CP0C0_KU 25
  162. #define CP0C0_MDU 20
  163. #define CP0C0_MM 17
  164. #define CP0C0_BM 16
  165. #define CP0C0_BE 15
  166. #define CP0C0_AT 13
  167. #define CP0C0_AR 10
  168. #define CP0C0_MT 7
  169. #define CP0C0_VI 3
  170. #define CP0C0_K0 0
  171. /* Config1 register bits */
  172. #define CP0C1_M 31
  173. #define CP0C1_MMU 25
  174. #define CP0C1_IS 22
  175. #define CP0C1_IL 19
  176. #define CP0C1_IA 16
  177. #define CP0C1_DS 13
  178. #define CP0C1_DL 10
  179. #define CP0C1_DA 7
  180. #define CP0C1_C2 6
  181. #define CP0C1_MD 5
  182. #define CP0C1_PC 4
  183. #define CP0C1_WR 3
  184. #define CP0C1_CA 2
  185. #define CP0C1_EP 1
  186. #define CP0C1_FP 0
  187. /* Config2 Register bits */
  188. #define CP0C2_M 31
  189. #define CP0C2_TU 28
  190. #define CP0C2_TS 24
  191. #define CP0C2_TL 20
  192. #define CP0C2_TA 16
  193. #define CP0C2_SU 12
  194. #define CP0C2_SS 8
  195. #define CP0C2_SL 4
  196. #define CP0C2_SA 0
  197. /* Config3 Register bits */
  198. #define CP0C3_M 31
  199. #define CP0C3_ISA_ON_EXC 16
  200. #define CP0C3_ULRI 13
  201. #define CP0C3_DSPP 10
  202. #define CP0C3_LPA 7
  203. #define CP0C3_VEIC 6
  204. #define CP0C3_VInt 5
  205. #define CP0C3_SP 4
  206. #define CP0C3_MT 2
  207. #define CP0C3_SM 1
  208. #define CP0C3_TL 0
  209. /* Have config1, Cacheable, noncoherent, write-back, write allocate*/
  210. #define MIPS_CONFIG0 \
  211. ((1 << CP0C0_M) | (0x3 << CP0C0_K0))
  212. /* Have config2, no coprocessor2 attached, no MDMX support attached,
  213. no performance counters, watch registers present,
  214. no code compression, EJTAG present, no FPU, no watch registers */
  215. #define MIPS_CONFIG1 \
  216. ((1 << CP0C1_M) | \
  217. (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
  218. (0 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
  219. (0 << CP0C1_FP))
  220. /* Have config3, no tertiary/secondary caches implemented */
  221. #define MIPS_CONFIG2 \
  222. ((1 << CP0C2_M))
  223. /* No config4, no DSP ASE, no large physaddr (PABITS),
  224. no external interrupt controller, no vectored interrupts,
  225. no 1kb pages, no SmartMIPS ASE, no trace logic */
  226. #define MIPS_CONFIG3 \
  227. ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
  228. (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
  229. (0 << CP0C3_SM) | (0 << CP0C3_TL))
  230. /* MMU types, the first four entries have the same layout as the
  231. CP0C0_MT field. */
  232. enum mips_mmu_types {
  233. MMU_TYPE_NONE,
  234. MMU_TYPE_R4000,
  235. MMU_TYPE_RESERVED,
  236. MMU_TYPE_FMT,
  237. MMU_TYPE_R3000,
  238. MMU_TYPE_R6000,
  239. MMU_TYPE_R8000
  240. };
  241. /*
  242. * Trap codes
  243. */
  244. #define T_INT 0 /* Interrupt pending */
  245. #define T_TLB_MOD 1 /* TLB modified fault */
  246. #define T_TLB_LD_MISS 2 /* TLB miss on load or ifetch */
  247. #define T_TLB_ST_MISS 3 /* TLB miss on a store */
  248. #define T_ADDR_ERR_LD 4 /* Address error on a load or ifetch */
  249. #define T_ADDR_ERR_ST 5 /* Address error on a store */
  250. #define T_BUS_ERR_IFETCH 6 /* Bus error on an ifetch */
  251. #define T_BUS_ERR_LD_ST 7 /* Bus error on a load or store */
  252. #define T_SYSCALL 8 /* System call */
  253. #define T_BREAK 9 /* Breakpoint */
  254. #define T_RES_INST 10 /* Reserved instruction exception */
  255. #define T_COP_UNUSABLE 11 /* Coprocessor unusable */
  256. #define T_OVFLOW 12 /* Arithmetic overflow */
  257. /*
  258. * Trap definitions added for r4000 port.
  259. */
  260. #define T_TRAP 13 /* Trap instruction */
  261. #define T_VCEI 14 /* Virtual coherency exception */
  262. #define T_FPE 15 /* Floating point exception */
  263. #define T_WATCH 23 /* Watch address reference */
  264. #define T_VCED 31 /* Virtual coherency data */
  265. /* Resume Flags */
  266. #define RESUME_FLAG_DR (1<<0) /* Reload guest nonvolatile state? */
  267. #define RESUME_FLAG_HOST (1<<1) /* Resume host? */
  268. #define RESUME_GUEST 0
  269. #define RESUME_GUEST_DR RESUME_FLAG_DR
  270. #define RESUME_HOST RESUME_FLAG_HOST
  271. enum emulation_result {
  272. EMULATE_DONE, /* no further processing */
  273. EMULATE_DO_MMIO, /* kvm_run filled with MMIO request */
  274. EMULATE_FAIL, /* can't emulate this instruction */
  275. EMULATE_WAIT, /* WAIT instruction */
  276. EMULATE_PRIV_FAIL,
  277. };
  278. #define MIPS3_PG_G 0x00000001 /* Global; ignore ASID if in lo0 & lo1 */
  279. #define MIPS3_PG_V 0x00000002 /* Valid */
  280. #define MIPS3_PG_NV 0x00000000
  281. #define MIPS3_PG_D 0x00000004 /* Dirty */
  282. #define mips3_paddr_to_tlbpfn(x) \
  283. (((unsigned long)(x) >> MIPS3_PG_SHIFT) & MIPS3_PG_FRAME)
  284. #define mips3_tlbpfn_to_paddr(x) \
  285. ((unsigned long)((x) & MIPS3_PG_FRAME) << MIPS3_PG_SHIFT)
  286. #define MIPS3_PG_SHIFT 6
  287. #define MIPS3_PG_FRAME 0x3fffffc0
  288. #define VPN2_MASK 0xffffe000
  289. #define TLB_IS_GLOBAL(x) (((x).tlb_lo0 & MIPS3_PG_G) && ((x).tlb_lo1 & MIPS3_PG_G))
  290. #define TLB_VPN2(x) ((x).tlb_hi & VPN2_MASK)
  291. #define TLB_ASID(x) ((x).tlb_hi & ASID_MASK)
  292. #define TLB_IS_VALID(x, va) (((va) & (1 << PAGE_SHIFT)) ? ((x).tlb_lo1 & MIPS3_PG_V) : ((x).tlb_lo0 & MIPS3_PG_V))
  293. struct kvm_mips_tlb {
  294. long tlb_mask;
  295. long tlb_hi;
  296. long tlb_lo0;
  297. long tlb_lo1;
  298. };
  299. #define KVM_MIPS_GUEST_TLB_SIZE 64
  300. struct kvm_vcpu_arch {
  301. void *host_ebase, *guest_ebase;
  302. unsigned long host_stack;
  303. unsigned long host_gp;
  304. /* Host CP0 registers used when handling exits from guest */
  305. unsigned long host_cp0_badvaddr;
  306. unsigned long host_cp0_cause;
  307. unsigned long host_cp0_epc;
  308. unsigned long host_cp0_entryhi;
  309. uint32_t guest_inst;
  310. /* GPRS */
  311. unsigned long gprs[32];
  312. unsigned long hi;
  313. unsigned long lo;
  314. unsigned long pc;
  315. /* FPU State */
  316. struct mips_fpu_struct fpu;
  317. /* COP0 State */
  318. struct mips_coproc *cop0;
  319. /* Host KSEG0 address of the EI/DI offset */
  320. void *kseg0_commpage;
  321. u32 io_gpr; /* GPR used as IO source/target */
  322. /* Used to calibrate the virutal count register for the guest */
  323. int32_t host_cp0_count;
  324. /* Bitmask of exceptions that are pending */
  325. unsigned long pending_exceptions;
  326. /* Bitmask of pending exceptions to be cleared */
  327. unsigned long pending_exceptions_clr;
  328. unsigned long pending_load_cause;
  329. /* Save/Restore the entryhi register when are are preempted/scheduled back in */
  330. unsigned long preempt_entryhi;
  331. /* S/W Based TLB for guest */
  332. struct kvm_mips_tlb guest_tlb[KVM_MIPS_GUEST_TLB_SIZE];
  333. /* Cached guest kernel/user ASIDs */
  334. uint32_t guest_user_asid[NR_CPUS];
  335. uint32_t guest_kernel_asid[NR_CPUS];
  336. struct mm_struct guest_kernel_mm, guest_user_mm;
  337. struct kvm_mips_tlb shadow_tlb[NR_CPUS][KVM_MIPS_GUEST_TLB_SIZE];
  338. struct hrtimer comparecount_timer;
  339. int last_sched_cpu;
  340. /* WAIT executed */
  341. int wait;
  342. };
  343. #define kvm_read_c0_guest_index(cop0) (cop0->reg[MIPS_CP0_TLB_INDEX][0])
  344. #define kvm_write_c0_guest_index(cop0, val) (cop0->reg[MIPS_CP0_TLB_INDEX][0] = val)
  345. #define kvm_read_c0_guest_entrylo0(cop0) (cop0->reg[MIPS_CP0_TLB_LO0][0])
  346. #define kvm_read_c0_guest_entrylo1(cop0) (cop0->reg[MIPS_CP0_TLB_LO1][0])
  347. #define kvm_read_c0_guest_context(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0])
  348. #define kvm_write_c0_guest_context(cop0, val) (cop0->reg[MIPS_CP0_TLB_CONTEXT][0] = (val))
  349. #define kvm_read_c0_guest_userlocal(cop0) (cop0->reg[MIPS_CP0_TLB_CONTEXT][2])
  350. #define kvm_read_c0_guest_pagemask(cop0) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0])
  351. #define kvm_write_c0_guest_pagemask(cop0, val) (cop0->reg[MIPS_CP0_TLB_PG_MASK][0] = (val))
  352. #define kvm_read_c0_guest_wired(cop0) (cop0->reg[MIPS_CP0_TLB_WIRED][0])
  353. #define kvm_write_c0_guest_wired(cop0, val) (cop0->reg[MIPS_CP0_TLB_WIRED][0] = (val))
  354. #define kvm_read_c0_guest_badvaddr(cop0) (cop0->reg[MIPS_CP0_BAD_VADDR][0])
  355. #define kvm_write_c0_guest_badvaddr(cop0, val) (cop0->reg[MIPS_CP0_BAD_VADDR][0] = (val))
  356. #define kvm_read_c0_guest_count(cop0) (cop0->reg[MIPS_CP0_COUNT][0])
  357. #define kvm_write_c0_guest_count(cop0, val) (cop0->reg[MIPS_CP0_COUNT][0] = (val))
  358. #define kvm_read_c0_guest_entryhi(cop0) (cop0->reg[MIPS_CP0_TLB_HI][0])
  359. #define kvm_write_c0_guest_entryhi(cop0, val) (cop0->reg[MIPS_CP0_TLB_HI][0] = (val))
  360. #define kvm_read_c0_guest_compare(cop0) (cop0->reg[MIPS_CP0_COMPARE][0])
  361. #define kvm_write_c0_guest_compare(cop0, val) (cop0->reg[MIPS_CP0_COMPARE][0] = (val))
  362. #define kvm_read_c0_guest_status(cop0) (cop0->reg[MIPS_CP0_STATUS][0])
  363. #define kvm_write_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] = (val))
  364. #define kvm_read_c0_guest_intctl(cop0) (cop0->reg[MIPS_CP0_STATUS][1])
  365. #define kvm_write_c0_guest_intctl(cop0, val) (cop0->reg[MIPS_CP0_STATUS][1] = (val))
  366. #define kvm_read_c0_guest_cause(cop0) (cop0->reg[MIPS_CP0_CAUSE][0])
  367. #define kvm_write_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] = (val))
  368. #define kvm_read_c0_guest_epc(cop0) (cop0->reg[MIPS_CP0_EXC_PC][0])
  369. #define kvm_write_c0_guest_epc(cop0, val) (cop0->reg[MIPS_CP0_EXC_PC][0] = (val))
  370. #define kvm_read_c0_guest_prid(cop0) (cop0->reg[MIPS_CP0_PRID][0])
  371. #define kvm_write_c0_guest_prid(cop0, val) (cop0->reg[MIPS_CP0_PRID][0] = (val))
  372. #define kvm_read_c0_guest_ebase(cop0) (cop0->reg[MIPS_CP0_PRID][1])
  373. #define kvm_write_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] = (val))
  374. #define kvm_read_c0_guest_config(cop0) (cop0->reg[MIPS_CP0_CONFIG][0])
  375. #define kvm_read_c0_guest_config1(cop0) (cop0->reg[MIPS_CP0_CONFIG][1])
  376. #define kvm_read_c0_guest_config2(cop0) (cop0->reg[MIPS_CP0_CONFIG][2])
  377. #define kvm_read_c0_guest_config3(cop0) (cop0->reg[MIPS_CP0_CONFIG][3])
  378. #define kvm_read_c0_guest_config7(cop0) (cop0->reg[MIPS_CP0_CONFIG][7])
  379. #define kvm_write_c0_guest_config(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][0] = (val))
  380. #define kvm_write_c0_guest_config1(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][1] = (val))
  381. #define kvm_write_c0_guest_config2(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][2] = (val))
  382. #define kvm_write_c0_guest_config3(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][3] = (val))
  383. #define kvm_write_c0_guest_config7(cop0, val) (cop0->reg[MIPS_CP0_CONFIG][7] = (val))
  384. #define kvm_read_c0_guest_errorepc(cop0) (cop0->reg[MIPS_CP0_ERROR_PC][0])
  385. #define kvm_write_c0_guest_errorepc(cop0, val) (cop0->reg[MIPS_CP0_ERROR_PC][0] = (val))
  386. #define kvm_set_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] |= (val))
  387. #define kvm_clear_c0_guest_status(cop0, val) (cop0->reg[MIPS_CP0_STATUS][0] &= ~(val))
  388. #define kvm_set_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] |= (val))
  389. #define kvm_clear_c0_guest_cause(cop0, val) (cop0->reg[MIPS_CP0_CAUSE][0] &= ~(val))
  390. #define kvm_change_c0_guest_cause(cop0, change, val) \
  391. { \
  392. kvm_clear_c0_guest_cause(cop0, change); \
  393. kvm_set_c0_guest_cause(cop0, ((val) & (change))); \
  394. }
  395. #define kvm_set_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] |= (val))
  396. #define kvm_clear_c0_guest_ebase(cop0, val) (cop0->reg[MIPS_CP0_PRID][1] &= ~(val))
  397. #define kvm_change_c0_guest_ebase(cop0, change, val) \
  398. { \
  399. kvm_clear_c0_guest_ebase(cop0, change); \
  400. kvm_set_c0_guest_ebase(cop0, ((val) & (change))); \
  401. }
  402. struct kvm_mips_callbacks {
  403. int (*handle_cop_unusable) (struct kvm_vcpu *vcpu);
  404. int (*handle_tlb_mod) (struct kvm_vcpu *vcpu);
  405. int (*handle_tlb_ld_miss) (struct kvm_vcpu *vcpu);
  406. int (*handle_tlb_st_miss) (struct kvm_vcpu *vcpu);
  407. int (*handle_addr_err_st) (struct kvm_vcpu *vcpu);
  408. int (*handle_addr_err_ld) (struct kvm_vcpu *vcpu);
  409. int (*handle_syscall) (struct kvm_vcpu *vcpu);
  410. int (*handle_res_inst) (struct kvm_vcpu *vcpu);
  411. int (*handle_break) (struct kvm_vcpu *vcpu);
  412. int (*vm_init) (struct kvm *kvm);
  413. int (*vcpu_init) (struct kvm_vcpu *vcpu);
  414. int (*vcpu_setup) (struct kvm_vcpu *vcpu);
  415. gpa_t(*gva_to_gpa) (gva_t gva);
  416. void (*queue_timer_int) (struct kvm_vcpu *vcpu);
  417. void (*dequeue_timer_int) (struct kvm_vcpu *vcpu);
  418. void (*queue_io_int) (struct kvm_vcpu *vcpu,
  419. struct kvm_mips_interrupt *irq);
  420. void (*dequeue_io_int) (struct kvm_vcpu *vcpu,
  421. struct kvm_mips_interrupt *irq);
  422. int (*irq_deliver) (struct kvm_vcpu *vcpu, unsigned int priority,
  423. uint32_t cause);
  424. int (*irq_clear) (struct kvm_vcpu *vcpu, unsigned int priority,
  425. uint32_t cause);
  426. };
  427. extern struct kvm_mips_callbacks *kvm_mips_callbacks;
  428. int kvm_mips_emulation_init(struct kvm_mips_callbacks **install_callbacks);
  429. /* Debug: dump vcpu state */
  430. int kvm_arch_vcpu_dump_regs(struct kvm_vcpu *vcpu);
  431. /* Trampoline ASM routine to start running in "Guest" context */
  432. extern int __kvm_mips_vcpu_run(struct kvm_run *run, struct kvm_vcpu *vcpu);
  433. /* TLB handling */
  434. uint32_t kvm_get_kernel_asid(struct kvm_vcpu *vcpu);
  435. uint32_t kvm_get_user_asid(struct kvm_vcpu *vcpu);
  436. uint32_t kvm_get_commpage_asid (struct kvm_vcpu *vcpu);
  437. extern int kvm_mips_handle_kseg0_tlb_fault(unsigned long badbaddr,
  438. struct kvm_vcpu *vcpu);
  439. extern int kvm_mips_handle_commpage_tlb_fault(unsigned long badvaddr,
  440. struct kvm_vcpu *vcpu);
  441. extern int kvm_mips_handle_mapped_seg_tlb_fault(struct kvm_vcpu *vcpu,
  442. struct kvm_mips_tlb *tlb,
  443. unsigned long *hpa0,
  444. unsigned long *hpa1);
  445. extern enum emulation_result kvm_mips_handle_tlbmiss(unsigned long cause,
  446. uint32_t *opc,
  447. struct kvm_run *run,
  448. struct kvm_vcpu *vcpu);
  449. extern enum emulation_result kvm_mips_handle_tlbmod(unsigned long cause,
  450. uint32_t *opc,
  451. struct kvm_run *run,
  452. struct kvm_vcpu *vcpu);
  453. extern void kvm_mips_dump_host_tlbs(void);
  454. extern void kvm_mips_dump_guest_tlbs(struct kvm_vcpu *vcpu);
  455. extern void kvm_mips_dump_shadow_tlbs(struct kvm_vcpu *vcpu);
  456. extern void kvm_mips_flush_host_tlb(int skip_kseg0);
  457. extern int kvm_mips_host_tlb_inv(struct kvm_vcpu *vcpu, unsigned long entryhi);
  458. extern int kvm_mips_host_tlb_inv_index(struct kvm_vcpu *vcpu, int index);
  459. extern int kvm_mips_guest_tlb_lookup(struct kvm_vcpu *vcpu,
  460. unsigned long entryhi);
  461. extern int kvm_mips_host_tlb_lookup(struct kvm_vcpu *vcpu, unsigned long vaddr);
  462. extern unsigned long kvm_mips_translate_guest_kseg0_to_hpa(struct kvm_vcpu *vcpu,
  463. unsigned long gva);
  464. extern void kvm_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu,
  465. struct kvm_vcpu *vcpu);
  466. extern void kvm_shadow_tlb_put(struct kvm_vcpu *vcpu);
  467. extern void kvm_shadow_tlb_load(struct kvm_vcpu *vcpu);
  468. extern void kvm_local_flush_tlb_all(void);
  469. extern void kvm_mips_init_shadow_tlb(struct kvm_vcpu *vcpu);
  470. extern void kvm_mips_alloc_new_mmu_context(struct kvm_vcpu *vcpu);
  471. extern void kvm_mips_vcpu_load(struct kvm_vcpu *vcpu, int cpu);
  472. extern void kvm_mips_vcpu_put(struct kvm_vcpu *vcpu);
  473. /* Emulation */
  474. uint32_t kvm_get_inst(uint32_t *opc, struct kvm_vcpu *vcpu);
  475. enum emulation_result update_pc(struct kvm_vcpu *vcpu, uint32_t cause);
  476. extern enum emulation_result kvm_mips_emulate_inst(unsigned long cause,
  477. uint32_t *opc,
  478. struct kvm_run *run,
  479. struct kvm_vcpu *vcpu);
  480. extern enum emulation_result kvm_mips_emulate_syscall(unsigned long cause,
  481. uint32_t *opc,
  482. struct kvm_run *run,
  483. struct kvm_vcpu *vcpu);
  484. extern enum emulation_result kvm_mips_emulate_tlbmiss_ld(unsigned long cause,
  485. uint32_t *opc,
  486. struct kvm_run *run,
  487. struct kvm_vcpu *vcpu);
  488. extern enum emulation_result kvm_mips_emulate_tlbinv_ld(unsigned long cause,
  489. uint32_t *opc,
  490. struct kvm_run *run,
  491. struct kvm_vcpu *vcpu);
  492. extern enum emulation_result kvm_mips_emulate_tlbmiss_st(unsigned long cause,
  493. uint32_t *opc,
  494. struct kvm_run *run,
  495. struct kvm_vcpu *vcpu);
  496. extern enum emulation_result kvm_mips_emulate_tlbinv_st(unsigned long cause,
  497. uint32_t *opc,
  498. struct kvm_run *run,
  499. struct kvm_vcpu *vcpu);
  500. extern enum emulation_result kvm_mips_emulate_tlbmod(unsigned long cause,
  501. uint32_t *opc,
  502. struct kvm_run *run,
  503. struct kvm_vcpu *vcpu);
  504. extern enum emulation_result kvm_mips_emulate_fpu_exc(unsigned long cause,
  505. uint32_t *opc,
  506. struct kvm_run *run,
  507. struct kvm_vcpu *vcpu);
  508. extern enum emulation_result kvm_mips_handle_ri(unsigned long cause,
  509. uint32_t *opc,
  510. struct kvm_run *run,
  511. struct kvm_vcpu *vcpu);
  512. extern enum emulation_result kvm_mips_emulate_ri_exc(unsigned long cause,
  513. uint32_t *opc,
  514. struct kvm_run *run,
  515. struct kvm_vcpu *vcpu);
  516. extern enum emulation_result kvm_mips_emulate_bp_exc(unsigned long cause,
  517. uint32_t *opc,
  518. struct kvm_run *run,
  519. struct kvm_vcpu *vcpu);
  520. extern enum emulation_result kvm_mips_complete_mmio_load(struct kvm_vcpu *vcpu,
  521. struct kvm_run *run);
  522. enum emulation_result kvm_mips_emulate_count(struct kvm_vcpu *vcpu);
  523. enum emulation_result kvm_mips_check_privilege(unsigned long cause,
  524. uint32_t *opc,
  525. struct kvm_run *run,
  526. struct kvm_vcpu *vcpu);
  527. enum emulation_result kvm_mips_emulate_cache(uint32_t inst,
  528. uint32_t *opc,
  529. uint32_t cause,
  530. struct kvm_run *run,
  531. struct kvm_vcpu *vcpu);
  532. enum emulation_result kvm_mips_emulate_CP0(uint32_t inst,
  533. uint32_t *opc,
  534. uint32_t cause,
  535. struct kvm_run *run,
  536. struct kvm_vcpu *vcpu);
  537. enum emulation_result kvm_mips_emulate_store(uint32_t inst,
  538. uint32_t cause,
  539. struct kvm_run *run,
  540. struct kvm_vcpu *vcpu);
  541. enum emulation_result kvm_mips_emulate_load(uint32_t inst,
  542. uint32_t cause,
  543. struct kvm_run *run,
  544. struct kvm_vcpu *vcpu);
  545. /* Dynamic binary translation */
  546. extern int kvm_mips_trans_cache_index(uint32_t inst, uint32_t *opc,
  547. struct kvm_vcpu *vcpu);
  548. extern int kvm_mips_trans_cache_va(uint32_t inst, uint32_t *opc,
  549. struct kvm_vcpu *vcpu);
  550. extern int kvm_mips_trans_mfc0(uint32_t inst, uint32_t *opc,
  551. struct kvm_vcpu *vcpu);
  552. extern int kvm_mips_trans_mtc0(uint32_t inst, uint32_t *opc,
  553. struct kvm_vcpu *vcpu);
  554. /* Misc */
  555. extern void mips32_SyncICache(unsigned long addr, unsigned long size);
  556. extern int kvm_mips_dump_stats(struct kvm_vcpu *vcpu);
  557. extern unsigned long kvm_mips_get_ramsize(struct kvm *kvm);
  558. #endif /* __MIPS_KVM_HOST_H__ */