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arch
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mips
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include
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asm
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branch.h

branch.h 1.7 KB
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  1. /*
    2. 

  2.  * This file is subject to the terms and conditions of the GNU General Public
    3. 

  3.  * License.  See the file "COPYING" in the main directory of this archive
    4. 

  4.  * for more details.
    5. 

  5.  *
    6. 

  6.  * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
    7. 

  7.  */
    8. 

  8. #ifndef _ASM_BRANCH_H
    9. 

  9. #define _ASM_BRANCH_H
    10. 

  10. 

  11. #include <asm/ptrace.h>
    12. 

  12. #include <asm/inst.h>
    13. 

  13. 

  14. extern int __isa_exception_epc(struct pt_regs *regs);
    15. 

  15. extern int __compute_return_epc(struct pt_regs *regs);
    16. 

  16. extern int __compute_return_epc_for_insn(struct pt_regs *regs,
    17. 

  17. 					 union mips_instruction insn);
    18. 

  18. extern int __microMIPS_compute_return_epc(struct pt_regs *regs);
    19. 

  19. extern int __MIPS16e_compute_return_epc(struct pt_regs *regs);
    20. 

  20. 

  21. 

  22. static inline int delay_slot(struct pt_regs *regs)
    23. 

  23. {
    24. 

  24. 	return regs->cp0_cause & CAUSEF_BD;
    25. 

  25. }
    26. 

  26. 

  27. static inline unsigned long exception_epc(struct pt_regs *regs)
    28. 

  28. {
    29. 

  29. 	if (likely(!delay_slot(regs)))
    30. 

  30. 		return regs->cp0_epc;
    31. 

  31. 

  32. 	if (get_isa16_mode(regs->cp0_epc))
    33. 

  33. 		return __isa_exception_epc(regs);
    34. 

  34. 

  35. 	return regs->cp0_epc + 4;
    36. 

  36. }
    37. 

  37. 

  38. #define BRANCH_LIKELY_TAKEN 0x0001
    39. 

  39. 

  40. static inline int compute_return_epc(struct pt_regs *regs)
    41. 

  41. {
    42. 

  42. 	if (get_isa16_mode(regs->cp0_epc)) {
    43. 

  43. 		if (cpu_has_mmips)
    44. 

  44. 			return __microMIPS_compute_return_epc(regs);
    45. 

  45. 		if (cpu_has_mips16)
    46. 

  46. 			return __MIPS16e_compute_return_epc(regs);
    47. 

  47. 		return regs->cp0_epc;
    48. 

  48. 	}
    49. 

  49. 

  50. 	if (!delay_slot(regs)) {
    51. 

  51. 		regs->cp0_epc += 4;
    52. 

  52. 		return 0;
    53. 

  53. 	}
    54. 

  54. 

  55. 	return __compute_return_epc(regs);
    56. 

  56. }
    57. 

  57. 

  58. static inline int MIPS16e_compute_return_epc(struct pt_regs *regs,
    59. 

  59. 					     union mips16e_instruction *inst)
    60. 

  60. {
    61. 

  61. 	if (likely(!delay_slot(regs))) {
    62. 

  62. 		if (inst->ri.opcode == MIPS16e_extend_op) {
    63. 

  63. 			regs->cp0_epc += 4;
    64. 

  64. 			return 0;
    65. 

  65. 		}
    66. 

  66. 		regs->cp0_epc += 2;
    67. 

  67. 		return 0;
    68. 

  68. 	}
    69. 

  69. 

  70. 	return __MIPS16e_compute_return_epc(regs);
    71. 

  71. }
    72. 

  72. 

  73. #endif /* _ASM_BRANCH_H */
    74.