pci.c 20 KB

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  1. /*
  2. * pci.c - Low-Level PCI Access in IA-64
  3. *
  4. * Derived from bios32.c of i386 tree.
  5. *
  6. * (c) Copyright 2002, 2005 Hewlett-Packard Development Company, L.P.
  7. * David Mosberger-Tang <davidm@hpl.hp.com>
  8. * Bjorn Helgaas <bjorn.helgaas@hp.com>
  9. * Copyright (C) 2004 Silicon Graphics, Inc.
  10. *
  11. * Note: Above list of copyright holders is incomplete...
  12. */
  13. #include <linux/acpi.h>
  14. #include <linux/types.h>
  15. #include <linux/kernel.h>
  16. #include <linux/pci.h>
  17. #include <linux/pci-acpi.h>
  18. #include <linux/init.h>
  19. #include <linux/ioport.h>
  20. #include <linux/slab.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/bootmem.h>
  23. #include <linux/export.h>
  24. #include <asm/machvec.h>
  25. #include <asm/page.h>
  26. #include <asm/io.h>
  27. #include <asm/sal.h>
  28. #include <asm/smp.h>
  29. #include <asm/irq.h>
  30. #include <asm/hw_irq.h>
  31. /*
  32. * Low-level SAL-based PCI configuration access functions. Note that SAL
  33. * calls are already serialized (via sal_lock), so we don't need another
  34. * synchronization mechanism here.
  35. */
  36. #define PCI_SAL_ADDRESS(seg, bus, devfn, reg) \
  37. (((u64) seg << 24) | (bus << 16) | (devfn << 8) | (reg))
  38. /* SAL 3.2 adds support for extended config space. */
  39. #define PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg) \
  40. (((u64) seg << 28) | (bus << 20) | (devfn << 12) | (reg))
  41. int raw_pci_read(unsigned int seg, unsigned int bus, unsigned int devfn,
  42. int reg, int len, u32 *value)
  43. {
  44. u64 addr, data = 0;
  45. int mode, result;
  46. if (!value || (seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  47. return -EINVAL;
  48. if ((seg | reg) <= 255) {
  49. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  50. mode = 0;
  51. } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  52. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  53. mode = 1;
  54. } else {
  55. return -EINVAL;
  56. }
  57. result = ia64_sal_pci_config_read(addr, mode, len, &data);
  58. if (result != 0)
  59. return -EINVAL;
  60. *value = (u32) data;
  61. return 0;
  62. }
  63. int raw_pci_write(unsigned int seg, unsigned int bus, unsigned int devfn,
  64. int reg, int len, u32 value)
  65. {
  66. u64 addr;
  67. int mode, result;
  68. if ((seg > 65535) || (bus > 255) || (devfn > 255) || (reg > 4095))
  69. return -EINVAL;
  70. if ((seg | reg) <= 255) {
  71. addr = PCI_SAL_ADDRESS(seg, bus, devfn, reg);
  72. mode = 0;
  73. } else if (sal_revision >= SAL_VERSION_CODE(3,2)) {
  74. addr = PCI_SAL_EXT_ADDRESS(seg, bus, devfn, reg);
  75. mode = 1;
  76. } else {
  77. return -EINVAL;
  78. }
  79. result = ia64_sal_pci_config_write(addr, mode, len, value);
  80. if (result != 0)
  81. return -EINVAL;
  82. return 0;
  83. }
  84. static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
  85. int size, u32 *value)
  86. {
  87. return raw_pci_read(pci_domain_nr(bus), bus->number,
  88. devfn, where, size, value);
  89. }
  90. static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
  91. int size, u32 value)
  92. {
  93. return raw_pci_write(pci_domain_nr(bus), bus->number,
  94. devfn, where, size, value);
  95. }
  96. struct pci_ops pci_root_ops = {
  97. .read = pci_read,
  98. .write = pci_write,
  99. };
  100. /* Called by ACPI when it finds a new root bus. */
  101. static struct pci_controller *alloc_pci_controller(int seg)
  102. {
  103. struct pci_controller *controller;
  104. controller = kzalloc(sizeof(*controller), GFP_KERNEL);
  105. if (!controller)
  106. return NULL;
  107. controller->segment = seg;
  108. controller->node = -1;
  109. return controller;
  110. }
  111. struct pci_root_info {
  112. struct acpi_device *bridge;
  113. struct pci_controller *controller;
  114. struct list_head resources;
  115. struct resource *res;
  116. resource_size_t *res_offset;
  117. unsigned int res_num;
  118. struct list_head io_resources;
  119. char *name;
  120. };
  121. static unsigned int
  122. new_space (u64 phys_base, int sparse)
  123. {
  124. u64 mmio_base;
  125. int i;
  126. if (phys_base == 0)
  127. return 0; /* legacy I/O port space */
  128. mmio_base = (u64) ioremap(phys_base, 0);
  129. for (i = 0; i < num_io_spaces; i++)
  130. if (io_space[i].mmio_base == mmio_base &&
  131. io_space[i].sparse == sparse)
  132. return i;
  133. if (num_io_spaces == MAX_IO_SPACES) {
  134. pr_err("PCI: Too many IO port spaces "
  135. "(MAX_IO_SPACES=%lu)\n", MAX_IO_SPACES);
  136. return ~0;
  137. }
  138. i = num_io_spaces++;
  139. io_space[i].mmio_base = mmio_base;
  140. io_space[i].sparse = sparse;
  141. return i;
  142. }
  143. static u64 add_io_space(struct pci_root_info *info,
  144. struct acpi_resource_address64 *addr)
  145. {
  146. struct iospace_resource *iospace;
  147. struct resource *resource;
  148. char *name;
  149. unsigned long base, min, max, base_port;
  150. unsigned int sparse = 0, space_nr, len;
  151. len = strlen(info->name) + 32;
  152. iospace = kzalloc(sizeof(*iospace) + len, GFP_KERNEL);
  153. if (!iospace) {
  154. dev_err(&info->bridge->dev,
  155. "PCI: No memory for %s I/O port space\n",
  156. info->name);
  157. goto out;
  158. }
  159. name = (char *)(iospace + 1);
  160. min = addr->minimum;
  161. max = min + addr->address_length - 1;
  162. if (addr->info.io.translation_type == ACPI_SPARSE_TRANSLATION)
  163. sparse = 1;
  164. space_nr = new_space(addr->translation_offset, sparse);
  165. if (space_nr == ~0)
  166. goto free_resource;
  167. base = __pa(io_space[space_nr].mmio_base);
  168. base_port = IO_SPACE_BASE(space_nr);
  169. snprintf(name, len, "%s I/O Ports %08lx-%08lx", info->name,
  170. base_port + min, base_port + max);
  171. /*
  172. * The SDM guarantees the legacy 0-64K space is sparse, but if the
  173. * mapping is done by the processor (not the bridge), ACPI may not
  174. * mark it as sparse.
  175. */
  176. if (space_nr == 0)
  177. sparse = 1;
  178. resource = &iospace->res;
  179. resource->name = name;
  180. resource->flags = IORESOURCE_MEM;
  181. resource->start = base + (sparse ? IO_SPACE_SPARSE_ENCODING(min) : min);
  182. resource->end = base + (sparse ? IO_SPACE_SPARSE_ENCODING(max) : max);
  183. if (insert_resource(&iomem_resource, resource)) {
  184. dev_err(&info->bridge->dev,
  185. "can't allocate host bridge io space resource %pR\n",
  186. resource);
  187. goto free_resource;
  188. }
  189. list_add_tail(&iospace->list, &info->io_resources);
  190. return base_port;
  191. free_resource:
  192. kfree(iospace);
  193. out:
  194. return ~0;
  195. }
  196. static acpi_status resource_to_window(struct acpi_resource *resource,
  197. struct acpi_resource_address64 *addr)
  198. {
  199. acpi_status status;
  200. /*
  201. * We're only interested in _CRS descriptors that are
  202. * - address space descriptors for memory or I/O space
  203. * - non-zero size
  204. * - producers, i.e., the address space is routed downstream,
  205. * not consumed by the bridge itself
  206. */
  207. status = acpi_resource_to_address64(resource, addr);
  208. if (ACPI_SUCCESS(status) &&
  209. (addr->resource_type == ACPI_MEMORY_RANGE ||
  210. addr->resource_type == ACPI_IO_RANGE) &&
  211. addr->address_length &&
  212. addr->producer_consumer == ACPI_PRODUCER)
  213. return AE_OK;
  214. return AE_ERROR;
  215. }
  216. static acpi_status count_window(struct acpi_resource *resource, void *data)
  217. {
  218. unsigned int *windows = (unsigned int *) data;
  219. struct acpi_resource_address64 addr;
  220. acpi_status status;
  221. status = resource_to_window(resource, &addr);
  222. if (ACPI_SUCCESS(status))
  223. (*windows)++;
  224. return AE_OK;
  225. }
  226. static acpi_status add_window(struct acpi_resource *res, void *data)
  227. {
  228. struct pci_root_info *info = data;
  229. struct resource *resource;
  230. struct acpi_resource_address64 addr;
  231. acpi_status status;
  232. unsigned long flags, offset = 0;
  233. struct resource *root;
  234. /* Return AE_OK for non-window resources to keep scanning for more */
  235. status = resource_to_window(res, &addr);
  236. if (!ACPI_SUCCESS(status))
  237. return AE_OK;
  238. if (addr.resource_type == ACPI_MEMORY_RANGE) {
  239. flags = IORESOURCE_MEM;
  240. root = &iomem_resource;
  241. offset = addr.translation_offset;
  242. } else if (addr.resource_type == ACPI_IO_RANGE) {
  243. flags = IORESOURCE_IO;
  244. root = &ioport_resource;
  245. offset = add_io_space(info, &addr);
  246. if (offset == ~0)
  247. return AE_OK;
  248. } else
  249. return AE_OK;
  250. resource = &info->res[info->res_num];
  251. resource->name = info->name;
  252. resource->flags = flags;
  253. resource->start = addr.minimum + offset;
  254. resource->end = resource->start + addr.address_length - 1;
  255. info->res_offset[info->res_num] = offset;
  256. if (insert_resource(root, resource)) {
  257. dev_err(&info->bridge->dev,
  258. "can't allocate host bridge window %pR\n",
  259. resource);
  260. } else {
  261. if (offset)
  262. dev_info(&info->bridge->dev, "host bridge window %pR "
  263. "(PCI address [%#llx-%#llx])\n",
  264. resource,
  265. resource->start - offset,
  266. resource->end - offset);
  267. else
  268. dev_info(&info->bridge->dev,
  269. "host bridge window %pR\n", resource);
  270. }
  271. /* HP's firmware has a hack to work around a Windows bug.
  272. * Ignore these tiny memory ranges */
  273. if (!((resource->flags & IORESOURCE_MEM) &&
  274. (resource->end - resource->start < 16)))
  275. pci_add_resource_offset(&info->resources, resource,
  276. info->res_offset[info->res_num]);
  277. info->res_num++;
  278. return AE_OK;
  279. }
  280. static void free_pci_root_info_res(struct pci_root_info *info)
  281. {
  282. struct iospace_resource *iospace, *tmp;
  283. list_for_each_entry_safe(iospace, tmp, &info->io_resources, list)
  284. kfree(iospace);
  285. kfree(info->name);
  286. kfree(info->res);
  287. info->res = NULL;
  288. kfree(info->res_offset);
  289. info->res_offset = NULL;
  290. info->res_num = 0;
  291. kfree(info->controller);
  292. info->controller = NULL;
  293. }
  294. static void __release_pci_root_info(struct pci_root_info *info)
  295. {
  296. int i;
  297. struct resource *res;
  298. struct iospace_resource *iospace;
  299. list_for_each_entry(iospace, &info->io_resources, list)
  300. release_resource(&iospace->res);
  301. for (i = 0; i < info->res_num; i++) {
  302. res = &info->res[i];
  303. if (!res->parent)
  304. continue;
  305. if (!(res->flags & (IORESOURCE_MEM | IORESOURCE_IO)))
  306. continue;
  307. release_resource(res);
  308. }
  309. free_pci_root_info_res(info);
  310. kfree(info);
  311. }
  312. static void release_pci_root_info(struct pci_host_bridge *bridge)
  313. {
  314. struct pci_root_info *info = bridge->release_data;
  315. __release_pci_root_info(info);
  316. }
  317. static int
  318. probe_pci_root_info(struct pci_root_info *info, struct acpi_device *device,
  319. int busnum, int domain)
  320. {
  321. char *name;
  322. name = kmalloc(16, GFP_KERNEL);
  323. if (!name)
  324. return -ENOMEM;
  325. sprintf(name, "PCI Bus %04x:%02x", domain, busnum);
  326. info->bridge = device;
  327. info->name = name;
  328. acpi_walk_resources(device->handle, METHOD_NAME__CRS, count_window,
  329. &info->res_num);
  330. if (info->res_num) {
  331. info->res =
  332. kzalloc_node(sizeof(*info->res) * info->res_num,
  333. GFP_KERNEL, info->controller->node);
  334. if (!info->res) {
  335. kfree(name);
  336. return -ENOMEM;
  337. }
  338. info->res_offset =
  339. kzalloc_node(sizeof(*info->res_offset) * info->res_num,
  340. GFP_KERNEL, info->controller->node);
  341. if (!info->res_offset) {
  342. kfree(name);
  343. kfree(info->res);
  344. info->res = NULL;
  345. return -ENOMEM;
  346. }
  347. info->res_num = 0;
  348. acpi_walk_resources(device->handle, METHOD_NAME__CRS,
  349. add_window, info);
  350. } else
  351. kfree(name);
  352. return 0;
  353. }
  354. struct pci_bus *pci_acpi_scan_root(struct acpi_pci_root *root)
  355. {
  356. struct acpi_device *device = root->device;
  357. int domain = root->segment;
  358. int bus = root->secondary.start;
  359. struct pci_controller *controller;
  360. struct pci_root_info *info = NULL;
  361. int busnum = root->secondary.start;
  362. struct pci_bus *pbus;
  363. int pxm, ret;
  364. controller = alloc_pci_controller(domain);
  365. if (!controller)
  366. return NULL;
  367. controller->acpi_handle = device->handle;
  368. pxm = acpi_get_pxm(controller->acpi_handle);
  369. #ifdef CONFIG_NUMA
  370. if (pxm >= 0)
  371. controller->node = pxm_to_node(pxm);
  372. #endif
  373. info = kzalloc(sizeof(*info), GFP_KERNEL);
  374. if (!info) {
  375. dev_err(&device->dev,
  376. "pci_bus %04x:%02x: ignored (out of memory)\n",
  377. domain, busnum);
  378. kfree(controller);
  379. return NULL;
  380. }
  381. info->controller = controller;
  382. INIT_LIST_HEAD(&info->io_resources);
  383. INIT_LIST_HEAD(&info->resources);
  384. ret = probe_pci_root_info(info, device, busnum, domain);
  385. if (ret) {
  386. kfree(info->controller);
  387. kfree(info);
  388. return NULL;
  389. }
  390. /* insert busn resource at first */
  391. pci_add_resource(&info->resources, &root->secondary);
  392. /*
  393. * See arch/x86/pci/acpi.c.
  394. * The desired pci bus might already be scanned in a quirk. We
  395. * should handle the case here, but it appears that IA64 hasn't
  396. * such quirk. So we just ignore the case now.
  397. */
  398. pbus = pci_create_root_bus(NULL, bus, &pci_root_ops, controller,
  399. &info->resources);
  400. if (!pbus) {
  401. pci_free_resource_list(&info->resources);
  402. __release_pci_root_info(info);
  403. return NULL;
  404. }
  405. pci_set_host_bridge_release(to_pci_host_bridge(pbus->bridge),
  406. release_pci_root_info, info);
  407. pci_scan_child_bus(pbus);
  408. return pbus;
  409. }
  410. int pcibios_root_bridge_prepare(struct pci_host_bridge *bridge)
  411. {
  412. struct pci_controller *controller = bridge->bus->sysdata;
  413. ACPI_HANDLE_SET(&bridge->dev, controller->acpi_handle);
  414. return 0;
  415. }
  416. static int is_valid_resource(struct pci_dev *dev, int idx)
  417. {
  418. unsigned int i, type_mask = IORESOURCE_IO | IORESOURCE_MEM;
  419. struct resource *devr = &dev->resource[idx], *busr;
  420. if (!dev->bus)
  421. return 0;
  422. pci_bus_for_each_resource(dev->bus, busr, i) {
  423. if (!busr || ((busr->flags ^ devr->flags) & type_mask))
  424. continue;
  425. if ((devr->start) && (devr->start >= busr->start) &&
  426. (devr->end <= busr->end))
  427. return 1;
  428. }
  429. return 0;
  430. }
  431. static void pcibios_fixup_resources(struct pci_dev *dev, int start, int limit)
  432. {
  433. int i;
  434. for (i = start; i < limit; i++) {
  435. if (!dev->resource[i].flags)
  436. continue;
  437. if ((is_valid_resource(dev, i)))
  438. pci_claim_resource(dev, i);
  439. }
  440. }
  441. void pcibios_fixup_device_resources(struct pci_dev *dev)
  442. {
  443. pcibios_fixup_resources(dev, 0, PCI_BRIDGE_RESOURCES);
  444. }
  445. EXPORT_SYMBOL_GPL(pcibios_fixup_device_resources);
  446. static void pcibios_fixup_bridge_resources(struct pci_dev *dev)
  447. {
  448. pcibios_fixup_resources(dev, PCI_BRIDGE_RESOURCES, PCI_NUM_RESOURCES);
  449. }
  450. /*
  451. * Called after each bus is probed, but before its children are examined.
  452. */
  453. void pcibios_fixup_bus(struct pci_bus *b)
  454. {
  455. struct pci_dev *dev;
  456. if (b->self) {
  457. pci_read_bridge_bases(b);
  458. pcibios_fixup_bridge_resources(b->self);
  459. }
  460. list_for_each_entry(dev, &b->devices, bus_list)
  461. pcibios_fixup_device_resources(dev);
  462. platform_pci_fixup_bus(b);
  463. }
  464. void pcibios_add_bus(struct pci_bus *bus)
  465. {
  466. acpi_pci_add_bus(bus);
  467. }
  468. void pcibios_remove_bus(struct pci_bus *bus)
  469. {
  470. acpi_pci_remove_bus(bus);
  471. }
  472. void pcibios_set_master (struct pci_dev *dev)
  473. {
  474. /* No special bus mastering setup handling */
  475. }
  476. int
  477. pcibios_enable_device (struct pci_dev *dev, int mask)
  478. {
  479. int ret;
  480. ret = pci_enable_resources(dev, mask);
  481. if (ret < 0)
  482. return ret;
  483. if (!dev->msi_enabled)
  484. return acpi_pci_irq_enable(dev);
  485. return 0;
  486. }
  487. void
  488. pcibios_disable_device (struct pci_dev *dev)
  489. {
  490. BUG_ON(atomic_read(&dev->enable_cnt));
  491. if (!dev->msi_enabled)
  492. acpi_pci_irq_disable(dev);
  493. }
  494. resource_size_t
  495. pcibios_align_resource (void *data, const struct resource *res,
  496. resource_size_t size, resource_size_t align)
  497. {
  498. return res->start;
  499. }
  500. int
  501. pci_mmap_page_range (struct pci_dev *dev, struct vm_area_struct *vma,
  502. enum pci_mmap_state mmap_state, int write_combine)
  503. {
  504. unsigned long size = vma->vm_end - vma->vm_start;
  505. pgprot_t prot;
  506. /*
  507. * I/O space cannot be accessed via normal processor loads and
  508. * stores on this platform.
  509. */
  510. if (mmap_state == pci_mmap_io)
  511. /*
  512. * XXX we could relax this for I/O spaces for which ACPI
  513. * indicates that the space is 1-to-1 mapped. But at the
  514. * moment, we don't support multiple PCI address spaces and
  515. * the legacy I/O space is not 1-to-1 mapped, so this is moot.
  516. */
  517. return -EINVAL;
  518. if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
  519. return -EINVAL;
  520. prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
  521. vma->vm_page_prot);
  522. /*
  523. * If the user requested WC, the kernel uses UC or WC for this region,
  524. * and the chipset supports WC, we can use WC. Otherwise, we have to
  525. * use the same attribute the kernel uses.
  526. */
  527. if (write_combine &&
  528. ((pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_UC ||
  529. (pgprot_val(prot) & _PAGE_MA_MASK) == _PAGE_MA_WC) &&
  530. efi_range_is_wc(vma->vm_start, vma->vm_end - vma->vm_start))
  531. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  532. else
  533. vma->vm_page_prot = prot;
  534. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  535. vma->vm_end - vma->vm_start, vma->vm_page_prot))
  536. return -EAGAIN;
  537. return 0;
  538. }
  539. /**
  540. * ia64_pci_get_legacy_mem - generic legacy mem routine
  541. * @bus: bus to get legacy memory base address for
  542. *
  543. * Find the base of legacy memory for @bus. This is typically the first
  544. * megabyte of bus address space for @bus or is simply 0 on platforms whose
  545. * chipsets support legacy I/O and memory routing. Returns the base address
  546. * or an error pointer if an error occurred.
  547. *
  548. * This is the ia64 generic version of this routine. Other platforms
  549. * are free to override it with a machine vector.
  550. */
  551. char *ia64_pci_get_legacy_mem(struct pci_bus *bus)
  552. {
  553. return (char *)__IA64_UNCACHED_OFFSET;
  554. }
  555. /**
  556. * pci_mmap_legacy_page_range - map legacy memory space to userland
  557. * @bus: bus whose legacy space we're mapping
  558. * @vma: vma passed in by mmap
  559. *
  560. * Map legacy memory space for this device back to userspace using a machine
  561. * vector to get the base address.
  562. */
  563. int
  564. pci_mmap_legacy_page_range(struct pci_bus *bus, struct vm_area_struct *vma,
  565. enum pci_mmap_state mmap_state)
  566. {
  567. unsigned long size = vma->vm_end - vma->vm_start;
  568. pgprot_t prot;
  569. char *addr;
  570. /* We only support mmap'ing of legacy memory space */
  571. if (mmap_state != pci_mmap_mem)
  572. return -ENOSYS;
  573. /*
  574. * Avoid attribute aliasing. See Documentation/ia64/aliasing.txt
  575. * for more details.
  576. */
  577. if (!valid_mmap_phys_addr_range(vma->vm_pgoff, size))
  578. return -EINVAL;
  579. prot = phys_mem_access_prot(NULL, vma->vm_pgoff, size,
  580. vma->vm_page_prot);
  581. addr = pci_get_legacy_mem(bus);
  582. if (IS_ERR(addr))
  583. return PTR_ERR(addr);
  584. vma->vm_pgoff += (unsigned long)addr >> PAGE_SHIFT;
  585. vma->vm_page_prot = prot;
  586. if (remap_pfn_range(vma, vma->vm_start, vma->vm_pgoff,
  587. size, vma->vm_page_prot))
  588. return -EAGAIN;
  589. return 0;
  590. }
  591. /**
  592. * ia64_pci_legacy_read - read from legacy I/O space
  593. * @bus: bus to read
  594. * @port: legacy port value
  595. * @val: caller allocated storage for returned value
  596. * @size: number of bytes to read
  597. *
  598. * Simply reads @size bytes from @port and puts the result in @val.
  599. *
  600. * Again, this (and the write routine) are generic versions that can be
  601. * overridden by the platform. This is necessary on platforms that don't
  602. * support legacy I/O routing or that hard fail on legacy I/O timeouts.
  603. */
  604. int ia64_pci_legacy_read(struct pci_bus *bus, u16 port, u32 *val, u8 size)
  605. {
  606. int ret = size;
  607. switch (size) {
  608. case 1:
  609. *val = inb(port);
  610. break;
  611. case 2:
  612. *val = inw(port);
  613. break;
  614. case 4:
  615. *val = inl(port);
  616. break;
  617. default:
  618. ret = -EINVAL;
  619. break;
  620. }
  621. return ret;
  622. }
  623. /**
  624. * ia64_pci_legacy_write - perform a legacy I/O write
  625. * @bus: bus pointer
  626. * @port: port to write
  627. * @val: value to write
  628. * @size: number of bytes to write from @val
  629. *
  630. * Simply writes @size bytes of @val to @port.
  631. */
  632. int ia64_pci_legacy_write(struct pci_bus *bus, u16 port, u32 val, u8 size)
  633. {
  634. int ret = size;
  635. switch (size) {
  636. case 1:
  637. outb(val, port);
  638. break;
  639. case 2:
  640. outw(val, port);
  641. break;
  642. case 4:
  643. outl(val, port);
  644. break;
  645. default:
  646. ret = -EINVAL;
  647. break;
  648. }
  649. return ret;
  650. }
  651. /**
  652. * set_pci_cacheline_size - determine cacheline size for PCI devices
  653. *
  654. * We want to use the line-size of the outer-most cache. We assume
  655. * that this line-size is the same for all CPUs.
  656. *
  657. * Code mostly taken from arch/ia64/kernel/palinfo.c:cache_info().
  658. */
  659. static void __init set_pci_dfl_cacheline_size(void)
  660. {
  661. unsigned long levels, unique_caches;
  662. long status;
  663. pal_cache_config_info_t cci;
  664. status = ia64_pal_cache_summary(&levels, &unique_caches);
  665. if (status != 0) {
  666. pr_err("%s: ia64_pal_cache_summary() failed "
  667. "(status=%ld)\n", __func__, status);
  668. return;
  669. }
  670. status = ia64_pal_cache_config_info(levels - 1,
  671. /* cache_type (data_or_unified)= */ 2, &cci);
  672. if (status != 0) {
  673. pr_err("%s: ia64_pal_cache_config_info() failed "
  674. "(status=%ld)\n", __func__, status);
  675. return;
  676. }
  677. pci_dfl_cache_line_size = (1 << cci.pcci_line_size) / 4;
  678. }
  679. u64 ia64_dma_get_required_mask(struct device *dev)
  680. {
  681. u32 low_totalram = ((max_pfn - 1) << PAGE_SHIFT);
  682. u32 high_totalram = ((max_pfn - 1) >> (32 - PAGE_SHIFT));
  683. u64 mask;
  684. if (!high_totalram) {
  685. /* convert to mask just covering totalram */
  686. low_totalram = (1 << (fls(low_totalram) - 1));
  687. low_totalram += low_totalram - 1;
  688. mask = low_totalram;
  689. } else {
  690. high_totalram = (1 << (fls(high_totalram) - 1));
  691. high_totalram += high_totalram - 1;
  692. mask = (((u64)high_totalram) << 32) + 0xffffffff;
  693. }
  694. return mask;
  695. }
  696. EXPORT_SYMBOL_GPL(ia64_dma_get_required_mask);
  697. u64 dma_get_required_mask(struct device *dev)
  698. {
  699. return platform_dma_get_required_mask(dev);
  700. }
  701. EXPORT_SYMBOL_GPL(dma_get_required_mask);
  702. static int __init pcibios_init(void)
  703. {
  704. set_pci_dfl_cacheline_size();
  705. return 0;
  706. }
  707. subsys_initcall(pcibios_init);