devs.c 39 KB

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  1. /* linux/arch/arm/plat-samsung/devs.c
  2. *
  3. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  4. * http://www.samsung.com
  5. *
  6. * Base SAMSUNG platform device definitions
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/amba/pl330.h>
  13. #include <linux/kernel.h>
  14. #include <linux/types.h>
  15. #include <linux/interrupt.h>
  16. #include <linux/list.h>
  17. #include <linux/timer.h>
  18. #include <linux/init.h>
  19. #include <linux/serial_core.h>
  20. #include <linux/platform_device.h>
  21. #include <linux/io.h>
  22. #include <linux/slab.h>
  23. #include <linux/string.h>
  24. #include <linux/dma-mapping.h>
  25. #include <linux/fb.h>
  26. #include <linux/gfp.h>
  27. #include <linux/mtd/mtd.h>
  28. #include <linux/mtd/onenand.h>
  29. #include <linux/mtd/partitions.h>
  30. #include <linux/mmc/host.h>
  31. #include <linux/ioport.h>
  32. #include <linux/platform_data/s3c-hsudc.h>
  33. #include <linux/platform_data/s3c-hsotg.h>
  34. #include <media/s5p_hdmi.h>
  35. #include <asm/irq.h>
  36. #include <asm/mach/arch.h>
  37. #include <asm/mach/map.h>
  38. #include <asm/mach/irq.h>
  39. #include <mach/hardware.h>
  40. #include <mach/dma.h>
  41. #include <mach/irqs.h>
  42. #include <mach/map.h>
  43. #include <plat/cpu.h>
  44. #include <plat/devs.h>
  45. #include <plat/adc.h>
  46. #include <linux/platform_data/ata-samsung_cf.h>
  47. #include <linux/platform_data/usb-ehci-s5p.h>
  48. #include <plat/fb.h>
  49. #include <plat/fb-s3c2410.h>
  50. #include <plat/hdmi.h>
  51. #include <linux/platform_data/hwmon-s3c.h>
  52. #include <linux/platform_data/i2c-s3c2410.h>
  53. #include <plat/keypad.h>
  54. #include <linux/platform_data/mmc-s3cmci.h>
  55. #include <linux/platform_data/mtd-nand-s3c2410.h>
  56. #include <plat/sdhci.h>
  57. #include <linux/platform_data/touchscreen-s3c2410.h>
  58. #include <linux/platform_data/usb-s3c2410_udc.h>
  59. #include <linux/platform_data/usb-ohci-s3c2410.h>
  60. #include <plat/usb-phy.h>
  61. #include <plat/regs-serial.h>
  62. #include <plat/regs-spi.h>
  63. #include <linux/platform_data/spi-s3c64xx.h>
  64. static u64 samsung_device_dma_mask = DMA_BIT_MASK(32);
  65. /* AC97 */
  66. #ifdef CONFIG_CPU_S3C2440
  67. static struct resource s3c_ac97_resource[] = {
  68. [0] = DEFINE_RES_MEM(S3C2440_PA_AC97, S3C2440_SZ_AC97),
  69. [1] = DEFINE_RES_IRQ(IRQ_S3C244X_AC97),
  70. [2] = DEFINE_RES_DMA_NAMED(DMACH_PCM_OUT, "PCM out"),
  71. [3] = DEFINE_RES_DMA_NAMED(DMACH_PCM_IN, "PCM in"),
  72. [4] = DEFINE_RES_DMA_NAMED(DMACH_MIC_IN, "Mic in"),
  73. };
  74. struct platform_device s3c_device_ac97 = {
  75. .name = "samsung-ac97",
  76. .id = -1,
  77. .num_resources = ARRAY_SIZE(s3c_ac97_resource),
  78. .resource = s3c_ac97_resource,
  79. .dev = {
  80. .dma_mask = &samsung_device_dma_mask,
  81. .coherent_dma_mask = DMA_BIT_MASK(32),
  82. }
  83. };
  84. #endif /* CONFIG_CPU_S3C2440 */
  85. /* ADC */
  86. #ifdef CONFIG_PLAT_S3C24XX
  87. static struct resource s3c_adc_resource[] = {
  88. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  89. [1] = DEFINE_RES_IRQ(IRQ_TC),
  90. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  91. };
  92. struct platform_device s3c_device_adc = {
  93. .name = "s3c24xx-adc",
  94. .id = -1,
  95. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  96. .resource = s3c_adc_resource,
  97. };
  98. #endif /* CONFIG_PLAT_S3C24XX */
  99. #if defined(CONFIG_SAMSUNG_DEV_ADC)
  100. static struct resource s3c_adc_resource[] = {
  101. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  102. [1] = DEFINE_RES_IRQ(IRQ_TC),
  103. [2] = DEFINE_RES_IRQ(IRQ_ADC),
  104. };
  105. struct platform_device s3c_device_adc = {
  106. .name = "samsung-adc",
  107. .id = -1,
  108. .num_resources = ARRAY_SIZE(s3c_adc_resource),
  109. .resource = s3c_adc_resource,
  110. };
  111. #endif /* CONFIG_SAMSUNG_DEV_ADC */
  112. /* Camif Controller */
  113. #ifdef CONFIG_CPU_S3C2440
  114. static struct resource s3c_camif_resource[] = {
  115. [0] = DEFINE_RES_MEM(S3C2440_PA_CAMIF, S3C2440_SZ_CAMIF),
  116. [1] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_C),
  117. [2] = DEFINE_RES_IRQ(IRQ_S3C2440_CAM_P),
  118. };
  119. struct platform_device s3c_device_camif = {
  120. .name = "s3c2440-camif",
  121. .id = -1,
  122. .num_resources = ARRAY_SIZE(s3c_camif_resource),
  123. .resource = s3c_camif_resource,
  124. .dev = {
  125. .dma_mask = &samsung_device_dma_mask,
  126. .coherent_dma_mask = DMA_BIT_MASK(32),
  127. }
  128. };
  129. #endif /* CONFIG_CPU_S3C2440 */
  130. /* ASOC DMA */
  131. #ifdef CONFIG_PLAT_S5P
  132. static struct resource samsung_asoc_idma_resource = DEFINE_RES_IRQ(IRQ_I2S0);
  133. struct platform_device samsung_asoc_idma = {
  134. .name = "samsung-idma",
  135. .id = -1,
  136. .num_resources = 1,
  137. .resource = &samsung_asoc_idma_resource,
  138. .dev = {
  139. .dma_mask = &samsung_device_dma_mask,
  140. .coherent_dma_mask = DMA_BIT_MASK(32),
  141. }
  142. };
  143. #endif
  144. /* FB */
  145. #ifdef CONFIG_S3C_DEV_FB
  146. static struct resource s3c_fb_resource[] = {
  147. [0] = DEFINE_RES_MEM(S3C_PA_FB, SZ_16K),
  148. [1] = DEFINE_RES_IRQ(IRQ_LCD_VSYNC),
  149. [2] = DEFINE_RES_IRQ(IRQ_LCD_FIFO),
  150. [3] = DEFINE_RES_IRQ(IRQ_LCD_SYSTEM),
  151. };
  152. struct platform_device s3c_device_fb = {
  153. .name = "s3c-fb",
  154. .id = -1,
  155. .num_resources = ARRAY_SIZE(s3c_fb_resource),
  156. .resource = s3c_fb_resource,
  157. .dev = {
  158. .dma_mask = &samsung_device_dma_mask,
  159. .coherent_dma_mask = DMA_BIT_MASK(32),
  160. },
  161. };
  162. void __init s3c_fb_set_platdata(struct s3c_fb_platdata *pd)
  163. {
  164. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  165. &s3c_device_fb);
  166. }
  167. #endif /* CONFIG_S3C_DEV_FB */
  168. /* FIMC */
  169. #ifdef CONFIG_S5P_DEV_FIMC0
  170. static struct resource s5p_fimc0_resource[] = {
  171. [0] = DEFINE_RES_MEM(S5P_PA_FIMC0, SZ_4K),
  172. [1] = DEFINE_RES_IRQ(IRQ_FIMC0),
  173. };
  174. struct platform_device s5p_device_fimc0 = {
  175. .name = "s5p-fimc",
  176. .id = 0,
  177. .num_resources = ARRAY_SIZE(s5p_fimc0_resource),
  178. .resource = s5p_fimc0_resource,
  179. .dev = {
  180. .dma_mask = &samsung_device_dma_mask,
  181. .coherent_dma_mask = DMA_BIT_MASK(32),
  182. },
  183. };
  184. struct platform_device s5p_device_fimc_md = {
  185. .name = "s5p-fimc-md",
  186. .id = -1,
  187. };
  188. #endif /* CONFIG_S5P_DEV_FIMC0 */
  189. #ifdef CONFIG_S5P_DEV_FIMC1
  190. static struct resource s5p_fimc1_resource[] = {
  191. [0] = DEFINE_RES_MEM(S5P_PA_FIMC1, SZ_4K),
  192. [1] = DEFINE_RES_IRQ(IRQ_FIMC1),
  193. };
  194. struct platform_device s5p_device_fimc1 = {
  195. .name = "s5p-fimc",
  196. .id = 1,
  197. .num_resources = ARRAY_SIZE(s5p_fimc1_resource),
  198. .resource = s5p_fimc1_resource,
  199. .dev = {
  200. .dma_mask = &samsung_device_dma_mask,
  201. .coherent_dma_mask = DMA_BIT_MASK(32),
  202. },
  203. };
  204. #endif /* CONFIG_S5P_DEV_FIMC1 */
  205. #ifdef CONFIG_S5P_DEV_FIMC2
  206. static struct resource s5p_fimc2_resource[] = {
  207. [0] = DEFINE_RES_MEM(S5P_PA_FIMC2, SZ_4K),
  208. [1] = DEFINE_RES_IRQ(IRQ_FIMC2),
  209. };
  210. struct platform_device s5p_device_fimc2 = {
  211. .name = "s5p-fimc",
  212. .id = 2,
  213. .num_resources = ARRAY_SIZE(s5p_fimc2_resource),
  214. .resource = s5p_fimc2_resource,
  215. .dev = {
  216. .dma_mask = &samsung_device_dma_mask,
  217. .coherent_dma_mask = DMA_BIT_MASK(32),
  218. },
  219. };
  220. #endif /* CONFIG_S5P_DEV_FIMC2 */
  221. #ifdef CONFIG_S5P_DEV_FIMC3
  222. static struct resource s5p_fimc3_resource[] = {
  223. [0] = DEFINE_RES_MEM(S5P_PA_FIMC3, SZ_4K),
  224. [1] = DEFINE_RES_IRQ(IRQ_FIMC3),
  225. };
  226. struct platform_device s5p_device_fimc3 = {
  227. .name = "s5p-fimc",
  228. .id = 3,
  229. .num_resources = ARRAY_SIZE(s5p_fimc3_resource),
  230. .resource = s5p_fimc3_resource,
  231. .dev = {
  232. .dma_mask = &samsung_device_dma_mask,
  233. .coherent_dma_mask = DMA_BIT_MASK(32),
  234. },
  235. };
  236. #endif /* CONFIG_S5P_DEV_FIMC3 */
  237. /* G2D */
  238. #ifdef CONFIG_S5P_DEV_G2D
  239. static struct resource s5p_g2d_resource[] = {
  240. [0] = DEFINE_RES_MEM(S5P_PA_G2D, SZ_4K),
  241. [1] = DEFINE_RES_IRQ(IRQ_2D),
  242. };
  243. struct platform_device s5p_device_g2d = {
  244. .name = "s5p-g2d",
  245. .id = 0,
  246. .num_resources = ARRAY_SIZE(s5p_g2d_resource),
  247. .resource = s5p_g2d_resource,
  248. .dev = {
  249. .dma_mask = &samsung_device_dma_mask,
  250. .coherent_dma_mask = DMA_BIT_MASK(32),
  251. },
  252. };
  253. #endif /* CONFIG_S5P_DEV_G2D */
  254. #ifdef CONFIG_S5P_DEV_JPEG
  255. static struct resource s5p_jpeg_resource[] = {
  256. [0] = DEFINE_RES_MEM(S5P_PA_JPEG, SZ_4K),
  257. [1] = DEFINE_RES_IRQ(IRQ_JPEG),
  258. };
  259. struct platform_device s5p_device_jpeg = {
  260. .name = "s5p-jpeg",
  261. .id = 0,
  262. .num_resources = ARRAY_SIZE(s5p_jpeg_resource),
  263. .resource = s5p_jpeg_resource,
  264. .dev = {
  265. .dma_mask = &samsung_device_dma_mask,
  266. .coherent_dma_mask = DMA_BIT_MASK(32),
  267. },
  268. };
  269. #endif /* CONFIG_S5P_DEV_JPEG */
  270. /* FIMD0 */
  271. #ifdef CONFIG_S5P_DEV_FIMD0
  272. static struct resource s5p_fimd0_resource[] = {
  273. [0] = DEFINE_RES_MEM(S5P_PA_FIMD0, SZ_32K),
  274. [1] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_VSYNC, "vsync"),
  275. [2] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_FIFO, "fifo"),
  276. [3] = DEFINE_RES_IRQ_NAMED(IRQ_FIMD0_SYSTEM, "lcd_sys"),
  277. };
  278. struct platform_device s5p_device_fimd0 = {
  279. .name = "s5p-fb",
  280. .id = 0,
  281. .num_resources = ARRAY_SIZE(s5p_fimd0_resource),
  282. .resource = s5p_fimd0_resource,
  283. .dev = {
  284. .dma_mask = &samsung_device_dma_mask,
  285. .coherent_dma_mask = DMA_BIT_MASK(32),
  286. },
  287. };
  288. void __init s5p_fimd0_set_platdata(struct s3c_fb_platdata *pd)
  289. {
  290. s3c_set_platdata(pd, sizeof(struct s3c_fb_platdata),
  291. &s5p_device_fimd0);
  292. }
  293. #endif /* CONFIG_S5P_DEV_FIMD0 */
  294. /* HWMON */
  295. #ifdef CONFIG_S3C_DEV_HWMON
  296. struct platform_device s3c_device_hwmon = {
  297. .name = "s3c-hwmon",
  298. .id = -1,
  299. .dev.parent = &s3c_device_adc.dev,
  300. };
  301. void __init s3c_hwmon_set_platdata(struct s3c_hwmon_pdata *pd)
  302. {
  303. s3c_set_platdata(pd, sizeof(struct s3c_hwmon_pdata),
  304. &s3c_device_hwmon);
  305. }
  306. #endif /* CONFIG_S3C_DEV_HWMON */
  307. /* HSMMC */
  308. #ifdef CONFIG_S3C_DEV_HSMMC
  309. static struct resource s3c_hsmmc_resource[] = {
  310. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC0, SZ_4K),
  311. [1] = DEFINE_RES_IRQ(IRQ_HSMMC0),
  312. };
  313. struct s3c_sdhci_platdata s3c_hsmmc0_def_platdata = {
  314. .max_width = 4,
  315. .host_caps = (MMC_CAP_4_BIT_DATA |
  316. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  317. };
  318. struct platform_device s3c_device_hsmmc0 = {
  319. .name = "s3c-sdhci",
  320. .id = 0,
  321. .num_resources = ARRAY_SIZE(s3c_hsmmc_resource),
  322. .resource = s3c_hsmmc_resource,
  323. .dev = {
  324. .dma_mask = &samsung_device_dma_mask,
  325. .coherent_dma_mask = DMA_BIT_MASK(32),
  326. .platform_data = &s3c_hsmmc0_def_platdata,
  327. },
  328. };
  329. void s3c_sdhci0_set_platdata(struct s3c_sdhci_platdata *pd)
  330. {
  331. s3c_sdhci_set_platdata(pd, &s3c_hsmmc0_def_platdata);
  332. }
  333. #endif /* CONFIG_S3C_DEV_HSMMC */
  334. #ifdef CONFIG_S3C_DEV_HSMMC1
  335. static struct resource s3c_hsmmc1_resource[] = {
  336. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC1, SZ_4K),
  337. [1] = DEFINE_RES_IRQ(IRQ_HSMMC1),
  338. };
  339. struct s3c_sdhci_platdata s3c_hsmmc1_def_platdata = {
  340. .max_width = 4,
  341. .host_caps = (MMC_CAP_4_BIT_DATA |
  342. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  343. };
  344. struct platform_device s3c_device_hsmmc1 = {
  345. .name = "s3c-sdhci",
  346. .id = 1,
  347. .num_resources = ARRAY_SIZE(s3c_hsmmc1_resource),
  348. .resource = s3c_hsmmc1_resource,
  349. .dev = {
  350. .dma_mask = &samsung_device_dma_mask,
  351. .coherent_dma_mask = DMA_BIT_MASK(32),
  352. .platform_data = &s3c_hsmmc1_def_platdata,
  353. },
  354. };
  355. void s3c_sdhci1_set_platdata(struct s3c_sdhci_platdata *pd)
  356. {
  357. s3c_sdhci_set_platdata(pd, &s3c_hsmmc1_def_platdata);
  358. }
  359. #endif /* CONFIG_S3C_DEV_HSMMC1 */
  360. /* HSMMC2 */
  361. #ifdef CONFIG_S3C_DEV_HSMMC2
  362. static struct resource s3c_hsmmc2_resource[] = {
  363. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC2, SZ_4K),
  364. [1] = DEFINE_RES_IRQ(IRQ_HSMMC2),
  365. };
  366. struct s3c_sdhci_platdata s3c_hsmmc2_def_platdata = {
  367. .max_width = 4,
  368. .host_caps = (MMC_CAP_4_BIT_DATA |
  369. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  370. };
  371. struct platform_device s3c_device_hsmmc2 = {
  372. .name = "s3c-sdhci",
  373. .id = 2,
  374. .num_resources = ARRAY_SIZE(s3c_hsmmc2_resource),
  375. .resource = s3c_hsmmc2_resource,
  376. .dev = {
  377. .dma_mask = &samsung_device_dma_mask,
  378. .coherent_dma_mask = DMA_BIT_MASK(32),
  379. .platform_data = &s3c_hsmmc2_def_platdata,
  380. },
  381. };
  382. void s3c_sdhci2_set_platdata(struct s3c_sdhci_platdata *pd)
  383. {
  384. s3c_sdhci_set_platdata(pd, &s3c_hsmmc2_def_platdata);
  385. }
  386. #endif /* CONFIG_S3C_DEV_HSMMC2 */
  387. #ifdef CONFIG_S3C_DEV_HSMMC3
  388. static struct resource s3c_hsmmc3_resource[] = {
  389. [0] = DEFINE_RES_MEM(S3C_PA_HSMMC3, SZ_4K),
  390. [1] = DEFINE_RES_IRQ(IRQ_HSMMC3),
  391. };
  392. struct s3c_sdhci_platdata s3c_hsmmc3_def_platdata = {
  393. .max_width = 4,
  394. .host_caps = (MMC_CAP_4_BIT_DATA |
  395. MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED),
  396. };
  397. struct platform_device s3c_device_hsmmc3 = {
  398. .name = "s3c-sdhci",
  399. .id = 3,
  400. .num_resources = ARRAY_SIZE(s3c_hsmmc3_resource),
  401. .resource = s3c_hsmmc3_resource,
  402. .dev = {
  403. .dma_mask = &samsung_device_dma_mask,
  404. .coherent_dma_mask = DMA_BIT_MASK(32),
  405. .platform_data = &s3c_hsmmc3_def_platdata,
  406. },
  407. };
  408. void s3c_sdhci3_set_platdata(struct s3c_sdhci_platdata *pd)
  409. {
  410. s3c_sdhci_set_platdata(pd, &s3c_hsmmc3_def_platdata);
  411. }
  412. #endif /* CONFIG_S3C_DEV_HSMMC3 */
  413. /* I2C */
  414. static struct resource s3c_i2c0_resource[] = {
  415. [0] = DEFINE_RES_MEM(S3C_PA_IIC, SZ_4K),
  416. [1] = DEFINE_RES_IRQ(IRQ_IIC),
  417. };
  418. struct platform_device s3c_device_i2c0 = {
  419. .name = "s3c2410-i2c",
  420. .id = 0,
  421. .num_resources = ARRAY_SIZE(s3c_i2c0_resource),
  422. .resource = s3c_i2c0_resource,
  423. };
  424. struct s3c2410_platform_i2c default_i2c_data __initdata = {
  425. .flags = 0,
  426. .slave_addr = 0x10,
  427. .frequency = 100*1000,
  428. .sda_delay = 100,
  429. };
  430. void __init s3c_i2c0_set_platdata(struct s3c2410_platform_i2c *pd)
  431. {
  432. struct s3c2410_platform_i2c *npd;
  433. if (!pd) {
  434. pd = &default_i2c_data;
  435. pd->bus_num = 0;
  436. }
  437. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  438. &s3c_device_i2c0);
  439. if (!npd->cfg_gpio)
  440. npd->cfg_gpio = s3c_i2c0_cfg_gpio;
  441. }
  442. #ifdef CONFIG_S3C_DEV_I2C1
  443. static struct resource s3c_i2c1_resource[] = {
  444. [0] = DEFINE_RES_MEM(S3C_PA_IIC1, SZ_4K),
  445. [1] = DEFINE_RES_IRQ(IRQ_IIC1),
  446. };
  447. struct platform_device s3c_device_i2c1 = {
  448. .name = "s3c2410-i2c",
  449. .id = 1,
  450. .num_resources = ARRAY_SIZE(s3c_i2c1_resource),
  451. .resource = s3c_i2c1_resource,
  452. };
  453. void __init s3c_i2c1_set_platdata(struct s3c2410_platform_i2c *pd)
  454. {
  455. struct s3c2410_platform_i2c *npd;
  456. if (!pd) {
  457. pd = &default_i2c_data;
  458. pd->bus_num = 1;
  459. }
  460. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  461. &s3c_device_i2c1);
  462. if (!npd->cfg_gpio)
  463. npd->cfg_gpio = s3c_i2c1_cfg_gpio;
  464. }
  465. #endif /* CONFIG_S3C_DEV_I2C1 */
  466. #ifdef CONFIG_S3C_DEV_I2C2
  467. static struct resource s3c_i2c2_resource[] = {
  468. [0] = DEFINE_RES_MEM(S3C_PA_IIC2, SZ_4K),
  469. [1] = DEFINE_RES_IRQ(IRQ_IIC2),
  470. };
  471. struct platform_device s3c_device_i2c2 = {
  472. .name = "s3c2410-i2c",
  473. .id = 2,
  474. .num_resources = ARRAY_SIZE(s3c_i2c2_resource),
  475. .resource = s3c_i2c2_resource,
  476. };
  477. void __init s3c_i2c2_set_platdata(struct s3c2410_platform_i2c *pd)
  478. {
  479. struct s3c2410_platform_i2c *npd;
  480. if (!pd) {
  481. pd = &default_i2c_data;
  482. pd->bus_num = 2;
  483. }
  484. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  485. &s3c_device_i2c2);
  486. if (!npd->cfg_gpio)
  487. npd->cfg_gpio = s3c_i2c2_cfg_gpio;
  488. }
  489. #endif /* CONFIG_S3C_DEV_I2C2 */
  490. #ifdef CONFIG_S3C_DEV_I2C3
  491. static struct resource s3c_i2c3_resource[] = {
  492. [0] = DEFINE_RES_MEM(S3C_PA_IIC3, SZ_4K),
  493. [1] = DEFINE_RES_IRQ(IRQ_IIC3),
  494. };
  495. struct platform_device s3c_device_i2c3 = {
  496. .name = "s3c2440-i2c",
  497. .id = 3,
  498. .num_resources = ARRAY_SIZE(s3c_i2c3_resource),
  499. .resource = s3c_i2c3_resource,
  500. };
  501. void __init s3c_i2c3_set_platdata(struct s3c2410_platform_i2c *pd)
  502. {
  503. struct s3c2410_platform_i2c *npd;
  504. if (!pd) {
  505. pd = &default_i2c_data;
  506. pd->bus_num = 3;
  507. }
  508. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  509. &s3c_device_i2c3);
  510. if (!npd->cfg_gpio)
  511. npd->cfg_gpio = s3c_i2c3_cfg_gpio;
  512. }
  513. #endif /*CONFIG_S3C_DEV_I2C3 */
  514. #ifdef CONFIG_S3C_DEV_I2C4
  515. static struct resource s3c_i2c4_resource[] = {
  516. [0] = DEFINE_RES_MEM(S3C_PA_IIC4, SZ_4K),
  517. [1] = DEFINE_RES_IRQ(IRQ_IIC4),
  518. };
  519. struct platform_device s3c_device_i2c4 = {
  520. .name = "s3c2440-i2c",
  521. .id = 4,
  522. .num_resources = ARRAY_SIZE(s3c_i2c4_resource),
  523. .resource = s3c_i2c4_resource,
  524. };
  525. void __init s3c_i2c4_set_platdata(struct s3c2410_platform_i2c *pd)
  526. {
  527. struct s3c2410_platform_i2c *npd;
  528. if (!pd) {
  529. pd = &default_i2c_data;
  530. pd->bus_num = 4;
  531. }
  532. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  533. &s3c_device_i2c4);
  534. if (!npd->cfg_gpio)
  535. npd->cfg_gpio = s3c_i2c4_cfg_gpio;
  536. }
  537. #endif /*CONFIG_S3C_DEV_I2C4 */
  538. #ifdef CONFIG_S3C_DEV_I2C5
  539. static struct resource s3c_i2c5_resource[] = {
  540. [0] = DEFINE_RES_MEM(S3C_PA_IIC5, SZ_4K),
  541. [1] = DEFINE_RES_IRQ(IRQ_IIC5),
  542. };
  543. struct platform_device s3c_device_i2c5 = {
  544. .name = "s3c2440-i2c",
  545. .id = 5,
  546. .num_resources = ARRAY_SIZE(s3c_i2c5_resource),
  547. .resource = s3c_i2c5_resource,
  548. };
  549. void __init s3c_i2c5_set_platdata(struct s3c2410_platform_i2c *pd)
  550. {
  551. struct s3c2410_platform_i2c *npd;
  552. if (!pd) {
  553. pd = &default_i2c_data;
  554. pd->bus_num = 5;
  555. }
  556. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  557. &s3c_device_i2c5);
  558. if (!npd->cfg_gpio)
  559. npd->cfg_gpio = s3c_i2c5_cfg_gpio;
  560. }
  561. #endif /*CONFIG_S3C_DEV_I2C5 */
  562. #ifdef CONFIG_S3C_DEV_I2C6
  563. static struct resource s3c_i2c6_resource[] = {
  564. [0] = DEFINE_RES_MEM(S3C_PA_IIC6, SZ_4K),
  565. [1] = DEFINE_RES_IRQ(IRQ_IIC6),
  566. };
  567. struct platform_device s3c_device_i2c6 = {
  568. .name = "s3c2440-i2c",
  569. .id = 6,
  570. .num_resources = ARRAY_SIZE(s3c_i2c6_resource),
  571. .resource = s3c_i2c6_resource,
  572. };
  573. void __init s3c_i2c6_set_platdata(struct s3c2410_platform_i2c *pd)
  574. {
  575. struct s3c2410_platform_i2c *npd;
  576. if (!pd) {
  577. pd = &default_i2c_data;
  578. pd->bus_num = 6;
  579. }
  580. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  581. &s3c_device_i2c6);
  582. if (!npd->cfg_gpio)
  583. npd->cfg_gpio = s3c_i2c6_cfg_gpio;
  584. }
  585. #endif /* CONFIG_S3C_DEV_I2C6 */
  586. #ifdef CONFIG_S3C_DEV_I2C7
  587. static struct resource s3c_i2c7_resource[] = {
  588. [0] = DEFINE_RES_MEM(S3C_PA_IIC7, SZ_4K),
  589. [1] = DEFINE_RES_IRQ(IRQ_IIC7),
  590. };
  591. struct platform_device s3c_device_i2c7 = {
  592. .name = "s3c2440-i2c",
  593. .id = 7,
  594. .num_resources = ARRAY_SIZE(s3c_i2c7_resource),
  595. .resource = s3c_i2c7_resource,
  596. };
  597. void __init s3c_i2c7_set_platdata(struct s3c2410_platform_i2c *pd)
  598. {
  599. struct s3c2410_platform_i2c *npd;
  600. if (!pd) {
  601. pd = &default_i2c_data;
  602. pd->bus_num = 7;
  603. }
  604. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  605. &s3c_device_i2c7);
  606. if (!npd->cfg_gpio)
  607. npd->cfg_gpio = s3c_i2c7_cfg_gpio;
  608. }
  609. #endif /* CONFIG_S3C_DEV_I2C7 */
  610. /* I2C HDMIPHY */
  611. #ifdef CONFIG_S5P_DEV_I2C_HDMIPHY
  612. static struct resource s5p_i2c_resource[] = {
  613. [0] = DEFINE_RES_MEM(S5P_PA_IIC_HDMIPHY, SZ_4K),
  614. [1] = DEFINE_RES_IRQ(IRQ_IIC_HDMIPHY),
  615. };
  616. struct platform_device s5p_device_i2c_hdmiphy = {
  617. .name = "s3c2440-hdmiphy-i2c",
  618. .id = -1,
  619. .num_resources = ARRAY_SIZE(s5p_i2c_resource),
  620. .resource = s5p_i2c_resource,
  621. };
  622. void __init s5p_i2c_hdmiphy_set_platdata(struct s3c2410_platform_i2c *pd)
  623. {
  624. struct s3c2410_platform_i2c *npd;
  625. if (!pd) {
  626. pd = &default_i2c_data;
  627. if (soc_is_exynos4210() ||
  628. soc_is_exynos4212() || soc_is_exynos4412())
  629. pd->bus_num = 8;
  630. else if (soc_is_s5pv210())
  631. pd->bus_num = 3;
  632. else
  633. pd->bus_num = 0;
  634. }
  635. npd = s3c_set_platdata(pd, sizeof(struct s3c2410_platform_i2c),
  636. &s5p_device_i2c_hdmiphy);
  637. }
  638. static struct s5p_hdmi_platform_data s5p_hdmi_def_platdata;
  639. void __init s5p_hdmi_set_platdata(struct i2c_board_info *hdmiphy_info,
  640. struct i2c_board_info *mhl_info, int mhl_bus)
  641. {
  642. struct s5p_hdmi_platform_data *pd = &s5p_hdmi_def_platdata;
  643. if (soc_is_exynos4210() ||
  644. soc_is_exynos4212() || soc_is_exynos4412())
  645. pd->hdmiphy_bus = 8;
  646. else if (soc_is_s5pv210())
  647. pd->hdmiphy_bus = 3;
  648. else
  649. pd->hdmiphy_bus = 0;
  650. pd->hdmiphy_info = hdmiphy_info;
  651. pd->mhl_info = mhl_info;
  652. pd->mhl_bus = mhl_bus;
  653. s3c_set_platdata(pd, sizeof(struct s5p_hdmi_platform_data),
  654. &s5p_device_hdmi);
  655. }
  656. #endif /* CONFIG_S5P_DEV_I2C_HDMIPHY */
  657. /* I2S */
  658. #ifdef CONFIG_PLAT_S3C24XX
  659. static struct resource s3c_iis_resource[] = {
  660. [0] = DEFINE_RES_MEM(S3C24XX_PA_IIS, S3C24XX_SZ_IIS),
  661. };
  662. struct platform_device s3c_device_iis = {
  663. .name = "s3c24xx-iis",
  664. .id = -1,
  665. .num_resources = ARRAY_SIZE(s3c_iis_resource),
  666. .resource = s3c_iis_resource,
  667. .dev = {
  668. .dma_mask = &samsung_device_dma_mask,
  669. .coherent_dma_mask = DMA_BIT_MASK(32),
  670. }
  671. };
  672. #endif /* CONFIG_PLAT_S3C24XX */
  673. /* IDE CFCON */
  674. #ifdef CONFIG_SAMSUNG_DEV_IDE
  675. static struct resource s3c_cfcon_resource[] = {
  676. [0] = DEFINE_RES_MEM(SAMSUNG_PA_CFCON, SZ_16K),
  677. [1] = DEFINE_RES_IRQ(IRQ_CFCON),
  678. };
  679. struct platform_device s3c_device_cfcon = {
  680. .id = 0,
  681. .num_resources = ARRAY_SIZE(s3c_cfcon_resource),
  682. .resource = s3c_cfcon_resource,
  683. };
  684. void __init s3c_ide_set_platdata(struct s3c_ide_platdata *pdata)
  685. {
  686. s3c_set_platdata(pdata, sizeof(struct s3c_ide_platdata),
  687. &s3c_device_cfcon);
  688. }
  689. #endif /* CONFIG_SAMSUNG_DEV_IDE */
  690. /* KEYPAD */
  691. #ifdef CONFIG_SAMSUNG_DEV_KEYPAD
  692. static struct resource samsung_keypad_resources[] = {
  693. [0] = DEFINE_RES_MEM(SAMSUNG_PA_KEYPAD, SZ_32),
  694. [1] = DEFINE_RES_IRQ(IRQ_KEYPAD),
  695. };
  696. struct platform_device samsung_device_keypad = {
  697. .name = "samsung-keypad",
  698. .id = -1,
  699. .num_resources = ARRAY_SIZE(samsung_keypad_resources),
  700. .resource = samsung_keypad_resources,
  701. };
  702. void __init samsung_keypad_set_platdata(struct samsung_keypad_platdata *pd)
  703. {
  704. struct samsung_keypad_platdata *npd;
  705. npd = s3c_set_platdata(pd, sizeof(struct samsung_keypad_platdata),
  706. &samsung_device_keypad);
  707. if (!npd->cfg_gpio)
  708. npd->cfg_gpio = samsung_keypad_cfg_gpio;
  709. }
  710. #endif /* CONFIG_SAMSUNG_DEV_KEYPAD */
  711. /* LCD Controller */
  712. #ifdef CONFIG_PLAT_S3C24XX
  713. static struct resource s3c_lcd_resource[] = {
  714. [0] = DEFINE_RES_MEM(S3C24XX_PA_LCD, S3C24XX_SZ_LCD),
  715. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  716. };
  717. struct platform_device s3c_device_lcd = {
  718. .name = "s3c2410-lcd",
  719. .id = -1,
  720. .num_resources = ARRAY_SIZE(s3c_lcd_resource),
  721. .resource = s3c_lcd_resource,
  722. .dev = {
  723. .dma_mask = &samsung_device_dma_mask,
  724. .coherent_dma_mask = DMA_BIT_MASK(32),
  725. }
  726. };
  727. void __init s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *pd)
  728. {
  729. struct s3c2410fb_mach_info *npd;
  730. npd = s3c_set_platdata(pd, sizeof(*npd), &s3c_device_lcd);
  731. if (npd) {
  732. npd->displays = kmemdup(pd->displays,
  733. sizeof(struct s3c2410fb_display) * npd->num_displays,
  734. GFP_KERNEL);
  735. if (!npd->displays)
  736. printk(KERN_ERR "no memory for LCD display data\n");
  737. } else {
  738. printk(KERN_ERR "no memory for LCD platform data\n");
  739. }
  740. }
  741. #endif /* CONFIG_PLAT_S3C24XX */
  742. /* MIPI CSIS */
  743. #ifdef CONFIG_S5P_DEV_CSIS0
  744. static struct resource s5p_mipi_csis0_resource[] = {
  745. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS0, SZ_16K),
  746. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS0),
  747. };
  748. struct platform_device s5p_device_mipi_csis0 = {
  749. .name = "s5p-mipi-csis",
  750. .id = 0,
  751. .num_resources = ARRAY_SIZE(s5p_mipi_csis0_resource),
  752. .resource = s5p_mipi_csis0_resource,
  753. };
  754. #endif /* CONFIG_S5P_DEV_CSIS0 */
  755. #ifdef CONFIG_S5P_DEV_CSIS1
  756. static struct resource s5p_mipi_csis1_resource[] = {
  757. [0] = DEFINE_RES_MEM(S5P_PA_MIPI_CSIS1, SZ_16K),
  758. [1] = DEFINE_RES_IRQ(IRQ_MIPI_CSIS1),
  759. };
  760. struct platform_device s5p_device_mipi_csis1 = {
  761. .name = "s5p-mipi-csis",
  762. .id = 1,
  763. .num_resources = ARRAY_SIZE(s5p_mipi_csis1_resource),
  764. .resource = s5p_mipi_csis1_resource,
  765. };
  766. #endif
  767. /* NAND */
  768. #ifdef CONFIG_S3C_DEV_NAND
  769. static struct resource s3c_nand_resource[] = {
  770. [0] = DEFINE_RES_MEM(S3C_PA_NAND, SZ_1M),
  771. };
  772. struct platform_device s3c_device_nand = {
  773. .name = "s3c2410-nand",
  774. .id = -1,
  775. .num_resources = ARRAY_SIZE(s3c_nand_resource),
  776. .resource = s3c_nand_resource,
  777. };
  778. /*
  779. * s3c_nand_copy_set() - copy nand set data
  780. * @set: The new structure, directly copied from the old.
  781. *
  782. * Copy all the fields from the NAND set field from what is probably __initdata
  783. * to new kernel memory. The code returns 0 if the copy happened correctly or
  784. * an error code for the calling function to display.
  785. *
  786. * Note, we currently do not try and look to see if we've already copied the
  787. * data in a previous set.
  788. */
  789. static int __init s3c_nand_copy_set(struct s3c2410_nand_set *set)
  790. {
  791. void *ptr;
  792. int size;
  793. size = sizeof(struct mtd_partition) * set->nr_partitions;
  794. if (size) {
  795. ptr = kmemdup(set->partitions, size, GFP_KERNEL);
  796. set->partitions = ptr;
  797. if (!ptr)
  798. return -ENOMEM;
  799. }
  800. if (set->nr_map && set->nr_chips) {
  801. size = sizeof(int) * set->nr_chips;
  802. ptr = kmemdup(set->nr_map, size, GFP_KERNEL);
  803. set->nr_map = ptr;
  804. if (!ptr)
  805. return -ENOMEM;
  806. }
  807. if (set->ecc_layout) {
  808. ptr = kmemdup(set->ecc_layout,
  809. sizeof(struct nand_ecclayout), GFP_KERNEL);
  810. set->ecc_layout = ptr;
  811. if (!ptr)
  812. return -ENOMEM;
  813. }
  814. return 0;
  815. }
  816. void __init s3c_nand_set_platdata(struct s3c2410_platform_nand *nand)
  817. {
  818. struct s3c2410_platform_nand *npd;
  819. int size;
  820. int ret;
  821. /* note, if we get a failure in allocation, we simply drop out of the
  822. * function. If there is so little memory available at initialisation
  823. * time then there is little chance the system is going to run.
  824. */
  825. npd = s3c_set_platdata(nand, sizeof(struct s3c2410_platform_nand),
  826. &s3c_device_nand);
  827. if (!npd)
  828. return;
  829. /* now see if we need to copy any of the nand set data */
  830. size = sizeof(struct s3c2410_nand_set) * npd->nr_sets;
  831. if (size) {
  832. struct s3c2410_nand_set *from = npd->sets;
  833. struct s3c2410_nand_set *to;
  834. int i;
  835. to = kmemdup(from, size, GFP_KERNEL);
  836. npd->sets = to; /* set, even if we failed */
  837. if (!to) {
  838. printk(KERN_ERR "%s: no memory for sets\n", __func__);
  839. return;
  840. }
  841. for (i = 0; i < npd->nr_sets; i++) {
  842. ret = s3c_nand_copy_set(to);
  843. if (ret) {
  844. printk(KERN_ERR "%s: failed to copy set %d\n",
  845. __func__, i);
  846. return;
  847. }
  848. to++;
  849. }
  850. }
  851. }
  852. #endif /* CONFIG_S3C_DEV_NAND */
  853. /* ONENAND */
  854. #ifdef CONFIG_S3C_DEV_ONENAND
  855. static struct resource s3c_onenand_resources[] = {
  856. [0] = DEFINE_RES_MEM(S3C_PA_ONENAND, SZ_1K),
  857. [1] = DEFINE_RES_MEM(S3C_PA_ONENAND_BUF, S3C_SZ_ONENAND_BUF),
  858. [2] = DEFINE_RES_IRQ(IRQ_ONENAND),
  859. };
  860. struct platform_device s3c_device_onenand = {
  861. .name = "samsung-onenand",
  862. .id = 0,
  863. .num_resources = ARRAY_SIZE(s3c_onenand_resources),
  864. .resource = s3c_onenand_resources,
  865. };
  866. #endif /* CONFIG_S3C_DEV_ONENAND */
  867. #ifdef CONFIG_S3C64XX_DEV_ONENAND1
  868. static struct resource s3c64xx_onenand1_resources[] = {
  869. [0] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1, SZ_1K),
  870. [1] = DEFINE_RES_MEM(S3C64XX_PA_ONENAND1_BUF, S3C64XX_SZ_ONENAND1_BUF),
  871. [2] = DEFINE_RES_IRQ(IRQ_ONENAND1),
  872. };
  873. struct platform_device s3c64xx_device_onenand1 = {
  874. .name = "samsung-onenand",
  875. .id = 1,
  876. .num_resources = ARRAY_SIZE(s3c64xx_onenand1_resources),
  877. .resource = s3c64xx_onenand1_resources,
  878. };
  879. void __init s3c64xx_onenand1_set_platdata(struct onenand_platform_data *pdata)
  880. {
  881. s3c_set_platdata(pdata, sizeof(struct onenand_platform_data),
  882. &s3c64xx_device_onenand1);
  883. }
  884. #endif /* CONFIG_S3C64XX_DEV_ONENAND1 */
  885. #ifdef CONFIG_S5P_DEV_ONENAND
  886. static struct resource s5p_onenand_resources[] = {
  887. [0] = DEFINE_RES_MEM(S5P_PA_ONENAND, SZ_128K),
  888. [1] = DEFINE_RES_MEM(S5P_PA_ONENAND_DMA, SZ_8K),
  889. [2] = DEFINE_RES_IRQ(IRQ_ONENAND_AUDI),
  890. };
  891. struct platform_device s5p_device_onenand = {
  892. .name = "s5pc110-onenand",
  893. .id = -1,
  894. .num_resources = ARRAY_SIZE(s5p_onenand_resources),
  895. .resource = s5p_onenand_resources,
  896. };
  897. #endif /* CONFIG_S5P_DEV_ONENAND */
  898. /* PMU */
  899. #if defined(CONFIG_PLAT_S5P) && !defined(CONFIG_ARCH_EXYNOS)
  900. static struct resource s5p_pmu_resource[] = {
  901. DEFINE_RES_IRQ(IRQ_PMU)
  902. };
  903. static struct platform_device s5p_device_pmu = {
  904. .name = "arm-pmu",
  905. .id = -1,
  906. .num_resources = ARRAY_SIZE(s5p_pmu_resource),
  907. .resource = s5p_pmu_resource,
  908. };
  909. static int __init s5p_pmu_init(void)
  910. {
  911. platform_device_register(&s5p_device_pmu);
  912. return 0;
  913. }
  914. arch_initcall(s5p_pmu_init);
  915. #endif /* CONFIG_PLAT_S5P */
  916. /* PWM Timer */
  917. #ifdef CONFIG_SAMSUNG_DEV_PWM
  918. #define TIMER_RESOURCE_SIZE (1)
  919. #define TIMER_RESOURCE(_tmr, _irq) \
  920. (struct resource [TIMER_RESOURCE_SIZE]) { \
  921. [0] = { \
  922. .start = _irq, \
  923. .end = _irq, \
  924. .flags = IORESOURCE_IRQ \
  925. } \
  926. }
  927. #define DEFINE_S3C_TIMER(_tmr_no, _irq) \
  928. .name = "s3c24xx-pwm", \
  929. .id = _tmr_no, \
  930. .num_resources = TIMER_RESOURCE_SIZE, \
  931. .resource = TIMER_RESOURCE(_tmr_no, _irq), \
  932. /*
  933. * since we already have an static mapping for the timer,
  934. * we do not bother setting any IO resource for the base.
  935. */
  936. struct platform_device s3c_device_timer[] = {
  937. [0] = { DEFINE_S3C_TIMER(0, IRQ_TIMER0) },
  938. [1] = { DEFINE_S3C_TIMER(1, IRQ_TIMER1) },
  939. [2] = { DEFINE_S3C_TIMER(2, IRQ_TIMER2) },
  940. [3] = { DEFINE_S3C_TIMER(3, IRQ_TIMER3) },
  941. [4] = { DEFINE_S3C_TIMER(4, IRQ_TIMER4) },
  942. };
  943. #endif /* CONFIG_SAMSUNG_DEV_PWM */
  944. /* RTC */
  945. #ifdef CONFIG_PLAT_S3C24XX
  946. static struct resource s3c_rtc_resource[] = {
  947. [0] = DEFINE_RES_MEM(S3C24XX_PA_RTC, SZ_256),
  948. [1] = DEFINE_RES_IRQ(IRQ_RTC),
  949. [2] = DEFINE_RES_IRQ(IRQ_TICK),
  950. };
  951. struct platform_device s3c_device_rtc = {
  952. .name = "s3c2410-rtc",
  953. .id = -1,
  954. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  955. .resource = s3c_rtc_resource,
  956. };
  957. #endif /* CONFIG_PLAT_S3C24XX */
  958. #ifdef CONFIG_S3C_DEV_RTC
  959. static struct resource s3c_rtc_resource[] = {
  960. [0] = DEFINE_RES_MEM(S3C_PA_RTC, SZ_256),
  961. [1] = DEFINE_RES_IRQ(IRQ_RTC_ALARM),
  962. [2] = DEFINE_RES_IRQ(IRQ_RTC_TIC),
  963. };
  964. struct platform_device s3c_device_rtc = {
  965. .name = "s3c64xx-rtc",
  966. .id = -1,
  967. .num_resources = ARRAY_SIZE(s3c_rtc_resource),
  968. .resource = s3c_rtc_resource,
  969. };
  970. #endif /* CONFIG_S3C_DEV_RTC */
  971. /* SDI */
  972. #ifdef CONFIG_PLAT_S3C24XX
  973. static struct resource s3c_sdi_resource[] = {
  974. [0] = DEFINE_RES_MEM(S3C24XX_PA_SDI, S3C24XX_SZ_SDI),
  975. [1] = DEFINE_RES_IRQ(IRQ_SDI),
  976. };
  977. struct platform_device s3c_device_sdi = {
  978. .name = "s3c2410-sdi",
  979. .id = -1,
  980. .num_resources = ARRAY_SIZE(s3c_sdi_resource),
  981. .resource = s3c_sdi_resource,
  982. };
  983. void __init s3c24xx_mci_set_platdata(struct s3c24xx_mci_pdata *pdata)
  984. {
  985. s3c_set_platdata(pdata, sizeof(struct s3c24xx_mci_pdata),
  986. &s3c_device_sdi);
  987. }
  988. #endif /* CONFIG_PLAT_S3C24XX */
  989. /* SPI */
  990. #ifdef CONFIG_PLAT_S3C24XX
  991. static struct resource s3c_spi0_resource[] = {
  992. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI, SZ_32),
  993. [1] = DEFINE_RES_IRQ(IRQ_SPI0),
  994. };
  995. struct platform_device s3c_device_spi0 = {
  996. .name = "s3c2410-spi",
  997. .id = 0,
  998. .num_resources = ARRAY_SIZE(s3c_spi0_resource),
  999. .resource = s3c_spi0_resource,
  1000. .dev = {
  1001. .dma_mask = &samsung_device_dma_mask,
  1002. .coherent_dma_mask = DMA_BIT_MASK(32),
  1003. }
  1004. };
  1005. static struct resource s3c_spi1_resource[] = {
  1006. [0] = DEFINE_RES_MEM(S3C24XX_PA_SPI1, SZ_32),
  1007. [1] = DEFINE_RES_IRQ(IRQ_SPI1),
  1008. };
  1009. struct platform_device s3c_device_spi1 = {
  1010. .name = "s3c2410-spi",
  1011. .id = 1,
  1012. .num_resources = ARRAY_SIZE(s3c_spi1_resource),
  1013. .resource = s3c_spi1_resource,
  1014. .dev = {
  1015. .dma_mask = &samsung_device_dma_mask,
  1016. .coherent_dma_mask = DMA_BIT_MASK(32),
  1017. }
  1018. };
  1019. #endif /* CONFIG_PLAT_S3C24XX */
  1020. /* Touchscreen */
  1021. #ifdef CONFIG_PLAT_S3C24XX
  1022. static struct resource s3c_ts_resource[] = {
  1023. [0] = DEFINE_RES_MEM(S3C24XX_PA_ADC, S3C24XX_SZ_ADC),
  1024. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1025. };
  1026. struct platform_device s3c_device_ts = {
  1027. .name = "s3c2410-ts",
  1028. .id = -1,
  1029. .dev.parent = &s3c_device_adc.dev,
  1030. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1031. .resource = s3c_ts_resource,
  1032. };
  1033. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *hard_s3c2410ts_info)
  1034. {
  1035. s3c_set_platdata(hard_s3c2410ts_info,
  1036. sizeof(struct s3c2410_ts_mach_info), &s3c_device_ts);
  1037. }
  1038. #endif /* CONFIG_PLAT_S3C24XX */
  1039. #ifdef CONFIG_SAMSUNG_DEV_TS
  1040. static struct resource s3c_ts_resource[] = {
  1041. [0] = DEFINE_RES_MEM(SAMSUNG_PA_ADC, SZ_256),
  1042. [1] = DEFINE_RES_IRQ(IRQ_TC),
  1043. };
  1044. static struct s3c2410_ts_mach_info default_ts_data __initdata = {
  1045. .delay = 10000,
  1046. .presc = 49,
  1047. .oversampling_shift = 2,
  1048. };
  1049. struct platform_device s3c_device_ts = {
  1050. .name = "s3c64xx-ts",
  1051. .id = -1,
  1052. .num_resources = ARRAY_SIZE(s3c_ts_resource),
  1053. .resource = s3c_ts_resource,
  1054. };
  1055. void __init s3c24xx_ts_set_platdata(struct s3c2410_ts_mach_info *pd)
  1056. {
  1057. if (!pd)
  1058. pd = &default_ts_data;
  1059. s3c_set_platdata(pd, sizeof(struct s3c2410_ts_mach_info),
  1060. &s3c_device_ts);
  1061. }
  1062. #endif /* CONFIG_SAMSUNG_DEV_TS */
  1063. /* TV */
  1064. #ifdef CONFIG_S5P_DEV_TV
  1065. static struct resource s5p_hdmi_resources[] = {
  1066. [0] = DEFINE_RES_MEM(S5P_PA_HDMI, SZ_1M),
  1067. [1] = DEFINE_RES_IRQ(IRQ_HDMI),
  1068. };
  1069. struct platform_device s5p_device_hdmi = {
  1070. .name = "s5p-hdmi",
  1071. .id = -1,
  1072. .num_resources = ARRAY_SIZE(s5p_hdmi_resources),
  1073. .resource = s5p_hdmi_resources,
  1074. };
  1075. static struct resource s5p_sdo_resources[] = {
  1076. [0] = DEFINE_RES_MEM(S5P_PA_SDO, SZ_64K),
  1077. [1] = DEFINE_RES_IRQ(IRQ_SDO),
  1078. };
  1079. struct platform_device s5p_device_sdo = {
  1080. .name = "s5p-sdo",
  1081. .id = -1,
  1082. .num_resources = ARRAY_SIZE(s5p_sdo_resources),
  1083. .resource = s5p_sdo_resources,
  1084. };
  1085. static struct resource s5p_mixer_resources[] = {
  1086. [0] = DEFINE_RES_MEM_NAMED(S5P_PA_MIXER, SZ_64K, "mxr"),
  1087. [1] = DEFINE_RES_MEM_NAMED(S5P_PA_VP, SZ_64K, "vp"),
  1088. [2] = DEFINE_RES_IRQ_NAMED(IRQ_MIXER, "irq"),
  1089. };
  1090. struct platform_device s5p_device_mixer = {
  1091. .name = "s5p-mixer",
  1092. .id = -1,
  1093. .num_resources = ARRAY_SIZE(s5p_mixer_resources),
  1094. .resource = s5p_mixer_resources,
  1095. .dev = {
  1096. .dma_mask = &samsung_device_dma_mask,
  1097. .coherent_dma_mask = DMA_BIT_MASK(32),
  1098. }
  1099. };
  1100. #endif /* CONFIG_S5P_DEV_TV */
  1101. /* USB */
  1102. #ifdef CONFIG_S3C_DEV_USB_HOST
  1103. static struct resource s3c_usb_resource[] = {
  1104. [0] = DEFINE_RES_MEM(S3C_PA_USBHOST, SZ_256),
  1105. [1] = DEFINE_RES_IRQ(IRQ_USBH),
  1106. };
  1107. struct platform_device s3c_device_ohci = {
  1108. .name = "s3c2410-ohci",
  1109. .id = -1,
  1110. .num_resources = ARRAY_SIZE(s3c_usb_resource),
  1111. .resource = s3c_usb_resource,
  1112. .dev = {
  1113. .dma_mask = &samsung_device_dma_mask,
  1114. .coherent_dma_mask = DMA_BIT_MASK(32),
  1115. }
  1116. };
  1117. /*
  1118. * s3c_ohci_set_platdata - initialise OHCI device platform data
  1119. * @info: The platform data.
  1120. *
  1121. * This call copies the @info passed in and sets the device .platform_data
  1122. * field to that copy. The @info is copied so that the original can be marked
  1123. * __initdata.
  1124. */
  1125. void __init s3c_ohci_set_platdata(struct s3c2410_hcd_info *info)
  1126. {
  1127. s3c_set_platdata(info, sizeof(struct s3c2410_hcd_info),
  1128. &s3c_device_ohci);
  1129. }
  1130. #endif /* CONFIG_S3C_DEV_USB_HOST */
  1131. /* USB Device (Gadget) */
  1132. #ifdef CONFIG_PLAT_S3C24XX
  1133. static struct resource s3c_usbgadget_resource[] = {
  1134. [0] = DEFINE_RES_MEM(S3C24XX_PA_USBDEV, S3C24XX_SZ_USBDEV),
  1135. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1136. };
  1137. struct platform_device s3c_device_usbgadget = {
  1138. .name = "s3c2410-usbgadget",
  1139. .id = -1,
  1140. .num_resources = ARRAY_SIZE(s3c_usbgadget_resource),
  1141. .resource = s3c_usbgadget_resource,
  1142. };
  1143. void __init s3c24xx_udc_set_platdata(struct s3c2410_udc_mach_info *pd)
  1144. {
  1145. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usbgadget);
  1146. }
  1147. #endif /* CONFIG_PLAT_S3C24XX */
  1148. /* USB EHCI Host Controller */
  1149. #ifdef CONFIG_S5P_DEV_USB_EHCI
  1150. static struct resource s5p_ehci_resource[] = {
  1151. [0] = DEFINE_RES_MEM(S5P_PA_EHCI, SZ_256),
  1152. [1] = DEFINE_RES_IRQ(IRQ_USB_HOST),
  1153. };
  1154. struct platform_device s5p_device_ehci = {
  1155. .name = "s5p-ehci",
  1156. .id = -1,
  1157. .num_resources = ARRAY_SIZE(s5p_ehci_resource),
  1158. .resource = s5p_ehci_resource,
  1159. .dev = {
  1160. .dma_mask = &samsung_device_dma_mask,
  1161. .coherent_dma_mask = DMA_BIT_MASK(32),
  1162. }
  1163. };
  1164. void __init s5p_ehci_set_platdata(struct s5p_ehci_platdata *pd)
  1165. {
  1166. struct s5p_ehci_platdata *npd;
  1167. npd = s3c_set_platdata(pd, sizeof(struct s5p_ehci_platdata),
  1168. &s5p_device_ehci);
  1169. if (!npd->phy_init)
  1170. npd->phy_init = s5p_usb_phy_init;
  1171. if (!npd->phy_exit)
  1172. npd->phy_exit = s5p_usb_phy_exit;
  1173. }
  1174. #endif /* CONFIG_S5P_DEV_USB_EHCI */
  1175. /* USB HSOTG */
  1176. #ifdef CONFIG_S3C_DEV_USB_HSOTG
  1177. static struct resource s3c_usb_hsotg_resources[] = {
  1178. [0] = DEFINE_RES_MEM(S3C_PA_USB_HSOTG, SZ_128K),
  1179. [1] = DEFINE_RES_IRQ(IRQ_OTG),
  1180. };
  1181. struct platform_device s3c_device_usb_hsotg = {
  1182. .name = "s3c-hsotg",
  1183. .id = -1,
  1184. .num_resources = ARRAY_SIZE(s3c_usb_hsotg_resources),
  1185. .resource = s3c_usb_hsotg_resources,
  1186. .dev = {
  1187. .dma_mask = &samsung_device_dma_mask,
  1188. .coherent_dma_mask = DMA_BIT_MASK(32),
  1189. },
  1190. };
  1191. void __init s3c_hsotg_set_platdata(struct s3c_hsotg_plat *pd)
  1192. {
  1193. struct s3c_hsotg_plat *npd;
  1194. npd = s3c_set_platdata(pd, sizeof(struct s3c_hsotg_plat),
  1195. &s3c_device_usb_hsotg);
  1196. if (!npd->phy_init)
  1197. npd->phy_init = s5p_usb_phy_init;
  1198. if (!npd->phy_exit)
  1199. npd->phy_exit = s5p_usb_phy_exit;
  1200. }
  1201. #endif /* CONFIG_S3C_DEV_USB_HSOTG */
  1202. /* USB High Spped 2.0 Device (Gadget) */
  1203. #ifdef CONFIG_PLAT_S3C24XX
  1204. static struct resource s3c_hsudc_resource[] = {
  1205. [0] = DEFINE_RES_MEM(S3C2416_PA_HSUDC, S3C2416_SZ_HSUDC),
  1206. [1] = DEFINE_RES_IRQ(IRQ_USBD),
  1207. };
  1208. struct platform_device s3c_device_usb_hsudc = {
  1209. .name = "s3c-hsudc",
  1210. .id = -1,
  1211. .num_resources = ARRAY_SIZE(s3c_hsudc_resource),
  1212. .resource = s3c_hsudc_resource,
  1213. .dev = {
  1214. .dma_mask = &samsung_device_dma_mask,
  1215. .coherent_dma_mask = DMA_BIT_MASK(32),
  1216. },
  1217. };
  1218. void __init s3c24xx_hsudc_set_platdata(struct s3c24xx_hsudc_platdata *pd)
  1219. {
  1220. s3c_set_platdata(pd, sizeof(*pd), &s3c_device_usb_hsudc);
  1221. }
  1222. #endif /* CONFIG_PLAT_S3C24XX */
  1223. /* WDT */
  1224. #ifdef CONFIG_S3C_DEV_WDT
  1225. static struct resource s3c_wdt_resource[] = {
  1226. [0] = DEFINE_RES_MEM(S3C_PA_WDT, SZ_1K),
  1227. [1] = DEFINE_RES_IRQ(IRQ_WDT),
  1228. };
  1229. struct platform_device s3c_device_wdt = {
  1230. .name = "s3c2410-wdt",
  1231. .id = -1,
  1232. .num_resources = ARRAY_SIZE(s3c_wdt_resource),
  1233. .resource = s3c_wdt_resource,
  1234. };
  1235. #endif /* CONFIG_S3C_DEV_WDT */
  1236. #ifdef CONFIG_S3C64XX_DEV_SPI0
  1237. static struct resource s3c64xx_spi0_resource[] = {
  1238. [0] = DEFINE_RES_MEM(S3C_PA_SPI0, SZ_256),
  1239. [1] = DEFINE_RES_DMA(DMACH_SPI0_TX),
  1240. [2] = DEFINE_RES_DMA(DMACH_SPI0_RX),
  1241. [3] = DEFINE_RES_IRQ(IRQ_SPI0),
  1242. };
  1243. struct platform_device s3c64xx_device_spi0 = {
  1244. .name = "s3c6410-spi",
  1245. .id = 0,
  1246. .num_resources = ARRAY_SIZE(s3c64xx_spi0_resource),
  1247. .resource = s3c64xx_spi0_resource,
  1248. .dev = {
  1249. .dma_mask = &samsung_device_dma_mask,
  1250. .coherent_dma_mask = DMA_BIT_MASK(32),
  1251. },
  1252. };
  1253. void __init s3c64xx_spi0_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1254. int num_cs)
  1255. {
  1256. struct s3c64xx_spi_info pd;
  1257. /* Reject invalid configuration */
  1258. if (!num_cs || src_clk_nr < 0) {
  1259. pr_err("%s: Invalid SPI configuration\n", __func__);
  1260. return;
  1261. }
  1262. pd.num_cs = num_cs;
  1263. pd.src_clk_nr = src_clk_nr;
  1264. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi0_cfg_gpio;
  1265. #ifdef CONFIG_PL330_DMA
  1266. pd.filter = pl330_filter;
  1267. #endif
  1268. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi0);
  1269. }
  1270. #endif /* CONFIG_S3C64XX_DEV_SPI0 */
  1271. #ifdef CONFIG_S3C64XX_DEV_SPI1
  1272. static struct resource s3c64xx_spi1_resource[] = {
  1273. [0] = DEFINE_RES_MEM(S3C_PA_SPI1, SZ_256),
  1274. [1] = DEFINE_RES_DMA(DMACH_SPI1_TX),
  1275. [2] = DEFINE_RES_DMA(DMACH_SPI1_RX),
  1276. [3] = DEFINE_RES_IRQ(IRQ_SPI1),
  1277. };
  1278. struct platform_device s3c64xx_device_spi1 = {
  1279. .name = "s3c6410-spi",
  1280. .id = 1,
  1281. .num_resources = ARRAY_SIZE(s3c64xx_spi1_resource),
  1282. .resource = s3c64xx_spi1_resource,
  1283. .dev = {
  1284. .dma_mask = &samsung_device_dma_mask,
  1285. .coherent_dma_mask = DMA_BIT_MASK(32),
  1286. },
  1287. };
  1288. void __init s3c64xx_spi1_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1289. int num_cs)
  1290. {
  1291. struct s3c64xx_spi_info pd;
  1292. /* Reject invalid configuration */
  1293. if (!num_cs || src_clk_nr < 0) {
  1294. pr_err("%s: Invalid SPI configuration\n", __func__);
  1295. return;
  1296. }
  1297. pd.num_cs = num_cs;
  1298. pd.src_clk_nr = src_clk_nr;
  1299. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi1_cfg_gpio;
  1300. #ifdef CONFIG_PL330_DMA
  1301. pd.filter = pl330_filter;
  1302. #endif
  1303. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi1);
  1304. }
  1305. #endif /* CONFIG_S3C64XX_DEV_SPI1 */
  1306. #ifdef CONFIG_S3C64XX_DEV_SPI2
  1307. static struct resource s3c64xx_spi2_resource[] = {
  1308. [0] = DEFINE_RES_MEM(S3C_PA_SPI2, SZ_256),
  1309. [1] = DEFINE_RES_DMA(DMACH_SPI2_TX),
  1310. [2] = DEFINE_RES_DMA(DMACH_SPI2_RX),
  1311. [3] = DEFINE_RES_IRQ(IRQ_SPI2),
  1312. };
  1313. struct platform_device s3c64xx_device_spi2 = {
  1314. .name = "s3c6410-spi",
  1315. .id = 2,
  1316. .num_resources = ARRAY_SIZE(s3c64xx_spi2_resource),
  1317. .resource = s3c64xx_spi2_resource,
  1318. .dev = {
  1319. .dma_mask = &samsung_device_dma_mask,
  1320. .coherent_dma_mask = DMA_BIT_MASK(32),
  1321. },
  1322. };
  1323. void __init s3c64xx_spi2_set_platdata(int (*cfg_gpio)(void), int src_clk_nr,
  1324. int num_cs)
  1325. {
  1326. struct s3c64xx_spi_info pd;
  1327. /* Reject invalid configuration */
  1328. if (!num_cs || src_clk_nr < 0) {
  1329. pr_err("%s: Invalid SPI configuration\n", __func__);
  1330. return;
  1331. }
  1332. pd.num_cs = num_cs;
  1333. pd.src_clk_nr = src_clk_nr;
  1334. pd.cfg_gpio = (cfg_gpio) ? cfg_gpio : s3c64xx_spi2_cfg_gpio;
  1335. #ifdef CONFIG_PL330_DMA
  1336. pd.filter = pl330_filter;
  1337. #endif
  1338. s3c_set_platdata(&pd, sizeof(pd), &s3c64xx_device_spi2);
  1339. }
  1340. #endif /* CONFIG_S3C64XX_DEV_SPI2 */