dma-mapping.c 51 KB

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  1. /*
  2. * linux/arch/arm/mm/dma-mapping.c
  3. *
  4. * Copyright (C) 2000-2004 Russell King
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * DMA uncached mapping support.
  11. */
  12. #include <linux/module.h>
  13. #include <linux/mm.h>
  14. #include <linux/gfp.h>
  15. #include <linux/errno.h>
  16. #include <linux/list.h>
  17. #include <linux/init.h>
  18. #include <linux/device.h>
  19. #include <linux/dma-mapping.h>
  20. #include <linux/dma-contiguous.h>
  21. #include <linux/highmem.h>
  22. #include <linux/memblock.h>
  23. #include <linux/slab.h>
  24. #include <linux/iommu.h>
  25. #include <linux/io.h>
  26. #include <linux/vmalloc.h>
  27. #include <linux/sizes.h>
  28. #include <asm/memory.h>
  29. #include <asm/highmem.h>
  30. #include <asm/cacheflush.h>
  31. #include <asm/tlbflush.h>
  32. #include <asm/mach/arch.h>
  33. #include <asm/dma-iommu.h>
  34. #include <asm/mach/map.h>
  35. #include <asm/system_info.h>
  36. #include <asm/dma-contiguous.h>
  37. #include "mm.h"
  38. /*
  39. * The DMA API is built upon the notion of "buffer ownership". A buffer
  40. * is either exclusively owned by the CPU (and therefore may be accessed
  41. * by it) or exclusively owned by the DMA device. These helper functions
  42. * represent the transitions between these two ownership states.
  43. *
  44. * Note, however, that on later ARMs, this notion does not work due to
  45. * speculative prefetches. We model our approach on the assumption that
  46. * the CPU does do speculative prefetches, which means we clean caches
  47. * before transfers and delay cache invalidation until transfer completion.
  48. *
  49. */
  50. static void __dma_page_cpu_to_dev(struct page *, unsigned long,
  51. size_t, enum dma_data_direction);
  52. static void __dma_page_dev_to_cpu(struct page *, unsigned long,
  53. size_t, enum dma_data_direction);
  54. /**
  55. * arm_dma_map_page - map a portion of a page for streaming DMA
  56. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  57. * @page: page that buffer resides in
  58. * @offset: offset into page for start of buffer
  59. * @size: size of buffer to map
  60. * @dir: DMA transfer direction
  61. *
  62. * Ensure that any data held in the cache is appropriately discarded
  63. * or written back.
  64. *
  65. * The device owns this memory once this call has completed. The CPU
  66. * can regain ownership by calling dma_unmap_page().
  67. */
  68. static dma_addr_t arm_dma_map_page(struct device *dev, struct page *page,
  69. unsigned long offset, size_t size, enum dma_data_direction dir,
  70. struct dma_attrs *attrs)
  71. {
  72. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  73. __dma_page_cpu_to_dev(page, offset, size, dir);
  74. return pfn_to_dma(dev, page_to_pfn(page)) + offset;
  75. }
  76. static dma_addr_t arm_coherent_dma_map_page(struct device *dev, struct page *page,
  77. unsigned long offset, size_t size, enum dma_data_direction dir,
  78. struct dma_attrs *attrs)
  79. {
  80. return pfn_to_dma(dev, page_to_pfn(page)) + offset;
  81. }
  82. /**
  83. * arm_dma_unmap_page - unmap a buffer previously mapped through dma_map_page()
  84. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  85. * @handle: DMA address of buffer
  86. * @size: size of buffer (same as passed to dma_map_page)
  87. * @dir: DMA transfer direction (same as passed to dma_map_page)
  88. *
  89. * Unmap a page streaming mode DMA translation. The handle and size
  90. * must match what was provided in the previous dma_map_page() call.
  91. * All other usages are undefined.
  92. *
  93. * After this call, reads by the CPU to the buffer are guaranteed to see
  94. * whatever the device wrote there.
  95. */
  96. static void arm_dma_unmap_page(struct device *dev, dma_addr_t handle,
  97. size_t size, enum dma_data_direction dir,
  98. struct dma_attrs *attrs)
  99. {
  100. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  101. __dma_page_dev_to_cpu(pfn_to_page(dma_to_pfn(dev, handle)),
  102. handle & ~PAGE_MASK, size, dir);
  103. }
  104. static void arm_dma_sync_single_for_cpu(struct device *dev,
  105. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  106. {
  107. unsigned int offset = handle & (PAGE_SIZE - 1);
  108. struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
  109. __dma_page_dev_to_cpu(page, offset, size, dir);
  110. }
  111. static void arm_dma_sync_single_for_device(struct device *dev,
  112. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  113. {
  114. unsigned int offset = handle & (PAGE_SIZE - 1);
  115. struct page *page = pfn_to_page(dma_to_pfn(dev, handle-offset));
  116. __dma_page_cpu_to_dev(page, offset, size, dir);
  117. }
  118. struct dma_map_ops arm_dma_ops = {
  119. .alloc = arm_dma_alloc,
  120. .free = arm_dma_free,
  121. .mmap = arm_dma_mmap,
  122. .get_sgtable = arm_dma_get_sgtable,
  123. .map_page = arm_dma_map_page,
  124. .unmap_page = arm_dma_unmap_page,
  125. .map_sg = arm_dma_map_sg,
  126. .unmap_sg = arm_dma_unmap_sg,
  127. .sync_single_for_cpu = arm_dma_sync_single_for_cpu,
  128. .sync_single_for_device = arm_dma_sync_single_for_device,
  129. .sync_sg_for_cpu = arm_dma_sync_sg_for_cpu,
  130. .sync_sg_for_device = arm_dma_sync_sg_for_device,
  131. .set_dma_mask = arm_dma_set_mask,
  132. };
  133. EXPORT_SYMBOL(arm_dma_ops);
  134. static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
  135. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs);
  136. static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
  137. dma_addr_t handle, struct dma_attrs *attrs);
  138. struct dma_map_ops arm_coherent_dma_ops = {
  139. .alloc = arm_coherent_dma_alloc,
  140. .free = arm_coherent_dma_free,
  141. .mmap = arm_dma_mmap,
  142. .get_sgtable = arm_dma_get_sgtable,
  143. .map_page = arm_coherent_dma_map_page,
  144. .map_sg = arm_dma_map_sg,
  145. .set_dma_mask = arm_dma_set_mask,
  146. };
  147. EXPORT_SYMBOL(arm_coherent_dma_ops);
  148. static u64 get_coherent_dma_mask(struct device *dev)
  149. {
  150. u64 mask = (u64)arm_dma_limit;
  151. if (dev) {
  152. mask = dev->coherent_dma_mask;
  153. /*
  154. * Sanity check the DMA mask - it must be non-zero, and
  155. * must be able to be satisfied by a DMA allocation.
  156. */
  157. if (mask == 0) {
  158. dev_warn(dev, "coherent DMA mask is unset\n");
  159. return 0;
  160. }
  161. if ((~mask) & (u64)arm_dma_limit) {
  162. dev_warn(dev, "coherent DMA mask %#llx is smaller "
  163. "than system GFP_DMA mask %#llx\n",
  164. mask, (u64)arm_dma_limit);
  165. return 0;
  166. }
  167. }
  168. return mask;
  169. }
  170. static void __dma_clear_buffer(struct page *page, size_t size)
  171. {
  172. /*
  173. * Ensure that the allocated pages are zeroed, and that any data
  174. * lurking in the kernel direct-mapped region is invalidated.
  175. */
  176. if (PageHighMem(page)) {
  177. phys_addr_t base = __pfn_to_phys(page_to_pfn(page));
  178. phys_addr_t end = base + size;
  179. while (size > 0) {
  180. void *ptr = kmap_atomic(page);
  181. memset(ptr, 0, PAGE_SIZE);
  182. dmac_flush_range(ptr, ptr + PAGE_SIZE);
  183. kunmap_atomic(ptr);
  184. page++;
  185. size -= PAGE_SIZE;
  186. }
  187. outer_flush_range(base, end);
  188. } else {
  189. void *ptr = page_address(page);
  190. memset(ptr, 0, size);
  191. dmac_flush_range(ptr, ptr + size);
  192. outer_flush_range(__pa(ptr), __pa(ptr) + size);
  193. }
  194. }
  195. /*
  196. * Allocate a DMA buffer for 'dev' of size 'size' using the
  197. * specified gfp mask. Note that 'size' must be page aligned.
  198. */
  199. static struct page *__dma_alloc_buffer(struct device *dev, size_t size, gfp_t gfp)
  200. {
  201. unsigned long order = get_order(size);
  202. struct page *page, *p, *e;
  203. page = alloc_pages(gfp, order);
  204. if (!page)
  205. return NULL;
  206. /*
  207. * Now split the huge page and free the excess pages
  208. */
  209. split_page(page, order);
  210. for (p = page + (size >> PAGE_SHIFT), e = page + (1 << order); p < e; p++)
  211. __free_page(p);
  212. __dma_clear_buffer(page, size);
  213. return page;
  214. }
  215. /*
  216. * Free a DMA buffer. 'size' must be page aligned.
  217. */
  218. static void __dma_free_buffer(struct page *page, size_t size)
  219. {
  220. struct page *e = page + (size >> PAGE_SHIFT);
  221. while (page < e) {
  222. __free_page(page);
  223. page++;
  224. }
  225. }
  226. #ifdef CONFIG_MMU
  227. #ifdef CONFIG_HUGETLB_PAGE
  228. #warning ARM Coherent DMA allocator does not (yet) support huge TLB
  229. #endif
  230. static void *__alloc_from_contiguous(struct device *dev, size_t size,
  231. pgprot_t prot, struct page **ret_page,
  232. const void *caller);
  233. static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
  234. pgprot_t prot, struct page **ret_page,
  235. const void *caller);
  236. static void *
  237. __dma_alloc_remap(struct page *page, size_t size, gfp_t gfp, pgprot_t prot,
  238. const void *caller)
  239. {
  240. struct vm_struct *area;
  241. unsigned long addr;
  242. /*
  243. * DMA allocation can be mapped to user space, so lets
  244. * set VM_USERMAP flags too.
  245. */
  246. area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
  247. caller);
  248. if (!area)
  249. return NULL;
  250. addr = (unsigned long)area->addr;
  251. area->phys_addr = __pfn_to_phys(page_to_pfn(page));
  252. if (ioremap_page_range(addr, addr + size, area->phys_addr, prot)) {
  253. vunmap((void *)addr);
  254. return NULL;
  255. }
  256. return (void *)addr;
  257. }
  258. static void __dma_free_remap(void *cpu_addr, size_t size)
  259. {
  260. unsigned int flags = VM_ARM_DMA_CONSISTENT | VM_USERMAP;
  261. struct vm_struct *area = find_vm_area(cpu_addr);
  262. if (!area || (area->flags & flags) != flags) {
  263. WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
  264. return;
  265. }
  266. unmap_kernel_range((unsigned long)cpu_addr, size);
  267. vunmap(cpu_addr);
  268. }
  269. #define DEFAULT_DMA_COHERENT_POOL_SIZE SZ_256K
  270. struct dma_pool {
  271. size_t size;
  272. spinlock_t lock;
  273. unsigned long *bitmap;
  274. unsigned long nr_pages;
  275. void *vaddr;
  276. struct page **pages;
  277. };
  278. static struct dma_pool atomic_pool = {
  279. .size = DEFAULT_DMA_COHERENT_POOL_SIZE,
  280. };
  281. static int __init early_coherent_pool(char *p)
  282. {
  283. atomic_pool.size = memparse(p, &p);
  284. return 0;
  285. }
  286. early_param("coherent_pool", early_coherent_pool);
  287. void __init init_dma_coherent_pool_size(unsigned long size)
  288. {
  289. /*
  290. * Catch any attempt to set the pool size too late.
  291. */
  292. BUG_ON(atomic_pool.vaddr);
  293. /*
  294. * Set architecture specific coherent pool size only if
  295. * it has not been changed by kernel command line parameter.
  296. */
  297. if (atomic_pool.size == DEFAULT_DMA_COHERENT_POOL_SIZE)
  298. atomic_pool.size = size;
  299. }
  300. /*
  301. * Initialise the coherent pool for atomic allocations.
  302. */
  303. static int __init atomic_pool_init(void)
  304. {
  305. struct dma_pool *pool = &atomic_pool;
  306. pgprot_t prot = pgprot_dmacoherent(pgprot_kernel);
  307. gfp_t gfp = GFP_KERNEL | GFP_DMA;
  308. unsigned long nr_pages = pool->size >> PAGE_SHIFT;
  309. unsigned long *bitmap;
  310. struct page *page;
  311. struct page **pages;
  312. void *ptr;
  313. int bitmap_size = BITS_TO_LONGS(nr_pages) * sizeof(long);
  314. bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  315. if (!bitmap)
  316. goto no_bitmap;
  317. pages = kzalloc(nr_pages * sizeof(struct page *), GFP_KERNEL);
  318. if (!pages)
  319. goto no_pages;
  320. if (IS_ENABLED(CONFIG_CMA))
  321. ptr = __alloc_from_contiguous(NULL, pool->size, prot, &page,
  322. atomic_pool_init);
  323. else
  324. ptr = __alloc_remap_buffer(NULL, pool->size, gfp, prot, &page,
  325. atomic_pool_init);
  326. if (ptr) {
  327. int i;
  328. for (i = 0; i < nr_pages; i++)
  329. pages[i] = page + i;
  330. spin_lock_init(&pool->lock);
  331. pool->vaddr = ptr;
  332. pool->pages = pages;
  333. pool->bitmap = bitmap;
  334. pool->nr_pages = nr_pages;
  335. pr_info("DMA: preallocated %u KiB pool for atomic coherent allocations\n",
  336. (unsigned)pool->size / 1024);
  337. return 0;
  338. }
  339. kfree(pages);
  340. no_pages:
  341. kfree(bitmap);
  342. no_bitmap:
  343. pr_err("DMA: failed to allocate %u KiB pool for atomic coherent allocation\n",
  344. (unsigned)pool->size / 1024);
  345. return -ENOMEM;
  346. }
  347. /*
  348. * CMA is activated by core_initcall, so we must be called after it.
  349. */
  350. postcore_initcall(atomic_pool_init);
  351. struct dma_contig_early_reserve {
  352. phys_addr_t base;
  353. unsigned long size;
  354. };
  355. static struct dma_contig_early_reserve dma_mmu_remap[MAX_CMA_AREAS] __initdata;
  356. static int dma_mmu_remap_num __initdata;
  357. void __init dma_contiguous_early_fixup(phys_addr_t base, unsigned long size)
  358. {
  359. dma_mmu_remap[dma_mmu_remap_num].base = base;
  360. dma_mmu_remap[dma_mmu_remap_num].size = size;
  361. dma_mmu_remap_num++;
  362. }
  363. void __init dma_contiguous_remap(void)
  364. {
  365. int i;
  366. for (i = 0; i < dma_mmu_remap_num; i++) {
  367. phys_addr_t start = dma_mmu_remap[i].base;
  368. phys_addr_t end = start + dma_mmu_remap[i].size;
  369. struct map_desc map;
  370. unsigned long addr;
  371. if (end > arm_lowmem_limit)
  372. end = arm_lowmem_limit;
  373. if (start >= end)
  374. continue;
  375. map.pfn = __phys_to_pfn(start);
  376. map.virtual = __phys_to_virt(start);
  377. map.length = end - start;
  378. map.type = MT_MEMORY_DMA_READY;
  379. /*
  380. * Clear previous low-memory mapping
  381. */
  382. for (addr = __phys_to_virt(start); addr < __phys_to_virt(end);
  383. addr += PMD_SIZE)
  384. pmd_clear(pmd_off_k(addr));
  385. iotable_init(&map, 1);
  386. }
  387. }
  388. static int __dma_update_pte(pte_t *pte, pgtable_t token, unsigned long addr,
  389. void *data)
  390. {
  391. struct page *page = virt_to_page(addr);
  392. pgprot_t prot = *(pgprot_t *)data;
  393. set_pte_ext(pte, mk_pte(page, prot), 0);
  394. return 0;
  395. }
  396. static void __dma_remap(struct page *page, size_t size, pgprot_t prot)
  397. {
  398. unsigned long start = (unsigned long) page_address(page);
  399. unsigned end = start + size;
  400. apply_to_page_range(&init_mm, start, size, __dma_update_pte, &prot);
  401. dsb();
  402. flush_tlb_kernel_range(start, end);
  403. }
  404. static void *__alloc_remap_buffer(struct device *dev, size_t size, gfp_t gfp,
  405. pgprot_t prot, struct page **ret_page,
  406. const void *caller)
  407. {
  408. struct page *page;
  409. void *ptr;
  410. page = __dma_alloc_buffer(dev, size, gfp);
  411. if (!page)
  412. return NULL;
  413. ptr = __dma_alloc_remap(page, size, gfp, prot, caller);
  414. if (!ptr) {
  415. __dma_free_buffer(page, size);
  416. return NULL;
  417. }
  418. *ret_page = page;
  419. return ptr;
  420. }
  421. static void *__alloc_from_pool(size_t size, struct page **ret_page)
  422. {
  423. struct dma_pool *pool = &atomic_pool;
  424. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  425. unsigned int pageno;
  426. unsigned long flags;
  427. void *ptr = NULL;
  428. unsigned long align_mask;
  429. if (!pool->vaddr) {
  430. WARN(1, "coherent pool not initialised!\n");
  431. return NULL;
  432. }
  433. /*
  434. * Align the region allocation - allocations from pool are rather
  435. * small, so align them to their order in pages, minimum is a page
  436. * size. This helps reduce fragmentation of the DMA space.
  437. */
  438. align_mask = (1 << get_order(size)) - 1;
  439. spin_lock_irqsave(&pool->lock, flags);
  440. pageno = bitmap_find_next_zero_area(pool->bitmap, pool->nr_pages,
  441. 0, count, align_mask);
  442. if (pageno < pool->nr_pages) {
  443. bitmap_set(pool->bitmap, pageno, count);
  444. ptr = pool->vaddr + PAGE_SIZE * pageno;
  445. *ret_page = pool->pages[pageno];
  446. } else {
  447. pr_err_once("ERROR: %u KiB atomic DMA coherent pool is too small!\n"
  448. "Please increase it with coherent_pool= kernel parameter!\n",
  449. (unsigned)pool->size / 1024);
  450. }
  451. spin_unlock_irqrestore(&pool->lock, flags);
  452. return ptr;
  453. }
  454. static bool __in_atomic_pool(void *start, size_t size)
  455. {
  456. struct dma_pool *pool = &atomic_pool;
  457. void *end = start + size;
  458. void *pool_start = pool->vaddr;
  459. void *pool_end = pool->vaddr + pool->size;
  460. if (start < pool_start || start >= pool_end)
  461. return false;
  462. if (end <= pool_end)
  463. return true;
  464. WARN(1, "Wrong coherent size(%p-%p) from atomic pool(%p-%p)\n",
  465. start, end - 1, pool_start, pool_end - 1);
  466. return false;
  467. }
  468. static int __free_from_pool(void *start, size_t size)
  469. {
  470. struct dma_pool *pool = &atomic_pool;
  471. unsigned long pageno, count;
  472. unsigned long flags;
  473. if (!__in_atomic_pool(start, size))
  474. return 0;
  475. pageno = (start - pool->vaddr) >> PAGE_SHIFT;
  476. count = size >> PAGE_SHIFT;
  477. spin_lock_irqsave(&pool->lock, flags);
  478. bitmap_clear(pool->bitmap, pageno, count);
  479. spin_unlock_irqrestore(&pool->lock, flags);
  480. return 1;
  481. }
  482. static void *__alloc_from_contiguous(struct device *dev, size_t size,
  483. pgprot_t prot, struct page **ret_page,
  484. const void *caller)
  485. {
  486. unsigned long order = get_order(size);
  487. size_t count = size >> PAGE_SHIFT;
  488. struct page *page;
  489. void *ptr;
  490. page = dma_alloc_from_contiguous(dev, count, order);
  491. if (!page)
  492. return NULL;
  493. __dma_clear_buffer(page, size);
  494. if (PageHighMem(page)) {
  495. ptr = __dma_alloc_remap(page, size, GFP_KERNEL, prot, caller);
  496. if (!ptr) {
  497. dma_release_from_contiguous(dev, page, count);
  498. return NULL;
  499. }
  500. } else {
  501. __dma_remap(page, size, prot);
  502. ptr = page_address(page);
  503. }
  504. *ret_page = page;
  505. return ptr;
  506. }
  507. static void __free_from_contiguous(struct device *dev, struct page *page,
  508. void *cpu_addr, size_t size)
  509. {
  510. if (PageHighMem(page))
  511. __dma_free_remap(cpu_addr, size);
  512. else
  513. __dma_remap(page, size, pgprot_kernel);
  514. dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT);
  515. }
  516. static inline pgprot_t __get_dma_pgprot(struct dma_attrs *attrs, pgprot_t prot)
  517. {
  518. prot = dma_get_attr(DMA_ATTR_WRITE_COMBINE, attrs) ?
  519. pgprot_writecombine(prot) :
  520. pgprot_dmacoherent(prot);
  521. return prot;
  522. }
  523. #define nommu() 0
  524. #else /* !CONFIG_MMU */
  525. #define nommu() 1
  526. #define __get_dma_pgprot(attrs, prot) __pgprot(0)
  527. #define __alloc_remap_buffer(dev, size, gfp, prot, ret, c) NULL
  528. #define __alloc_from_pool(size, ret_page) NULL
  529. #define __alloc_from_contiguous(dev, size, prot, ret, c) NULL
  530. #define __free_from_pool(cpu_addr, size) 0
  531. #define __free_from_contiguous(dev, page, cpu_addr, size) do { } while (0)
  532. #define __dma_free_remap(cpu_addr, size) do { } while (0)
  533. #endif /* CONFIG_MMU */
  534. static void *__alloc_simple_buffer(struct device *dev, size_t size, gfp_t gfp,
  535. struct page **ret_page)
  536. {
  537. struct page *page;
  538. page = __dma_alloc_buffer(dev, size, gfp);
  539. if (!page)
  540. return NULL;
  541. *ret_page = page;
  542. return page_address(page);
  543. }
  544. static void *__dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
  545. gfp_t gfp, pgprot_t prot, bool is_coherent, const void *caller)
  546. {
  547. u64 mask = get_coherent_dma_mask(dev);
  548. struct page *page = NULL;
  549. void *addr;
  550. #ifdef CONFIG_DMA_API_DEBUG
  551. u64 limit = (mask + 1) & ~mask;
  552. if (limit && size >= limit) {
  553. dev_warn(dev, "coherent allocation too big (requested %#x mask %#llx)\n",
  554. size, mask);
  555. return NULL;
  556. }
  557. #endif
  558. if (!mask)
  559. return NULL;
  560. if (mask < 0xffffffffULL)
  561. gfp |= GFP_DMA;
  562. /*
  563. * Following is a work-around (a.k.a. hack) to prevent pages
  564. * with __GFP_COMP being passed to split_page() which cannot
  565. * handle them. The real problem is that this flag probably
  566. * should be 0 on ARM as it is not supported on this
  567. * platform; see CONFIG_HUGETLBFS.
  568. */
  569. gfp &= ~(__GFP_COMP);
  570. *handle = DMA_ERROR_CODE;
  571. size = PAGE_ALIGN(size);
  572. if (is_coherent || nommu())
  573. addr = __alloc_simple_buffer(dev, size, gfp, &page);
  574. else if (!(gfp & __GFP_WAIT))
  575. addr = __alloc_from_pool(size, &page);
  576. else if (!IS_ENABLED(CONFIG_CMA))
  577. addr = __alloc_remap_buffer(dev, size, gfp, prot, &page, caller);
  578. else
  579. addr = __alloc_from_contiguous(dev, size, prot, &page, caller);
  580. if (addr)
  581. *handle = pfn_to_dma(dev, page_to_pfn(page));
  582. return addr;
  583. }
  584. /*
  585. * Allocate DMA-coherent memory space and return both the kernel remapped
  586. * virtual and bus address for that space.
  587. */
  588. void *arm_dma_alloc(struct device *dev, size_t size, dma_addr_t *handle,
  589. gfp_t gfp, struct dma_attrs *attrs)
  590. {
  591. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  592. void *memory;
  593. if (dma_alloc_from_coherent(dev, size, handle, &memory))
  594. return memory;
  595. return __dma_alloc(dev, size, handle, gfp, prot, false,
  596. __builtin_return_address(0));
  597. }
  598. static void *arm_coherent_dma_alloc(struct device *dev, size_t size,
  599. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
  600. {
  601. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  602. void *memory;
  603. if (dma_alloc_from_coherent(dev, size, handle, &memory))
  604. return memory;
  605. return __dma_alloc(dev, size, handle, gfp, prot, true,
  606. __builtin_return_address(0));
  607. }
  608. /*
  609. * Create userspace mapping for the DMA-coherent memory.
  610. */
  611. int arm_dma_mmap(struct device *dev, struct vm_area_struct *vma,
  612. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  613. struct dma_attrs *attrs)
  614. {
  615. int ret = -ENXIO;
  616. #ifdef CONFIG_MMU
  617. unsigned long nr_vma_pages = (vma->vm_end - vma->vm_start) >> PAGE_SHIFT;
  618. unsigned long nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
  619. unsigned long pfn = dma_to_pfn(dev, dma_addr);
  620. unsigned long off = vma->vm_pgoff;
  621. vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
  622. if (dma_mmap_from_coherent(dev, vma, cpu_addr, size, &ret))
  623. return ret;
  624. if (off < nr_pages && nr_vma_pages <= (nr_pages - off)) {
  625. ret = remap_pfn_range(vma, vma->vm_start,
  626. pfn + off,
  627. vma->vm_end - vma->vm_start,
  628. vma->vm_page_prot);
  629. }
  630. #endif /* CONFIG_MMU */
  631. return ret;
  632. }
  633. /*
  634. * Free a buffer as defined by the above mapping.
  635. */
  636. static void __arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
  637. dma_addr_t handle, struct dma_attrs *attrs,
  638. bool is_coherent)
  639. {
  640. struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
  641. if (dma_release_from_coherent(dev, get_order(size), cpu_addr))
  642. return;
  643. size = PAGE_ALIGN(size);
  644. if (is_coherent || nommu()) {
  645. __dma_free_buffer(page, size);
  646. } else if (__free_from_pool(cpu_addr, size)) {
  647. return;
  648. } else if (!IS_ENABLED(CONFIG_CMA)) {
  649. __dma_free_remap(cpu_addr, size);
  650. __dma_free_buffer(page, size);
  651. } else {
  652. /*
  653. * Non-atomic allocations cannot be freed with IRQs disabled
  654. */
  655. WARN_ON(irqs_disabled());
  656. __free_from_contiguous(dev, page, cpu_addr, size);
  657. }
  658. }
  659. void arm_dma_free(struct device *dev, size_t size, void *cpu_addr,
  660. dma_addr_t handle, struct dma_attrs *attrs)
  661. {
  662. __arm_dma_free(dev, size, cpu_addr, handle, attrs, false);
  663. }
  664. static void arm_coherent_dma_free(struct device *dev, size_t size, void *cpu_addr,
  665. dma_addr_t handle, struct dma_attrs *attrs)
  666. {
  667. __arm_dma_free(dev, size, cpu_addr, handle, attrs, true);
  668. }
  669. int arm_dma_get_sgtable(struct device *dev, struct sg_table *sgt,
  670. void *cpu_addr, dma_addr_t handle, size_t size,
  671. struct dma_attrs *attrs)
  672. {
  673. struct page *page = pfn_to_page(dma_to_pfn(dev, handle));
  674. int ret;
  675. ret = sg_alloc_table(sgt, 1, GFP_KERNEL);
  676. if (unlikely(ret))
  677. return ret;
  678. sg_set_page(sgt->sgl, page, PAGE_ALIGN(size), 0);
  679. return 0;
  680. }
  681. static void dma_cache_maint_page(struct page *page, unsigned long offset,
  682. size_t size, enum dma_data_direction dir,
  683. void (*op)(const void *, size_t, int))
  684. {
  685. unsigned long pfn;
  686. size_t left = size;
  687. pfn = page_to_pfn(page) + offset / PAGE_SIZE;
  688. offset %= PAGE_SIZE;
  689. /*
  690. * A single sg entry may refer to multiple physically contiguous
  691. * pages. But we still need to process highmem pages individually.
  692. * If highmem is not configured then the bulk of this loop gets
  693. * optimized out.
  694. */
  695. do {
  696. size_t len = left;
  697. void *vaddr;
  698. page = pfn_to_page(pfn);
  699. if (PageHighMem(page)) {
  700. if (len + offset > PAGE_SIZE)
  701. len = PAGE_SIZE - offset;
  702. if (cache_is_vipt_nonaliasing()) {
  703. vaddr = kmap_atomic(page);
  704. op(vaddr + offset, len, dir);
  705. kunmap_atomic(vaddr);
  706. } else {
  707. vaddr = kmap_high_get(page);
  708. if (vaddr) {
  709. op(vaddr + offset, len, dir);
  710. kunmap_high(page);
  711. }
  712. }
  713. } else {
  714. vaddr = page_address(page) + offset;
  715. op(vaddr, len, dir);
  716. }
  717. offset = 0;
  718. pfn++;
  719. left -= len;
  720. } while (left);
  721. }
  722. /*
  723. * Make an area consistent for devices.
  724. * Note: Drivers should NOT use this function directly, as it will break
  725. * platforms with CONFIG_DMABOUNCE.
  726. * Use the driver DMA support - see dma-mapping.h (dma_sync_*)
  727. */
  728. static void __dma_page_cpu_to_dev(struct page *page, unsigned long off,
  729. size_t size, enum dma_data_direction dir)
  730. {
  731. unsigned long paddr;
  732. dma_cache_maint_page(page, off, size, dir, dmac_map_area);
  733. paddr = page_to_phys(page) + off;
  734. if (dir == DMA_FROM_DEVICE) {
  735. outer_inv_range(paddr, paddr + size);
  736. } else {
  737. outer_clean_range(paddr, paddr + size);
  738. }
  739. /* FIXME: non-speculating: flush on bidirectional mappings? */
  740. }
  741. static void __dma_page_dev_to_cpu(struct page *page, unsigned long off,
  742. size_t size, enum dma_data_direction dir)
  743. {
  744. unsigned long paddr = page_to_phys(page) + off;
  745. /* FIXME: non-speculating: not required */
  746. /* don't bother invalidating if DMA to device */
  747. if (dir != DMA_TO_DEVICE)
  748. outer_inv_range(paddr, paddr + size);
  749. dma_cache_maint_page(page, off, size, dir, dmac_unmap_area);
  750. /*
  751. * Mark the D-cache clean for these pages to avoid extra flushing.
  752. */
  753. if (dir != DMA_TO_DEVICE && size >= PAGE_SIZE) {
  754. unsigned long pfn;
  755. size_t left = size;
  756. pfn = page_to_pfn(page) + off / PAGE_SIZE;
  757. off %= PAGE_SIZE;
  758. if (off) {
  759. pfn++;
  760. left -= PAGE_SIZE - off;
  761. }
  762. while (left >= PAGE_SIZE) {
  763. page = pfn_to_page(pfn++);
  764. set_bit(PG_dcache_clean, &page->flags);
  765. left -= PAGE_SIZE;
  766. }
  767. }
  768. }
  769. /**
  770. * arm_dma_map_sg - map a set of SG buffers for streaming mode DMA
  771. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  772. * @sg: list of buffers
  773. * @nents: number of buffers to map
  774. * @dir: DMA transfer direction
  775. *
  776. * Map a set of buffers described by scatterlist in streaming mode for DMA.
  777. * This is the scatter-gather version of the dma_map_single interface.
  778. * Here the scatter gather list elements are each tagged with the
  779. * appropriate dma address and length. They are obtained via
  780. * sg_dma_{address,length}.
  781. *
  782. * Device ownership issues as mentioned for dma_map_single are the same
  783. * here.
  784. */
  785. int arm_dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  786. enum dma_data_direction dir, struct dma_attrs *attrs)
  787. {
  788. struct dma_map_ops *ops = get_dma_ops(dev);
  789. struct scatterlist *s;
  790. int i, j;
  791. for_each_sg(sg, s, nents, i) {
  792. #ifdef CONFIG_NEED_SG_DMA_LENGTH
  793. s->dma_length = s->length;
  794. #endif
  795. s->dma_address = ops->map_page(dev, sg_page(s), s->offset,
  796. s->length, dir, attrs);
  797. if (dma_mapping_error(dev, s->dma_address))
  798. goto bad_mapping;
  799. }
  800. return nents;
  801. bad_mapping:
  802. for_each_sg(sg, s, i, j)
  803. ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
  804. return 0;
  805. }
  806. /**
  807. * arm_dma_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  808. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  809. * @sg: list of buffers
  810. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  811. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  812. *
  813. * Unmap a set of streaming mode DMA translations. Again, CPU access
  814. * rules concerning calls here are the same as for dma_unmap_single().
  815. */
  816. void arm_dma_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
  817. enum dma_data_direction dir, struct dma_attrs *attrs)
  818. {
  819. struct dma_map_ops *ops = get_dma_ops(dev);
  820. struct scatterlist *s;
  821. int i;
  822. for_each_sg(sg, s, nents, i)
  823. ops->unmap_page(dev, sg_dma_address(s), sg_dma_len(s), dir, attrs);
  824. }
  825. /**
  826. * arm_dma_sync_sg_for_cpu
  827. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  828. * @sg: list of buffers
  829. * @nents: number of buffers to map (returned from dma_map_sg)
  830. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  831. */
  832. void arm_dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
  833. int nents, enum dma_data_direction dir)
  834. {
  835. struct dma_map_ops *ops = get_dma_ops(dev);
  836. struct scatterlist *s;
  837. int i;
  838. for_each_sg(sg, s, nents, i)
  839. ops->sync_single_for_cpu(dev, sg_dma_address(s), s->length,
  840. dir);
  841. }
  842. /**
  843. * arm_dma_sync_sg_for_device
  844. * @dev: valid struct device pointer, or NULL for ISA and EISA-like devices
  845. * @sg: list of buffers
  846. * @nents: number of buffers to map (returned from dma_map_sg)
  847. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  848. */
  849. void arm_dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
  850. int nents, enum dma_data_direction dir)
  851. {
  852. struct dma_map_ops *ops = get_dma_ops(dev);
  853. struct scatterlist *s;
  854. int i;
  855. for_each_sg(sg, s, nents, i)
  856. ops->sync_single_for_device(dev, sg_dma_address(s), s->length,
  857. dir);
  858. }
  859. /*
  860. * Return whether the given device DMA address mask can be supported
  861. * properly. For example, if your device can only drive the low 24-bits
  862. * during bus mastering, then you would pass 0x00ffffff as the mask
  863. * to this function.
  864. */
  865. int dma_supported(struct device *dev, u64 mask)
  866. {
  867. if (mask < (u64)arm_dma_limit)
  868. return 0;
  869. return 1;
  870. }
  871. EXPORT_SYMBOL(dma_supported);
  872. int arm_dma_set_mask(struct device *dev, u64 dma_mask)
  873. {
  874. if (!dev->dma_mask || !dma_supported(dev, dma_mask))
  875. return -EIO;
  876. *dev->dma_mask = dma_mask;
  877. return 0;
  878. }
  879. #define PREALLOC_DMA_DEBUG_ENTRIES 4096
  880. static int __init dma_debug_do_init(void)
  881. {
  882. dma_debug_init(PREALLOC_DMA_DEBUG_ENTRIES);
  883. return 0;
  884. }
  885. fs_initcall(dma_debug_do_init);
  886. #ifdef CONFIG_ARM_DMA_USE_IOMMU
  887. /* IOMMU */
  888. static inline dma_addr_t __alloc_iova(struct dma_iommu_mapping *mapping,
  889. size_t size)
  890. {
  891. unsigned int order = get_order(size);
  892. unsigned int align = 0;
  893. unsigned int count, start;
  894. unsigned long flags;
  895. if (order > CONFIG_ARM_DMA_IOMMU_ALIGNMENT)
  896. order = CONFIG_ARM_DMA_IOMMU_ALIGNMENT;
  897. count = ((PAGE_ALIGN(size) >> PAGE_SHIFT) +
  898. (1 << mapping->order) - 1) >> mapping->order;
  899. if (order > mapping->order)
  900. align = (1 << (order - mapping->order)) - 1;
  901. spin_lock_irqsave(&mapping->lock, flags);
  902. start = bitmap_find_next_zero_area(mapping->bitmap, mapping->bits, 0,
  903. count, align);
  904. if (start > mapping->bits) {
  905. spin_unlock_irqrestore(&mapping->lock, flags);
  906. return DMA_ERROR_CODE;
  907. }
  908. bitmap_set(mapping->bitmap, start, count);
  909. spin_unlock_irqrestore(&mapping->lock, flags);
  910. return mapping->base + (start << (mapping->order + PAGE_SHIFT));
  911. }
  912. static inline void __free_iova(struct dma_iommu_mapping *mapping,
  913. dma_addr_t addr, size_t size)
  914. {
  915. unsigned int start = (addr - mapping->base) >>
  916. (mapping->order + PAGE_SHIFT);
  917. unsigned int count = ((size >> PAGE_SHIFT) +
  918. (1 << mapping->order) - 1) >> mapping->order;
  919. unsigned long flags;
  920. spin_lock_irqsave(&mapping->lock, flags);
  921. bitmap_clear(mapping->bitmap, start, count);
  922. spin_unlock_irqrestore(&mapping->lock, flags);
  923. }
  924. static struct page **__iommu_alloc_buffer(struct device *dev, size_t size,
  925. gfp_t gfp, struct dma_attrs *attrs)
  926. {
  927. struct page **pages;
  928. int count = size >> PAGE_SHIFT;
  929. int array_size = count * sizeof(struct page *);
  930. int i = 0;
  931. if (array_size <= PAGE_SIZE)
  932. pages = kzalloc(array_size, gfp);
  933. else
  934. pages = vzalloc(array_size);
  935. if (!pages)
  936. return NULL;
  937. if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs))
  938. {
  939. unsigned long order = get_order(size);
  940. struct page *page;
  941. page = dma_alloc_from_contiguous(dev, count, order);
  942. if (!page)
  943. goto error;
  944. __dma_clear_buffer(page, size);
  945. for (i = 0; i < count; i++)
  946. pages[i] = page + i;
  947. return pages;
  948. }
  949. /*
  950. * IOMMU can map any pages, so himem can also be used here
  951. */
  952. gfp |= __GFP_NOWARN | __GFP_HIGHMEM;
  953. while (count) {
  954. int j, order = __fls(count);
  955. pages[i] = alloc_pages(gfp, order);
  956. while (!pages[i] && order)
  957. pages[i] = alloc_pages(gfp, --order);
  958. if (!pages[i])
  959. goto error;
  960. if (order) {
  961. split_page(pages[i], order);
  962. j = 1 << order;
  963. while (--j)
  964. pages[i + j] = pages[i] + j;
  965. }
  966. __dma_clear_buffer(pages[i], PAGE_SIZE << order);
  967. i += 1 << order;
  968. count -= 1 << order;
  969. }
  970. return pages;
  971. error:
  972. while (i--)
  973. if (pages[i])
  974. __free_pages(pages[i], 0);
  975. if (array_size <= PAGE_SIZE)
  976. kfree(pages);
  977. else
  978. vfree(pages);
  979. return NULL;
  980. }
  981. static int __iommu_free_buffer(struct device *dev, struct page **pages,
  982. size_t size, struct dma_attrs *attrs)
  983. {
  984. int count = size >> PAGE_SHIFT;
  985. int array_size = count * sizeof(struct page *);
  986. int i;
  987. if (dma_get_attr(DMA_ATTR_FORCE_CONTIGUOUS, attrs)) {
  988. dma_release_from_contiguous(dev, pages[0], count);
  989. } else {
  990. for (i = 0; i < count; i++)
  991. if (pages[i])
  992. __free_pages(pages[i], 0);
  993. }
  994. if (array_size <= PAGE_SIZE)
  995. kfree(pages);
  996. else
  997. vfree(pages);
  998. return 0;
  999. }
  1000. /*
  1001. * Create a CPU mapping for a specified pages
  1002. */
  1003. static void *
  1004. __iommu_alloc_remap(struct page **pages, size_t size, gfp_t gfp, pgprot_t prot,
  1005. const void *caller)
  1006. {
  1007. unsigned int i, nr_pages = PAGE_ALIGN(size) >> PAGE_SHIFT;
  1008. struct vm_struct *area;
  1009. unsigned long p;
  1010. area = get_vm_area_caller(size, VM_ARM_DMA_CONSISTENT | VM_USERMAP,
  1011. caller);
  1012. if (!area)
  1013. return NULL;
  1014. area->pages = pages;
  1015. area->nr_pages = nr_pages;
  1016. p = (unsigned long)area->addr;
  1017. for (i = 0; i < nr_pages; i++) {
  1018. phys_addr_t phys = __pfn_to_phys(page_to_pfn(pages[i]));
  1019. if (ioremap_page_range(p, p + PAGE_SIZE, phys, prot))
  1020. goto err;
  1021. p += PAGE_SIZE;
  1022. }
  1023. return area->addr;
  1024. err:
  1025. unmap_kernel_range((unsigned long)area->addr, size);
  1026. vunmap(area->addr);
  1027. return NULL;
  1028. }
  1029. /*
  1030. * Create a mapping in device IO address space for specified pages
  1031. */
  1032. static dma_addr_t
  1033. __iommu_create_mapping(struct device *dev, struct page **pages, size_t size)
  1034. {
  1035. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1036. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  1037. dma_addr_t dma_addr, iova;
  1038. int i, ret = DMA_ERROR_CODE;
  1039. dma_addr = __alloc_iova(mapping, size);
  1040. if (dma_addr == DMA_ERROR_CODE)
  1041. return dma_addr;
  1042. iova = dma_addr;
  1043. for (i = 0; i < count; ) {
  1044. unsigned int next_pfn = page_to_pfn(pages[i]) + 1;
  1045. phys_addr_t phys = page_to_phys(pages[i]);
  1046. unsigned int len, j;
  1047. for (j = i + 1; j < count; j++, next_pfn++)
  1048. if (page_to_pfn(pages[j]) != next_pfn)
  1049. break;
  1050. len = (j - i) << PAGE_SHIFT;
  1051. ret = iommu_map(mapping->domain, iova, phys, len, 0);
  1052. if (ret < 0)
  1053. goto fail;
  1054. iova += len;
  1055. i = j;
  1056. }
  1057. return dma_addr;
  1058. fail:
  1059. iommu_unmap(mapping->domain, dma_addr, iova-dma_addr);
  1060. __free_iova(mapping, dma_addr, size);
  1061. return DMA_ERROR_CODE;
  1062. }
  1063. static int __iommu_remove_mapping(struct device *dev, dma_addr_t iova, size_t size)
  1064. {
  1065. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1066. /*
  1067. * add optional in-page offset from iova to size and align
  1068. * result to page size
  1069. */
  1070. size = PAGE_ALIGN((iova & ~PAGE_MASK) + size);
  1071. iova &= PAGE_MASK;
  1072. iommu_unmap(mapping->domain, iova, size);
  1073. __free_iova(mapping, iova, size);
  1074. return 0;
  1075. }
  1076. static struct page **__atomic_get_pages(void *addr)
  1077. {
  1078. struct dma_pool *pool = &atomic_pool;
  1079. struct page **pages = pool->pages;
  1080. int offs = (addr - pool->vaddr) >> PAGE_SHIFT;
  1081. return pages + offs;
  1082. }
  1083. static struct page **__iommu_get_pages(void *cpu_addr, struct dma_attrs *attrs)
  1084. {
  1085. struct vm_struct *area;
  1086. if (__in_atomic_pool(cpu_addr, PAGE_SIZE))
  1087. return __atomic_get_pages(cpu_addr);
  1088. if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
  1089. return cpu_addr;
  1090. area = find_vm_area(cpu_addr);
  1091. if (area && (area->flags & VM_ARM_DMA_CONSISTENT))
  1092. return area->pages;
  1093. return NULL;
  1094. }
  1095. static void *__iommu_alloc_atomic(struct device *dev, size_t size,
  1096. dma_addr_t *handle)
  1097. {
  1098. struct page *page;
  1099. void *addr;
  1100. addr = __alloc_from_pool(size, &page);
  1101. if (!addr)
  1102. return NULL;
  1103. *handle = __iommu_create_mapping(dev, &page, size);
  1104. if (*handle == DMA_ERROR_CODE)
  1105. goto err_mapping;
  1106. return addr;
  1107. err_mapping:
  1108. __free_from_pool(addr, size);
  1109. return NULL;
  1110. }
  1111. static void __iommu_free_atomic(struct device *dev, void *cpu_addr,
  1112. dma_addr_t handle, size_t size)
  1113. {
  1114. __iommu_remove_mapping(dev, handle, size);
  1115. __free_from_pool(cpu_addr, size);
  1116. }
  1117. static void *arm_iommu_alloc_attrs(struct device *dev, size_t size,
  1118. dma_addr_t *handle, gfp_t gfp, struct dma_attrs *attrs)
  1119. {
  1120. pgprot_t prot = __get_dma_pgprot(attrs, pgprot_kernel);
  1121. struct page **pages;
  1122. void *addr = NULL;
  1123. *handle = DMA_ERROR_CODE;
  1124. size = PAGE_ALIGN(size);
  1125. if (gfp & GFP_ATOMIC)
  1126. return __iommu_alloc_atomic(dev, size, handle);
  1127. /*
  1128. * Following is a work-around (a.k.a. hack) to prevent pages
  1129. * with __GFP_COMP being passed to split_page() which cannot
  1130. * handle them. The real problem is that this flag probably
  1131. * should be 0 on ARM as it is not supported on this
  1132. * platform; see CONFIG_HUGETLBFS.
  1133. */
  1134. gfp &= ~(__GFP_COMP);
  1135. pages = __iommu_alloc_buffer(dev, size, gfp, attrs);
  1136. if (!pages)
  1137. return NULL;
  1138. *handle = __iommu_create_mapping(dev, pages, size);
  1139. if (*handle == DMA_ERROR_CODE)
  1140. goto err_buffer;
  1141. if (dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs))
  1142. return pages;
  1143. addr = __iommu_alloc_remap(pages, size, gfp, prot,
  1144. __builtin_return_address(0));
  1145. if (!addr)
  1146. goto err_mapping;
  1147. return addr;
  1148. err_mapping:
  1149. __iommu_remove_mapping(dev, *handle, size);
  1150. err_buffer:
  1151. __iommu_free_buffer(dev, pages, size, attrs);
  1152. return NULL;
  1153. }
  1154. static int arm_iommu_mmap_attrs(struct device *dev, struct vm_area_struct *vma,
  1155. void *cpu_addr, dma_addr_t dma_addr, size_t size,
  1156. struct dma_attrs *attrs)
  1157. {
  1158. unsigned long uaddr = vma->vm_start;
  1159. unsigned long usize = vma->vm_end - vma->vm_start;
  1160. struct page **pages = __iommu_get_pages(cpu_addr, attrs);
  1161. vma->vm_page_prot = __get_dma_pgprot(attrs, vma->vm_page_prot);
  1162. if (!pages)
  1163. return -ENXIO;
  1164. do {
  1165. int ret = vm_insert_page(vma, uaddr, *pages++);
  1166. if (ret) {
  1167. pr_err("Remapping memory failed: %d\n", ret);
  1168. return ret;
  1169. }
  1170. uaddr += PAGE_SIZE;
  1171. usize -= PAGE_SIZE;
  1172. } while (usize > 0);
  1173. return 0;
  1174. }
  1175. /*
  1176. * free a page as defined by the above mapping.
  1177. * Must not be called with IRQs disabled.
  1178. */
  1179. void arm_iommu_free_attrs(struct device *dev, size_t size, void *cpu_addr,
  1180. dma_addr_t handle, struct dma_attrs *attrs)
  1181. {
  1182. struct page **pages;
  1183. size = PAGE_ALIGN(size);
  1184. if (__in_atomic_pool(cpu_addr, size)) {
  1185. __iommu_free_atomic(dev, cpu_addr, handle, size);
  1186. return;
  1187. }
  1188. pages = __iommu_get_pages(cpu_addr, attrs);
  1189. if (!pages) {
  1190. WARN(1, "trying to free invalid coherent area: %p\n", cpu_addr);
  1191. return;
  1192. }
  1193. if (!dma_get_attr(DMA_ATTR_NO_KERNEL_MAPPING, attrs)) {
  1194. unmap_kernel_range((unsigned long)cpu_addr, size);
  1195. vunmap(cpu_addr);
  1196. }
  1197. __iommu_remove_mapping(dev, handle, size);
  1198. __iommu_free_buffer(dev, pages, size, attrs);
  1199. }
  1200. static int arm_iommu_get_sgtable(struct device *dev, struct sg_table *sgt,
  1201. void *cpu_addr, dma_addr_t dma_addr,
  1202. size_t size, struct dma_attrs *attrs)
  1203. {
  1204. unsigned int count = PAGE_ALIGN(size) >> PAGE_SHIFT;
  1205. struct page **pages = __iommu_get_pages(cpu_addr, attrs);
  1206. if (!pages)
  1207. return -ENXIO;
  1208. return sg_alloc_table_from_pages(sgt, pages, count, 0, size,
  1209. GFP_KERNEL);
  1210. }
  1211. /*
  1212. * Map a part of the scatter-gather list into contiguous io address space
  1213. */
  1214. static int __map_sg_chunk(struct device *dev, struct scatterlist *sg,
  1215. size_t size, dma_addr_t *handle,
  1216. enum dma_data_direction dir, struct dma_attrs *attrs,
  1217. bool is_coherent)
  1218. {
  1219. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1220. dma_addr_t iova, iova_base;
  1221. int ret = 0;
  1222. unsigned int count;
  1223. struct scatterlist *s;
  1224. size = PAGE_ALIGN(size);
  1225. *handle = DMA_ERROR_CODE;
  1226. iova_base = iova = __alloc_iova(mapping, size);
  1227. if (iova == DMA_ERROR_CODE)
  1228. return -ENOMEM;
  1229. for (count = 0, s = sg; count < (size >> PAGE_SHIFT); s = sg_next(s)) {
  1230. phys_addr_t phys = page_to_phys(sg_page(s));
  1231. unsigned int len = PAGE_ALIGN(s->offset + s->length);
  1232. if (!is_coherent &&
  1233. !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1234. __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
  1235. ret = iommu_map(mapping->domain, iova, phys, len, 0);
  1236. if (ret < 0)
  1237. goto fail;
  1238. count += len >> PAGE_SHIFT;
  1239. iova += len;
  1240. }
  1241. *handle = iova_base;
  1242. return 0;
  1243. fail:
  1244. iommu_unmap(mapping->domain, iova_base, count * PAGE_SIZE);
  1245. __free_iova(mapping, iova_base, size);
  1246. return ret;
  1247. }
  1248. static int __iommu_map_sg(struct device *dev, struct scatterlist *sg, int nents,
  1249. enum dma_data_direction dir, struct dma_attrs *attrs,
  1250. bool is_coherent)
  1251. {
  1252. struct scatterlist *s = sg, *dma = sg, *start = sg;
  1253. int i, count = 0;
  1254. unsigned int offset = s->offset;
  1255. unsigned int size = s->offset + s->length;
  1256. unsigned int max = dma_get_max_seg_size(dev);
  1257. for (i = 1; i < nents; i++) {
  1258. s = sg_next(s);
  1259. s->dma_address = DMA_ERROR_CODE;
  1260. s->dma_length = 0;
  1261. if (s->offset || (size & ~PAGE_MASK) || size + s->length > max) {
  1262. if (__map_sg_chunk(dev, start, size, &dma->dma_address,
  1263. dir, attrs, is_coherent) < 0)
  1264. goto bad_mapping;
  1265. dma->dma_address += offset;
  1266. dma->dma_length = size - offset;
  1267. size = offset = s->offset;
  1268. start = s;
  1269. dma = sg_next(dma);
  1270. count += 1;
  1271. }
  1272. size += s->length;
  1273. }
  1274. if (__map_sg_chunk(dev, start, size, &dma->dma_address, dir, attrs,
  1275. is_coherent) < 0)
  1276. goto bad_mapping;
  1277. dma->dma_address += offset;
  1278. dma->dma_length = size - offset;
  1279. return count+1;
  1280. bad_mapping:
  1281. for_each_sg(sg, s, count, i)
  1282. __iommu_remove_mapping(dev, sg_dma_address(s), sg_dma_len(s));
  1283. return 0;
  1284. }
  1285. /**
  1286. * arm_coherent_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  1287. * @dev: valid struct device pointer
  1288. * @sg: list of buffers
  1289. * @nents: number of buffers to map
  1290. * @dir: DMA transfer direction
  1291. *
  1292. * Map a set of i/o coherent buffers described by scatterlist in streaming
  1293. * mode for DMA. The scatter gather list elements are merged together (if
  1294. * possible) and tagged with the appropriate dma address and length. They are
  1295. * obtained via sg_dma_{address,length}.
  1296. */
  1297. int arm_coherent_iommu_map_sg(struct device *dev, struct scatterlist *sg,
  1298. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1299. {
  1300. return __iommu_map_sg(dev, sg, nents, dir, attrs, true);
  1301. }
  1302. /**
  1303. * arm_iommu_map_sg - map a set of SG buffers for streaming mode DMA
  1304. * @dev: valid struct device pointer
  1305. * @sg: list of buffers
  1306. * @nents: number of buffers to map
  1307. * @dir: DMA transfer direction
  1308. *
  1309. * Map a set of buffers described by scatterlist in streaming mode for DMA.
  1310. * The scatter gather list elements are merged together (if possible) and
  1311. * tagged with the appropriate dma address and length. They are obtained via
  1312. * sg_dma_{address,length}.
  1313. */
  1314. int arm_iommu_map_sg(struct device *dev, struct scatterlist *sg,
  1315. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1316. {
  1317. return __iommu_map_sg(dev, sg, nents, dir, attrs, false);
  1318. }
  1319. static void __iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
  1320. int nents, enum dma_data_direction dir, struct dma_attrs *attrs,
  1321. bool is_coherent)
  1322. {
  1323. struct scatterlist *s;
  1324. int i;
  1325. for_each_sg(sg, s, nents, i) {
  1326. if (sg_dma_len(s))
  1327. __iommu_remove_mapping(dev, sg_dma_address(s),
  1328. sg_dma_len(s));
  1329. if (!is_coherent &&
  1330. !dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1331. __dma_page_dev_to_cpu(sg_page(s), s->offset,
  1332. s->length, dir);
  1333. }
  1334. }
  1335. /**
  1336. * arm_coherent_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  1337. * @dev: valid struct device pointer
  1338. * @sg: list of buffers
  1339. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  1340. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1341. *
  1342. * Unmap a set of streaming mode DMA translations. Again, CPU access
  1343. * rules concerning calls here are the same as for dma_unmap_single().
  1344. */
  1345. void arm_coherent_iommu_unmap_sg(struct device *dev, struct scatterlist *sg,
  1346. int nents, enum dma_data_direction dir, struct dma_attrs *attrs)
  1347. {
  1348. __iommu_unmap_sg(dev, sg, nents, dir, attrs, true);
  1349. }
  1350. /**
  1351. * arm_iommu_unmap_sg - unmap a set of SG buffers mapped by dma_map_sg
  1352. * @dev: valid struct device pointer
  1353. * @sg: list of buffers
  1354. * @nents: number of buffers to unmap (same as was passed to dma_map_sg)
  1355. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1356. *
  1357. * Unmap a set of streaming mode DMA translations. Again, CPU access
  1358. * rules concerning calls here are the same as for dma_unmap_single().
  1359. */
  1360. void arm_iommu_unmap_sg(struct device *dev, struct scatterlist *sg, int nents,
  1361. enum dma_data_direction dir, struct dma_attrs *attrs)
  1362. {
  1363. __iommu_unmap_sg(dev, sg, nents, dir, attrs, false);
  1364. }
  1365. /**
  1366. * arm_iommu_sync_sg_for_cpu
  1367. * @dev: valid struct device pointer
  1368. * @sg: list of buffers
  1369. * @nents: number of buffers to map (returned from dma_map_sg)
  1370. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1371. */
  1372. void arm_iommu_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
  1373. int nents, enum dma_data_direction dir)
  1374. {
  1375. struct scatterlist *s;
  1376. int i;
  1377. for_each_sg(sg, s, nents, i)
  1378. __dma_page_dev_to_cpu(sg_page(s), s->offset, s->length, dir);
  1379. }
  1380. /**
  1381. * arm_iommu_sync_sg_for_device
  1382. * @dev: valid struct device pointer
  1383. * @sg: list of buffers
  1384. * @nents: number of buffers to map (returned from dma_map_sg)
  1385. * @dir: DMA transfer direction (same as was passed to dma_map_sg)
  1386. */
  1387. void arm_iommu_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
  1388. int nents, enum dma_data_direction dir)
  1389. {
  1390. struct scatterlist *s;
  1391. int i;
  1392. for_each_sg(sg, s, nents, i)
  1393. __dma_page_cpu_to_dev(sg_page(s), s->offset, s->length, dir);
  1394. }
  1395. /**
  1396. * arm_coherent_iommu_map_page
  1397. * @dev: valid struct device pointer
  1398. * @page: page that buffer resides in
  1399. * @offset: offset into page for start of buffer
  1400. * @size: size of buffer to map
  1401. * @dir: DMA transfer direction
  1402. *
  1403. * Coherent IOMMU aware version of arm_dma_map_page()
  1404. */
  1405. static dma_addr_t arm_coherent_iommu_map_page(struct device *dev, struct page *page,
  1406. unsigned long offset, size_t size, enum dma_data_direction dir,
  1407. struct dma_attrs *attrs)
  1408. {
  1409. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1410. dma_addr_t dma_addr;
  1411. int ret, prot, len = PAGE_ALIGN(size + offset);
  1412. dma_addr = __alloc_iova(mapping, len);
  1413. if (dma_addr == DMA_ERROR_CODE)
  1414. return dma_addr;
  1415. switch (dir) {
  1416. case DMA_BIDIRECTIONAL:
  1417. prot = IOMMU_READ | IOMMU_WRITE;
  1418. break;
  1419. case DMA_TO_DEVICE:
  1420. prot = IOMMU_READ;
  1421. break;
  1422. case DMA_FROM_DEVICE:
  1423. prot = IOMMU_WRITE;
  1424. break;
  1425. default:
  1426. prot = 0;
  1427. }
  1428. ret = iommu_map(mapping->domain, dma_addr, page_to_phys(page), len, prot);
  1429. if (ret < 0)
  1430. goto fail;
  1431. return dma_addr + offset;
  1432. fail:
  1433. __free_iova(mapping, dma_addr, len);
  1434. return DMA_ERROR_CODE;
  1435. }
  1436. /**
  1437. * arm_iommu_map_page
  1438. * @dev: valid struct device pointer
  1439. * @page: page that buffer resides in
  1440. * @offset: offset into page for start of buffer
  1441. * @size: size of buffer to map
  1442. * @dir: DMA transfer direction
  1443. *
  1444. * IOMMU aware version of arm_dma_map_page()
  1445. */
  1446. static dma_addr_t arm_iommu_map_page(struct device *dev, struct page *page,
  1447. unsigned long offset, size_t size, enum dma_data_direction dir,
  1448. struct dma_attrs *attrs)
  1449. {
  1450. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1451. __dma_page_cpu_to_dev(page, offset, size, dir);
  1452. return arm_coherent_iommu_map_page(dev, page, offset, size, dir, attrs);
  1453. }
  1454. /**
  1455. * arm_coherent_iommu_unmap_page
  1456. * @dev: valid struct device pointer
  1457. * @handle: DMA address of buffer
  1458. * @size: size of buffer (same as passed to dma_map_page)
  1459. * @dir: DMA transfer direction (same as passed to dma_map_page)
  1460. *
  1461. * Coherent IOMMU aware version of arm_dma_unmap_page()
  1462. */
  1463. static void arm_coherent_iommu_unmap_page(struct device *dev, dma_addr_t handle,
  1464. size_t size, enum dma_data_direction dir,
  1465. struct dma_attrs *attrs)
  1466. {
  1467. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1468. dma_addr_t iova = handle & PAGE_MASK;
  1469. int offset = handle & ~PAGE_MASK;
  1470. int len = PAGE_ALIGN(size + offset);
  1471. if (!iova)
  1472. return;
  1473. iommu_unmap(mapping->domain, iova, len);
  1474. __free_iova(mapping, iova, len);
  1475. }
  1476. /**
  1477. * arm_iommu_unmap_page
  1478. * @dev: valid struct device pointer
  1479. * @handle: DMA address of buffer
  1480. * @size: size of buffer (same as passed to dma_map_page)
  1481. * @dir: DMA transfer direction (same as passed to dma_map_page)
  1482. *
  1483. * IOMMU aware version of arm_dma_unmap_page()
  1484. */
  1485. static void arm_iommu_unmap_page(struct device *dev, dma_addr_t handle,
  1486. size_t size, enum dma_data_direction dir,
  1487. struct dma_attrs *attrs)
  1488. {
  1489. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1490. dma_addr_t iova = handle & PAGE_MASK;
  1491. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1492. int offset = handle & ~PAGE_MASK;
  1493. int len = PAGE_ALIGN(size + offset);
  1494. if (!iova)
  1495. return;
  1496. if (!dma_get_attr(DMA_ATTR_SKIP_CPU_SYNC, attrs))
  1497. __dma_page_dev_to_cpu(page, offset, size, dir);
  1498. iommu_unmap(mapping->domain, iova, len);
  1499. __free_iova(mapping, iova, len);
  1500. }
  1501. static void arm_iommu_sync_single_for_cpu(struct device *dev,
  1502. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  1503. {
  1504. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1505. dma_addr_t iova = handle & PAGE_MASK;
  1506. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1507. unsigned int offset = handle & ~PAGE_MASK;
  1508. if (!iova)
  1509. return;
  1510. __dma_page_dev_to_cpu(page, offset, size, dir);
  1511. }
  1512. static void arm_iommu_sync_single_for_device(struct device *dev,
  1513. dma_addr_t handle, size_t size, enum dma_data_direction dir)
  1514. {
  1515. struct dma_iommu_mapping *mapping = dev->archdata.mapping;
  1516. dma_addr_t iova = handle & PAGE_MASK;
  1517. struct page *page = phys_to_page(iommu_iova_to_phys(mapping->domain, iova));
  1518. unsigned int offset = handle & ~PAGE_MASK;
  1519. if (!iova)
  1520. return;
  1521. __dma_page_cpu_to_dev(page, offset, size, dir);
  1522. }
  1523. struct dma_map_ops iommu_ops = {
  1524. .alloc = arm_iommu_alloc_attrs,
  1525. .free = arm_iommu_free_attrs,
  1526. .mmap = arm_iommu_mmap_attrs,
  1527. .get_sgtable = arm_iommu_get_sgtable,
  1528. .map_page = arm_iommu_map_page,
  1529. .unmap_page = arm_iommu_unmap_page,
  1530. .sync_single_for_cpu = arm_iommu_sync_single_for_cpu,
  1531. .sync_single_for_device = arm_iommu_sync_single_for_device,
  1532. .map_sg = arm_iommu_map_sg,
  1533. .unmap_sg = arm_iommu_unmap_sg,
  1534. .sync_sg_for_cpu = arm_iommu_sync_sg_for_cpu,
  1535. .sync_sg_for_device = arm_iommu_sync_sg_for_device,
  1536. .set_dma_mask = arm_dma_set_mask,
  1537. };
  1538. struct dma_map_ops iommu_coherent_ops = {
  1539. .alloc = arm_iommu_alloc_attrs,
  1540. .free = arm_iommu_free_attrs,
  1541. .mmap = arm_iommu_mmap_attrs,
  1542. .get_sgtable = arm_iommu_get_sgtable,
  1543. .map_page = arm_coherent_iommu_map_page,
  1544. .unmap_page = arm_coherent_iommu_unmap_page,
  1545. .map_sg = arm_coherent_iommu_map_sg,
  1546. .unmap_sg = arm_coherent_iommu_unmap_sg,
  1547. .set_dma_mask = arm_dma_set_mask,
  1548. };
  1549. /**
  1550. * arm_iommu_create_mapping
  1551. * @bus: pointer to the bus holding the client device (for IOMMU calls)
  1552. * @base: start address of the valid IO address space
  1553. * @size: size of the valid IO address space
  1554. * @order: accuracy of the IO addresses allocations
  1555. *
  1556. * Creates a mapping structure which holds information about used/unused
  1557. * IO address ranges, which is required to perform memory allocation and
  1558. * mapping with IOMMU aware functions.
  1559. *
  1560. * The client device need to be attached to the mapping with
  1561. * arm_iommu_attach_device function.
  1562. */
  1563. struct dma_iommu_mapping *
  1564. arm_iommu_create_mapping(struct bus_type *bus, dma_addr_t base, size_t size,
  1565. int order)
  1566. {
  1567. unsigned int count = size >> (PAGE_SHIFT + order);
  1568. unsigned int bitmap_size = BITS_TO_LONGS(count) * sizeof(long);
  1569. struct dma_iommu_mapping *mapping;
  1570. int err = -ENOMEM;
  1571. if (!count)
  1572. return ERR_PTR(-EINVAL);
  1573. mapping = kzalloc(sizeof(struct dma_iommu_mapping), GFP_KERNEL);
  1574. if (!mapping)
  1575. goto err;
  1576. mapping->bitmap = kzalloc(bitmap_size, GFP_KERNEL);
  1577. if (!mapping->bitmap)
  1578. goto err2;
  1579. mapping->base = base;
  1580. mapping->bits = BITS_PER_BYTE * bitmap_size;
  1581. mapping->order = order;
  1582. spin_lock_init(&mapping->lock);
  1583. mapping->domain = iommu_domain_alloc(bus);
  1584. if (!mapping->domain)
  1585. goto err3;
  1586. kref_init(&mapping->kref);
  1587. return mapping;
  1588. err3:
  1589. kfree(mapping->bitmap);
  1590. err2:
  1591. kfree(mapping);
  1592. err:
  1593. return ERR_PTR(err);
  1594. }
  1595. EXPORT_SYMBOL_GPL(arm_iommu_create_mapping);
  1596. static void release_iommu_mapping(struct kref *kref)
  1597. {
  1598. struct dma_iommu_mapping *mapping =
  1599. container_of(kref, struct dma_iommu_mapping, kref);
  1600. iommu_domain_free(mapping->domain);
  1601. kfree(mapping->bitmap);
  1602. kfree(mapping);
  1603. }
  1604. void arm_iommu_release_mapping(struct dma_iommu_mapping *mapping)
  1605. {
  1606. if (mapping)
  1607. kref_put(&mapping->kref, release_iommu_mapping);
  1608. }
  1609. EXPORT_SYMBOL_GPL(arm_iommu_release_mapping);
  1610. /**
  1611. * arm_iommu_attach_device
  1612. * @dev: valid struct device pointer
  1613. * @mapping: io address space mapping structure (returned from
  1614. * arm_iommu_create_mapping)
  1615. *
  1616. * Attaches specified io address space mapping to the provided device,
  1617. * this replaces the dma operations (dma_map_ops pointer) with the
  1618. * IOMMU aware version. More than one client might be attached to
  1619. * the same io address space mapping.
  1620. */
  1621. int arm_iommu_attach_device(struct device *dev,
  1622. struct dma_iommu_mapping *mapping)
  1623. {
  1624. int err;
  1625. err = iommu_attach_device(mapping->domain, dev);
  1626. if (err)
  1627. return err;
  1628. kref_get(&mapping->kref);
  1629. dev->archdata.mapping = mapping;
  1630. set_dma_ops(dev, &iommu_ops);
  1631. pr_debug("Attached IOMMU controller to %s device.\n", dev_name(dev));
  1632. return 0;
  1633. }
  1634. EXPORT_SYMBOL_GPL(arm_iommu_attach_device);
  1635. /**
  1636. * arm_iommu_detach_device
  1637. * @dev: valid struct device pointer
  1638. *
  1639. * Detaches the provided device from a previously attached map.
  1640. * This voids the dma operations (dma_map_ops pointer)
  1641. */
  1642. void arm_iommu_detach_device(struct device *dev)
  1643. {
  1644. struct dma_iommu_mapping *mapping;
  1645. mapping = to_dma_iommu_mapping(dev);
  1646. if (!mapping) {
  1647. dev_warn(dev, "Not attached\n");
  1648. return;
  1649. }
  1650. iommu_detach_device(mapping->domain, dev);
  1651. kref_put(&mapping->kref, release_iommu_mapping);
  1652. dev->archdata.mapping = NULL;
  1653. set_dma_ops(dev, NULL);
  1654. pr_debug("Detached IOMMU controller from %s device.\n", dev_name(dev));
  1655. }
  1656. EXPORT_SYMBOL_GPL(arm_iommu_detach_device);
  1657. #endif