cache-l2x0.c 25 KB

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  1. /*
  2. * arch/arm/mm/cache-l2x0.c - L210/L220 cache controller support
  3. *
  4. * Copyright (C) 2007 ARM Limited
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. *
  15. * You should have received a copy of the GNU General Public License
  16. * along with this program; if not, write to the Free Software
  17. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  18. */
  19. #include <linux/err.h>
  20. #include <linux/init.h>
  21. #include <linux/spinlock.h>
  22. #include <linux/io.h>
  23. #include <linux/of.h>
  24. #include <linux/of_address.h>
  25. #include <asm/cacheflush.h>
  26. #include <asm/hardware/cache-l2x0.h>
  27. #include "cache-aurora-l2.h"
  28. #define CACHE_LINE_SIZE 32
  29. static void __iomem *l2x0_base;
  30. static DEFINE_RAW_SPINLOCK(l2x0_lock);
  31. static u32 l2x0_way_mask; /* Bitmask of active ways */
  32. static u32 l2x0_size;
  33. static unsigned long sync_reg_offset = L2X0_CACHE_SYNC;
  34. /* Aurora don't have the cache ID register available, so we have to
  35. * pass it though the device tree */
  36. static u32 cache_id_part_number_from_dt;
  37. struct l2x0_regs l2x0_saved_regs;
  38. struct l2x0_of_data {
  39. void (*setup)(const struct device_node *, u32 *, u32 *);
  40. void (*save)(void);
  41. struct outer_cache_fns outer_cache;
  42. };
  43. static bool of_init = false;
  44. static inline void cache_wait_way(void __iomem *reg, unsigned long mask)
  45. {
  46. /* wait for cache operation by line or way to complete */
  47. while (readl_relaxed(reg) & mask)
  48. cpu_relax();
  49. }
  50. #ifdef CONFIG_CACHE_PL310
  51. static inline void cache_wait(void __iomem *reg, unsigned long mask)
  52. {
  53. /* cache operations by line are atomic on PL310 */
  54. }
  55. #else
  56. #define cache_wait cache_wait_way
  57. #endif
  58. static inline void cache_sync(void)
  59. {
  60. void __iomem *base = l2x0_base;
  61. writel_relaxed(0, base + sync_reg_offset);
  62. cache_wait(base + L2X0_CACHE_SYNC, 1);
  63. }
  64. static inline void l2x0_clean_line(unsigned long addr)
  65. {
  66. void __iomem *base = l2x0_base;
  67. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  68. writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
  69. }
  70. static inline void l2x0_inv_line(unsigned long addr)
  71. {
  72. void __iomem *base = l2x0_base;
  73. cache_wait(base + L2X0_INV_LINE_PA, 1);
  74. writel_relaxed(addr, base + L2X0_INV_LINE_PA);
  75. }
  76. #if defined(CONFIG_PL310_ERRATA_588369) || defined(CONFIG_PL310_ERRATA_727915)
  77. static inline void debug_writel(unsigned long val)
  78. {
  79. if (outer_cache.set_debug)
  80. outer_cache.set_debug(val);
  81. }
  82. static void pl310_set_debug(unsigned long val)
  83. {
  84. writel_relaxed(val, l2x0_base + L2X0_DEBUG_CTRL);
  85. }
  86. #else
  87. /* Optimised out for non-errata case */
  88. static inline void debug_writel(unsigned long val)
  89. {
  90. }
  91. #define pl310_set_debug NULL
  92. #endif
  93. #ifdef CONFIG_PL310_ERRATA_588369
  94. static inline void l2x0_flush_line(unsigned long addr)
  95. {
  96. void __iomem *base = l2x0_base;
  97. /* Clean by PA followed by Invalidate by PA */
  98. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  99. writel_relaxed(addr, base + L2X0_CLEAN_LINE_PA);
  100. cache_wait(base + L2X0_INV_LINE_PA, 1);
  101. writel_relaxed(addr, base + L2X0_INV_LINE_PA);
  102. }
  103. #else
  104. static inline void l2x0_flush_line(unsigned long addr)
  105. {
  106. void __iomem *base = l2x0_base;
  107. cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
  108. writel_relaxed(addr, base + L2X0_CLEAN_INV_LINE_PA);
  109. }
  110. #endif
  111. static void l2x0_cache_sync(void)
  112. {
  113. unsigned long flags;
  114. raw_spin_lock_irqsave(&l2x0_lock, flags);
  115. cache_sync();
  116. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  117. }
  118. static void __l2x0_flush_all(void)
  119. {
  120. debug_writel(0x03);
  121. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_INV_WAY);
  122. cache_wait_way(l2x0_base + L2X0_CLEAN_INV_WAY, l2x0_way_mask);
  123. cache_sync();
  124. debug_writel(0x00);
  125. }
  126. static void l2x0_flush_all(void)
  127. {
  128. unsigned long flags;
  129. /* clean all ways */
  130. raw_spin_lock_irqsave(&l2x0_lock, flags);
  131. __l2x0_flush_all();
  132. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  133. }
  134. static void l2x0_clean_all(void)
  135. {
  136. unsigned long flags;
  137. /* clean all ways */
  138. raw_spin_lock_irqsave(&l2x0_lock, flags);
  139. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_CLEAN_WAY);
  140. cache_wait_way(l2x0_base + L2X0_CLEAN_WAY, l2x0_way_mask);
  141. cache_sync();
  142. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  143. }
  144. static void l2x0_inv_all(void)
  145. {
  146. unsigned long flags;
  147. /* invalidate all ways */
  148. raw_spin_lock_irqsave(&l2x0_lock, flags);
  149. /* Invalidating when L2 is enabled is a nono */
  150. BUG_ON(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN);
  151. writel_relaxed(l2x0_way_mask, l2x0_base + L2X0_INV_WAY);
  152. cache_wait_way(l2x0_base + L2X0_INV_WAY, l2x0_way_mask);
  153. cache_sync();
  154. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  155. }
  156. static void l2x0_inv_range(unsigned long start, unsigned long end)
  157. {
  158. void __iomem *base = l2x0_base;
  159. unsigned long flags;
  160. raw_spin_lock_irqsave(&l2x0_lock, flags);
  161. if (start & (CACHE_LINE_SIZE - 1)) {
  162. start &= ~(CACHE_LINE_SIZE - 1);
  163. debug_writel(0x03);
  164. l2x0_flush_line(start);
  165. debug_writel(0x00);
  166. start += CACHE_LINE_SIZE;
  167. }
  168. if (end & (CACHE_LINE_SIZE - 1)) {
  169. end &= ~(CACHE_LINE_SIZE - 1);
  170. debug_writel(0x03);
  171. l2x0_flush_line(end);
  172. debug_writel(0x00);
  173. }
  174. while (start < end) {
  175. unsigned long blk_end = start + min(end - start, 4096UL);
  176. while (start < blk_end) {
  177. l2x0_inv_line(start);
  178. start += CACHE_LINE_SIZE;
  179. }
  180. if (blk_end < end) {
  181. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  182. raw_spin_lock_irqsave(&l2x0_lock, flags);
  183. }
  184. }
  185. cache_wait(base + L2X0_INV_LINE_PA, 1);
  186. cache_sync();
  187. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  188. }
  189. static void l2x0_clean_range(unsigned long start, unsigned long end)
  190. {
  191. void __iomem *base = l2x0_base;
  192. unsigned long flags;
  193. if ((end - start) >= l2x0_size) {
  194. l2x0_clean_all();
  195. return;
  196. }
  197. raw_spin_lock_irqsave(&l2x0_lock, flags);
  198. start &= ~(CACHE_LINE_SIZE - 1);
  199. while (start < end) {
  200. unsigned long blk_end = start + min(end - start, 4096UL);
  201. while (start < blk_end) {
  202. l2x0_clean_line(start);
  203. start += CACHE_LINE_SIZE;
  204. }
  205. if (blk_end < end) {
  206. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  207. raw_spin_lock_irqsave(&l2x0_lock, flags);
  208. }
  209. }
  210. cache_wait(base + L2X0_CLEAN_LINE_PA, 1);
  211. cache_sync();
  212. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  213. }
  214. static void l2x0_flush_range(unsigned long start, unsigned long end)
  215. {
  216. void __iomem *base = l2x0_base;
  217. unsigned long flags;
  218. if ((end - start) >= l2x0_size) {
  219. l2x0_flush_all();
  220. return;
  221. }
  222. raw_spin_lock_irqsave(&l2x0_lock, flags);
  223. start &= ~(CACHE_LINE_SIZE - 1);
  224. while (start < end) {
  225. unsigned long blk_end = start + min(end - start, 4096UL);
  226. debug_writel(0x03);
  227. while (start < blk_end) {
  228. l2x0_flush_line(start);
  229. start += CACHE_LINE_SIZE;
  230. }
  231. debug_writel(0x00);
  232. if (blk_end < end) {
  233. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  234. raw_spin_lock_irqsave(&l2x0_lock, flags);
  235. }
  236. }
  237. cache_wait(base + L2X0_CLEAN_INV_LINE_PA, 1);
  238. cache_sync();
  239. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  240. }
  241. static void l2x0_disable(void)
  242. {
  243. unsigned long flags;
  244. raw_spin_lock_irqsave(&l2x0_lock, flags);
  245. __l2x0_flush_all();
  246. writel_relaxed(0, l2x0_base + L2X0_CTRL);
  247. dsb();
  248. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  249. }
  250. static void l2x0_unlock(u32 cache_id)
  251. {
  252. int lockregs;
  253. int i;
  254. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  255. case L2X0_CACHE_ID_PART_L310:
  256. lockregs = 8;
  257. break;
  258. case AURORA_CACHE_ID:
  259. lockregs = 4;
  260. break;
  261. default:
  262. /* L210 and unknown types */
  263. lockregs = 1;
  264. break;
  265. }
  266. for (i = 0; i < lockregs; i++) {
  267. writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_D_BASE +
  268. i * L2X0_LOCKDOWN_STRIDE);
  269. writel_relaxed(0x0, l2x0_base + L2X0_LOCKDOWN_WAY_I_BASE +
  270. i * L2X0_LOCKDOWN_STRIDE);
  271. }
  272. }
  273. void __init l2x0_init(void __iomem *base, u32 aux_val, u32 aux_mask)
  274. {
  275. u32 aux;
  276. u32 cache_id;
  277. u32 way_size = 0;
  278. int ways;
  279. int way_size_shift = L2X0_WAY_SIZE_SHIFT;
  280. const char *type;
  281. l2x0_base = base;
  282. if (cache_id_part_number_from_dt)
  283. cache_id = cache_id_part_number_from_dt;
  284. else
  285. cache_id = readl_relaxed(l2x0_base + L2X0_CACHE_ID);
  286. aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  287. aux &= aux_mask;
  288. aux |= aux_val;
  289. /* Determine the number of ways */
  290. switch (cache_id & L2X0_CACHE_ID_PART_MASK) {
  291. case L2X0_CACHE_ID_PART_L310:
  292. if (aux & (1 << 16))
  293. ways = 16;
  294. else
  295. ways = 8;
  296. type = "L310";
  297. #ifdef CONFIG_PL310_ERRATA_753970
  298. /* Unmapped register. */
  299. sync_reg_offset = L2X0_DUMMY_REG;
  300. #endif
  301. if ((cache_id & L2X0_CACHE_ID_RTL_MASK) <= L2X0_CACHE_ID_RTL_R3P0)
  302. outer_cache.set_debug = pl310_set_debug;
  303. break;
  304. case L2X0_CACHE_ID_PART_L210:
  305. ways = (aux >> 13) & 0xf;
  306. type = "L210";
  307. break;
  308. case AURORA_CACHE_ID:
  309. sync_reg_offset = AURORA_SYNC_REG;
  310. ways = (aux >> 13) & 0xf;
  311. ways = 2 << ((ways + 1) >> 2);
  312. way_size_shift = AURORA_WAY_SIZE_SHIFT;
  313. type = "Aurora";
  314. break;
  315. default:
  316. /* Assume unknown chips have 8 ways */
  317. ways = 8;
  318. type = "L2x0 series";
  319. break;
  320. }
  321. l2x0_way_mask = (1 << ways) - 1;
  322. /*
  323. * L2 cache Size = Way size * Number of ways
  324. */
  325. way_size = (aux & L2X0_AUX_CTRL_WAY_SIZE_MASK) >> 17;
  326. way_size = 1 << (way_size + way_size_shift);
  327. l2x0_size = ways * way_size * SZ_1K;
  328. /*
  329. * Check if l2x0 controller is already enabled.
  330. * If you are booting from non-secure mode
  331. * accessing the below registers will fault.
  332. */
  333. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  334. /* Make sure that I&D is not locked down when starting */
  335. l2x0_unlock(cache_id);
  336. /* l2x0 controller is disabled */
  337. writel_relaxed(aux, l2x0_base + L2X0_AUX_CTRL);
  338. l2x0_inv_all();
  339. /* enable L2X0 */
  340. writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
  341. }
  342. /* Re-read it in case some bits are reserved. */
  343. aux = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  344. /* Save the value for resuming. */
  345. l2x0_saved_regs.aux_ctrl = aux;
  346. if (!of_init) {
  347. outer_cache.inv_range = l2x0_inv_range;
  348. outer_cache.clean_range = l2x0_clean_range;
  349. outer_cache.flush_range = l2x0_flush_range;
  350. outer_cache.sync = l2x0_cache_sync;
  351. outer_cache.flush_all = l2x0_flush_all;
  352. outer_cache.inv_all = l2x0_inv_all;
  353. outer_cache.disable = l2x0_disable;
  354. }
  355. printk(KERN_INFO "%s cache controller enabled\n", type);
  356. printk(KERN_INFO "l2x0: %d ways, CACHE_ID 0x%08x, AUX_CTRL 0x%08x, Cache size: %d B\n",
  357. ways, cache_id, aux, l2x0_size);
  358. }
  359. #ifdef CONFIG_OF
  360. static int l2_wt_override;
  361. /*
  362. * Note that the end addresses passed to Linux primitives are
  363. * noninclusive, while the hardware cache range operations use
  364. * inclusive start and end addresses.
  365. */
  366. static unsigned long calc_range_end(unsigned long start, unsigned long end)
  367. {
  368. /*
  369. * Limit the number of cache lines processed at once,
  370. * since cache range operations stall the CPU pipeline
  371. * until completion.
  372. */
  373. if (end > start + MAX_RANGE_SIZE)
  374. end = start + MAX_RANGE_SIZE;
  375. /*
  376. * Cache range operations can't straddle a page boundary.
  377. */
  378. if (end > PAGE_ALIGN(start+1))
  379. end = PAGE_ALIGN(start+1);
  380. return end;
  381. }
  382. /*
  383. * Make sure 'start' and 'end' reference the same page, as L2 is PIPT
  384. * and range operations only do a TLB lookup on the start address.
  385. */
  386. static void aurora_pa_range(unsigned long start, unsigned long end,
  387. unsigned long offset)
  388. {
  389. unsigned long flags;
  390. raw_spin_lock_irqsave(&l2x0_lock, flags);
  391. writel_relaxed(start, l2x0_base + AURORA_RANGE_BASE_ADDR_REG);
  392. writel_relaxed(end, l2x0_base + offset);
  393. raw_spin_unlock_irqrestore(&l2x0_lock, flags);
  394. cache_sync();
  395. }
  396. static void aurora_inv_range(unsigned long start, unsigned long end)
  397. {
  398. /*
  399. * round start and end adresses up to cache line size
  400. */
  401. start &= ~(CACHE_LINE_SIZE - 1);
  402. end = ALIGN(end, CACHE_LINE_SIZE);
  403. /*
  404. * Invalidate all full cache lines between 'start' and 'end'.
  405. */
  406. while (start < end) {
  407. unsigned long range_end = calc_range_end(start, end);
  408. aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  409. AURORA_INVAL_RANGE_REG);
  410. start = range_end;
  411. }
  412. }
  413. static void aurora_clean_range(unsigned long start, unsigned long end)
  414. {
  415. /*
  416. * If L2 is forced to WT, the L2 will always be clean and we
  417. * don't need to do anything here.
  418. */
  419. if (!l2_wt_override) {
  420. start &= ~(CACHE_LINE_SIZE - 1);
  421. end = ALIGN(end, CACHE_LINE_SIZE);
  422. while (start != end) {
  423. unsigned long range_end = calc_range_end(start, end);
  424. aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  425. AURORA_CLEAN_RANGE_REG);
  426. start = range_end;
  427. }
  428. }
  429. }
  430. static void aurora_flush_range(unsigned long start, unsigned long end)
  431. {
  432. start &= ~(CACHE_LINE_SIZE - 1);
  433. end = ALIGN(end, CACHE_LINE_SIZE);
  434. while (start != end) {
  435. unsigned long range_end = calc_range_end(start, end);
  436. /*
  437. * If L2 is forced to WT, the L2 will always be clean and we
  438. * just need to invalidate.
  439. */
  440. if (l2_wt_override)
  441. aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  442. AURORA_INVAL_RANGE_REG);
  443. else
  444. aurora_pa_range(start, range_end - CACHE_LINE_SIZE,
  445. AURORA_FLUSH_RANGE_REG);
  446. start = range_end;
  447. }
  448. }
  449. /*
  450. * For certain Broadcom SoCs, depending on the address range, different offsets
  451. * need to be added to the address before passing it to L2 for
  452. * invalidation/clean/flush
  453. *
  454. * Section Address Range Offset EMI
  455. * 1 0x00000000 - 0x3FFFFFFF 0x80000000 VC
  456. * 2 0x40000000 - 0xBFFFFFFF 0x40000000 SYS
  457. * 3 0xC0000000 - 0xFFFFFFFF 0x80000000 VC
  458. *
  459. * When the start and end addresses have crossed two different sections, we
  460. * need to break the L2 operation into two, each within its own section.
  461. * For example, if we need to invalidate addresses starts at 0xBFFF0000 and
  462. * ends at 0xC0001000, we need do invalidate 1) 0xBFFF0000 - 0xBFFFFFFF and 2)
  463. * 0xC0000000 - 0xC0001000
  464. *
  465. * Note 1:
  466. * By breaking a single L2 operation into two, we may potentially suffer some
  467. * performance hit, but keep in mind the cross section case is very rare
  468. *
  469. * Note 2:
  470. * We do not need to handle the case when the start address is in
  471. * Section 1 and the end address is in Section 3, since it is not a valid use
  472. * case
  473. *
  474. * Note 3:
  475. * Section 1 in practical terms can no longer be used on rev A2. Because of
  476. * that the code does not need to handle section 1 at all.
  477. *
  478. */
  479. #define BCM_SYS_EMI_START_ADDR 0x40000000UL
  480. #define BCM_VC_EMI_SEC3_START_ADDR 0xC0000000UL
  481. #define BCM_SYS_EMI_OFFSET 0x40000000UL
  482. #define BCM_VC_EMI_OFFSET 0x80000000UL
  483. static inline int bcm_addr_is_sys_emi(unsigned long addr)
  484. {
  485. return (addr >= BCM_SYS_EMI_START_ADDR) &&
  486. (addr < BCM_VC_EMI_SEC3_START_ADDR);
  487. }
  488. static inline unsigned long bcm_l2_phys_addr(unsigned long addr)
  489. {
  490. if (bcm_addr_is_sys_emi(addr))
  491. return addr + BCM_SYS_EMI_OFFSET;
  492. else
  493. return addr + BCM_VC_EMI_OFFSET;
  494. }
  495. static void bcm_inv_range(unsigned long start, unsigned long end)
  496. {
  497. unsigned long new_start, new_end;
  498. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  499. if (unlikely(end <= start))
  500. return;
  501. new_start = bcm_l2_phys_addr(start);
  502. new_end = bcm_l2_phys_addr(end);
  503. /* normal case, no cross section between start and end */
  504. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  505. l2x0_inv_range(new_start, new_end);
  506. return;
  507. }
  508. /* They cross sections, so it can only be a cross from section
  509. * 2 to section 3
  510. */
  511. l2x0_inv_range(new_start,
  512. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  513. l2x0_inv_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  514. new_end);
  515. }
  516. static void bcm_clean_range(unsigned long start, unsigned long end)
  517. {
  518. unsigned long new_start, new_end;
  519. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  520. if (unlikely(end <= start))
  521. return;
  522. if ((end - start) >= l2x0_size) {
  523. l2x0_clean_all();
  524. return;
  525. }
  526. new_start = bcm_l2_phys_addr(start);
  527. new_end = bcm_l2_phys_addr(end);
  528. /* normal case, no cross section between start and end */
  529. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  530. l2x0_clean_range(new_start, new_end);
  531. return;
  532. }
  533. /* They cross sections, so it can only be a cross from section
  534. * 2 to section 3
  535. */
  536. l2x0_clean_range(new_start,
  537. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  538. l2x0_clean_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  539. new_end);
  540. }
  541. static void bcm_flush_range(unsigned long start, unsigned long end)
  542. {
  543. unsigned long new_start, new_end;
  544. BUG_ON(start < BCM_SYS_EMI_START_ADDR);
  545. if (unlikely(end <= start))
  546. return;
  547. if ((end - start) >= l2x0_size) {
  548. l2x0_flush_all();
  549. return;
  550. }
  551. new_start = bcm_l2_phys_addr(start);
  552. new_end = bcm_l2_phys_addr(end);
  553. /* normal case, no cross section between start and end */
  554. if (likely(bcm_addr_is_sys_emi(end) || !bcm_addr_is_sys_emi(start))) {
  555. l2x0_flush_range(new_start, new_end);
  556. return;
  557. }
  558. /* They cross sections, so it can only be a cross from section
  559. * 2 to section 3
  560. */
  561. l2x0_flush_range(new_start,
  562. bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR-1));
  563. l2x0_flush_range(bcm_l2_phys_addr(BCM_VC_EMI_SEC3_START_ADDR),
  564. new_end);
  565. }
  566. static void __init l2x0_of_setup(const struct device_node *np,
  567. u32 *aux_val, u32 *aux_mask)
  568. {
  569. u32 data[2] = { 0, 0 };
  570. u32 tag = 0;
  571. u32 dirty = 0;
  572. u32 val = 0, mask = 0;
  573. of_property_read_u32(np, "arm,tag-latency", &tag);
  574. if (tag) {
  575. mask |= L2X0_AUX_CTRL_TAG_LATENCY_MASK;
  576. val |= (tag - 1) << L2X0_AUX_CTRL_TAG_LATENCY_SHIFT;
  577. }
  578. of_property_read_u32_array(np, "arm,data-latency",
  579. data, ARRAY_SIZE(data));
  580. if (data[0] && data[1]) {
  581. mask |= L2X0_AUX_CTRL_DATA_RD_LATENCY_MASK |
  582. L2X0_AUX_CTRL_DATA_WR_LATENCY_MASK;
  583. val |= ((data[0] - 1) << L2X0_AUX_CTRL_DATA_RD_LATENCY_SHIFT) |
  584. ((data[1] - 1) << L2X0_AUX_CTRL_DATA_WR_LATENCY_SHIFT);
  585. }
  586. of_property_read_u32(np, "arm,dirty-latency", &dirty);
  587. if (dirty) {
  588. mask |= L2X0_AUX_CTRL_DIRTY_LATENCY_MASK;
  589. val |= (dirty - 1) << L2X0_AUX_CTRL_DIRTY_LATENCY_SHIFT;
  590. }
  591. *aux_val &= ~mask;
  592. *aux_val |= val;
  593. *aux_mask &= ~mask;
  594. }
  595. static void __init pl310_of_setup(const struct device_node *np,
  596. u32 *aux_val, u32 *aux_mask)
  597. {
  598. u32 data[3] = { 0, 0, 0 };
  599. u32 tag[3] = { 0, 0, 0 };
  600. u32 filter[2] = { 0, 0 };
  601. of_property_read_u32_array(np, "arm,tag-latency", tag, ARRAY_SIZE(tag));
  602. if (tag[0] && tag[1] && tag[2])
  603. writel_relaxed(
  604. ((tag[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
  605. ((tag[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
  606. ((tag[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
  607. l2x0_base + L2X0_TAG_LATENCY_CTRL);
  608. of_property_read_u32_array(np, "arm,data-latency",
  609. data, ARRAY_SIZE(data));
  610. if (data[0] && data[1] && data[2])
  611. writel_relaxed(
  612. ((data[0] - 1) << L2X0_LATENCY_CTRL_RD_SHIFT) |
  613. ((data[1] - 1) << L2X0_LATENCY_CTRL_WR_SHIFT) |
  614. ((data[2] - 1) << L2X0_LATENCY_CTRL_SETUP_SHIFT),
  615. l2x0_base + L2X0_DATA_LATENCY_CTRL);
  616. of_property_read_u32_array(np, "arm,filter-ranges",
  617. filter, ARRAY_SIZE(filter));
  618. if (filter[1]) {
  619. writel_relaxed(ALIGN(filter[0] + filter[1], SZ_1M),
  620. l2x0_base + L2X0_ADDR_FILTER_END);
  621. writel_relaxed((filter[0] & ~(SZ_1M - 1)) | L2X0_ADDR_FILTER_EN,
  622. l2x0_base + L2X0_ADDR_FILTER_START);
  623. }
  624. }
  625. static void __init pl310_save(void)
  626. {
  627. u32 l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
  628. L2X0_CACHE_ID_RTL_MASK;
  629. l2x0_saved_regs.tag_latency = readl_relaxed(l2x0_base +
  630. L2X0_TAG_LATENCY_CTRL);
  631. l2x0_saved_regs.data_latency = readl_relaxed(l2x0_base +
  632. L2X0_DATA_LATENCY_CTRL);
  633. l2x0_saved_regs.filter_end = readl_relaxed(l2x0_base +
  634. L2X0_ADDR_FILTER_END);
  635. l2x0_saved_regs.filter_start = readl_relaxed(l2x0_base +
  636. L2X0_ADDR_FILTER_START);
  637. if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
  638. /*
  639. * From r2p0, there is Prefetch offset/control register
  640. */
  641. l2x0_saved_regs.prefetch_ctrl = readl_relaxed(l2x0_base +
  642. L2X0_PREFETCH_CTRL);
  643. /*
  644. * From r3p0, there is Power control register
  645. */
  646. if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
  647. l2x0_saved_regs.pwr_ctrl = readl_relaxed(l2x0_base +
  648. L2X0_POWER_CTRL);
  649. }
  650. }
  651. static void aurora_save(void)
  652. {
  653. l2x0_saved_regs.ctrl = readl_relaxed(l2x0_base + L2X0_CTRL);
  654. l2x0_saved_regs.aux_ctrl = readl_relaxed(l2x0_base + L2X0_AUX_CTRL);
  655. }
  656. static void l2x0_resume(void)
  657. {
  658. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  659. /* restore aux ctrl and enable l2 */
  660. l2x0_unlock(readl_relaxed(l2x0_base + L2X0_CACHE_ID));
  661. writel_relaxed(l2x0_saved_regs.aux_ctrl, l2x0_base +
  662. L2X0_AUX_CTRL);
  663. l2x0_inv_all();
  664. writel_relaxed(L2X0_CTRL_EN, l2x0_base + L2X0_CTRL);
  665. }
  666. }
  667. static void pl310_resume(void)
  668. {
  669. u32 l2x0_revision;
  670. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  671. /* restore pl310 setup */
  672. writel_relaxed(l2x0_saved_regs.tag_latency,
  673. l2x0_base + L2X0_TAG_LATENCY_CTRL);
  674. writel_relaxed(l2x0_saved_regs.data_latency,
  675. l2x0_base + L2X0_DATA_LATENCY_CTRL);
  676. writel_relaxed(l2x0_saved_regs.filter_end,
  677. l2x0_base + L2X0_ADDR_FILTER_END);
  678. writel_relaxed(l2x0_saved_regs.filter_start,
  679. l2x0_base + L2X0_ADDR_FILTER_START);
  680. l2x0_revision = readl_relaxed(l2x0_base + L2X0_CACHE_ID) &
  681. L2X0_CACHE_ID_RTL_MASK;
  682. if (l2x0_revision >= L2X0_CACHE_ID_RTL_R2P0) {
  683. writel_relaxed(l2x0_saved_regs.prefetch_ctrl,
  684. l2x0_base + L2X0_PREFETCH_CTRL);
  685. if (l2x0_revision >= L2X0_CACHE_ID_RTL_R3P0)
  686. writel_relaxed(l2x0_saved_regs.pwr_ctrl,
  687. l2x0_base + L2X0_POWER_CTRL);
  688. }
  689. }
  690. l2x0_resume();
  691. }
  692. static void aurora_resume(void)
  693. {
  694. if (!(readl(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  695. writel_relaxed(l2x0_saved_regs.aux_ctrl,
  696. l2x0_base + L2X0_AUX_CTRL);
  697. writel_relaxed(l2x0_saved_regs.ctrl, l2x0_base + L2X0_CTRL);
  698. }
  699. }
  700. static void __init aurora_broadcast_l2_commands(void)
  701. {
  702. __u32 u;
  703. /* Enable Broadcasting of cache commands to L2*/
  704. __asm__ __volatile__("mrc p15, 1, %0, c15, c2, 0" : "=r"(u));
  705. u |= AURORA_CTRL_FW; /* Set the FW bit */
  706. __asm__ __volatile__("mcr p15, 1, %0, c15, c2, 0\n" : : "r"(u));
  707. isb();
  708. }
  709. static void __init aurora_of_setup(const struct device_node *np,
  710. u32 *aux_val, u32 *aux_mask)
  711. {
  712. u32 val = AURORA_ACR_REPLACEMENT_TYPE_SEMIPLRU;
  713. u32 mask = AURORA_ACR_REPLACEMENT_MASK;
  714. of_property_read_u32(np, "cache-id-part",
  715. &cache_id_part_number_from_dt);
  716. /* Determine and save the write policy */
  717. l2_wt_override = of_property_read_bool(np, "wt-override");
  718. if (l2_wt_override) {
  719. val |= AURORA_ACR_FORCE_WRITE_THRO_POLICY;
  720. mask |= AURORA_ACR_FORCE_WRITE_POLICY_MASK;
  721. }
  722. *aux_val &= ~mask;
  723. *aux_val |= val;
  724. *aux_mask &= ~mask;
  725. }
  726. static const struct l2x0_of_data pl310_data = {
  727. .setup = pl310_of_setup,
  728. .save = pl310_save,
  729. .outer_cache = {
  730. .resume = pl310_resume,
  731. .inv_range = l2x0_inv_range,
  732. .clean_range = l2x0_clean_range,
  733. .flush_range = l2x0_flush_range,
  734. .sync = l2x0_cache_sync,
  735. .flush_all = l2x0_flush_all,
  736. .inv_all = l2x0_inv_all,
  737. .disable = l2x0_disable,
  738. },
  739. };
  740. static const struct l2x0_of_data l2x0_data = {
  741. .setup = l2x0_of_setup,
  742. .save = NULL,
  743. .outer_cache = {
  744. .resume = l2x0_resume,
  745. .inv_range = l2x0_inv_range,
  746. .clean_range = l2x0_clean_range,
  747. .flush_range = l2x0_flush_range,
  748. .sync = l2x0_cache_sync,
  749. .flush_all = l2x0_flush_all,
  750. .inv_all = l2x0_inv_all,
  751. .disable = l2x0_disable,
  752. },
  753. };
  754. static const struct l2x0_of_data aurora_with_outer_data = {
  755. .setup = aurora_of_setup,
  756. .save = aurora_save,
  757. .outer_cache = {
  758. .resume = aurora_resume,
  759. .inv_range = aurora_inv_range,
  760. .clean_range = aurora_clean_range,
  761. .flush_range = aurora_flush_range,
  762. .sync = l2x0_cache_sync,
  763. .flush_all = l2x0_flush_all,
  764. .inv_all = l2x0_inv_all,
  765. .disable = l2x0_disable,
  766. },
  767. };
  768. static const struct l2x0_of_data aurora_no_outer_data = {
  769. .setup = aurora_of_setup,
  770. .save = aurora_save,
  771. .outer_cache = {
  772. .resume = aurora_resume,
  773. },
  774. };
  775. static const struct l2x0_of_data bcm_l2x0_data = {
  776. .setup = pl310_of_setup,
  777. .save = pl310_save,
  778. .outer_cache = {
  779. .resume = pl310_resume,
  780. .inv_range = bcm_inv_range,
  781. .clean_range = bcm_clean_range,
  782. .flush_range = bcm_flush_range,
  783. .sync = l2x0_cache_sync,
  784. .flush_all = l2x0_flush_all,
  785. .inv_all = l2x0_inv_all,
  786. .disable = l2x0_disable,
  787. },
  788. };
  789. static const struct of_device_id l2x0_ids[] __initconst = {
  790. { .compatible = "arm,pl310-cache", .data = (void *)&pl310_data },
  791. { .compatible = "arm,l220-cache", .data = (void *)&l2x0_data },
  792. { .compatible = "arm,l210-cache", .data = (void *)&l2x0_data },
  793. { .compatible = "marvell,aurora-system-cache",
  794. .data = (void *)&aurora_no_outer_data},
  795. { .compatible = "marvell,aurora-outer-cache",
  796. .data = (void *)&aurora_with_outer_data},
  797. { .compatible = "bcm,bcm11351-a2-pl310-cache",
  798. .data = (void *)&bcm_l2x0_data},
  799. {}
  800. };
  801. int __init l2x0_of_init(u32 aux_val, u32 aux_mask)
  802. {
  803. struct device_node *np;
  804. const struct l2x0_of_data *data;
  805. struct resource res;
  806. np = of_find_matching_node(NULL, l2x0_ids);
  807. if (!np)
  808. return -ENODEV;
  809. if (of_address_to_resource(np, 0, &res))
  810. return -ENODEV;
  811. l2x0_base = ioremap(res.start, resource_size(&res));
  812. if (!l2x0_base)
  813. return -ENOMEM;
  814. l2x0_saved_regs.phy_base = res.start;
  815. data = of_match_node(l2x0_ids, np)->data;
  816. /* L2 configuration can only be changed if the cache is disabled */
  817. if (!(readl_relaxed(l2x0_base + L2X0_CTRL) & L2X0_CTRL_EN)) {
  818. if (data->setup)
  819. data->setup(np, &aux_val, &aux_mask);
  820. /* For aurora cache in no outer mode select the
  821. * correct mode using the coprocessor*/
  822. if (data == &aurora_no_outer_data)
  823. aurora_broadcast_l2_commands();
  824. }
  825. if (data->save)
  826. data->save();
  827. of_init = true;
  828. memcpy(&outer_cache, &data->outer_cache, sizeof(outer_cache));
  829. l2x0_init(l2x0_base, aux_val, aux_mask);
  830. return 0;
  831. }
  832. #endif