tegra114_speedo.c 2.4 KB

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  1. /*
  2. * Copyright (c) 2013, NVIDIA CORPORATION. All rights reserved.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License
  14. * along with this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/bug.h>
  18. #include "fuse.h"
  19. #define CORE_PROCESS_CORNERS_NUM 2
  20. #define CPU_PROCESS_CORNERS_NUM 2
  21. enum {
  22. THRESHOLD_INDEX_0,
  23. THRESHOLD_INDEX_1,
  24. THRESHOLD_INDEX_COUNT,
  25. };
  26. static const u32 core_process_speedos[][CORE_PROCESS_CORNERS_NUM] = {
  27. {1123, UINT_MAX},
  28. {0, UINT_MAX},
  29. };
  30. static const u32 cpu_process_speedos[][CPU_PROCESS_CORNERS_NUM] = {
  31. {1695, UINT_MAX},
  32. {0, UINT_MAX},
  33. };
  34. static void rev_sku_to_speedo_ids(int rev, int sku, int *threshold)
  35. {
  36. u32 tmp;
  37. switch (sku) {
  38. case 0x00:
  39. case 0x10:
  40. case 0x05:
  41. case 0x06:
  42. tegra_cpu_speedo_id = 1;
  43. tegra_soc_speedo_id = 0;
  44. *threshold = THRESHOLD_INDEX_0;
  45. break;
  46. case 0x03:
  47. case 0x04:
  48. tegra_cpu_speedo_id = 2;
  49. tegra_soc_speedo_id = 1;
  50. *threshold = THRESHOLD_INDEX_1;
  51. break;
  52. default:
  53. pr_err("Tegra114 Unknown SKU %d\n", sku);
  54. tegra_cpu_speedo_id = 0;
  55. tegra_soc_speedo_id = 0;
  56. *threshold = THRESHOLD_INDEX_0;
  57. break;
  58. }
  59. if (rev == TEGRA_REVISION_A01) {
  60. tmp = tegra_fuse_readl(0x270) << 1;
  61. tmp |= tegra_fuse_readl(0x26c);
  62. if (!tmp)
  63. tegra_cpu_speedo_id = 0;
  64. }
  65. }
  66. void tegra114_init_speedo_data(void)
  67. {
  68. u32 cpu_speedo_val;
  69. u32 core_speedo_val;
  70. int threshold;
  71. int i;
  72. BUILD_BUG_ON(ARRAY_SIZE(cpu_process_speedos) !=
  73. THRESHOLD_INDEX_COUNT);
  74. BUILD_BUG_ON(ARRAY_SIZE(core_process_speedos) !=
  75. THRESHOLD_INDEX_COUNT);
  76. rev_sku_to_speedo_ids(tegra_revision, tegra_sku_id, &threshold);
  77. cpu_speedo_val = tegra_fuse_readl(0x12c) + 1024;
  78. core_speedo_val = tegra_fuse_readl(0x134);
  79. for (i = 0; i < CPU_PROCESS_CORNERS_NUM; i++)
  80. if (cpu_speedo_val < cpu_process_speedos[threshold][i])
  81. break;
  82. tegra_cpu_process_id = i;
  83. for (i = 0; i < CORE_PROCESS_CORNERS_NUM; i++)
  84. if (core_speedo_val < core_process_speedos[threshold][i])
  85. break;
  86. tegra_core_process_id = i;
  87. }