common.c 2.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115
  1. /*
  2. * arch/arm/mach-tegra/common.c
  3. *
  4. * Copyright (c) 2013 NVIDIA Corporation. All rights reserved.
  5. * Copyright (C) 2010 Google, Inc.
  6. *
  7. * Author:
  8. * Colin Cross <ccross@android.com>
  9. *
  10. * This software is licensed under the terms of the GNU General Public
  11. * License version 2, as published by the Free Software Foundation, and
  12. * may be copied, distributed, and modified under those terms.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. */
  20. #include <linux/init.h>
  21. #include <linux/io.h>
  22. #include <linux/clk.h>
  23. #include <linux/delay.h>
  24. #include <linux/reboot.h>
  25. #include <linux/irqchip.h>
  26. #include <linux/clk-provider.h>
  27. #include <asm/hardware/cache-l2x0.h>
  28. #include "board.h"
  29. #include "common.h"
  30. #include "cpuidle.h"
  31. #include "fuse.h"
  32. #include "iomap.h"
  33. #include "irq.h"
  34. #include "pmc.h"
  35. #include "apbio.h"
  36. #include "sleep.h"
  37. #include "pm.h"
  38. #include "reset.h"
  39. /*
  40. * Storage for debug-macro.S's state.
  41. *
  42. * This must be in .data not .bss so that it gets initialized each time the
  43. * kernel is loaded. The data is declared here rather than debug-macro.S so
  44. * that multiple inclusions of debug-macro.S point at the same data.
  45. */
  46. u32 tegra_uart_config[4] = {
  47. /* Debug UART initialization required */
  48. 1,
  49. /* Debug UART physical address */
  50. 0,
  51. /* Debug UART virtual address */
  52. 0,
  53. /* Scratch space for debug macro */
  54. 0,
  55. };
  56. #ifdef CONFIG_OF
  57. void __init tegra_dt_init_irq(void)
  58. {
  59. of_clk_init(NULL);
  60. tegra_pmc_init();
  61. tegra_init_irq();
  62. irqchip_init();
  63. tegra_legacy_irq_syscore_init();
  64. }
  65. #endif
  66. void tegra_assert_system_reset(enum reboot_mode mode, const char *cmd)
  67. {
  68. void __iomem *reset = IO_ADDRESS(TEGRA_PMC_BASE + 0);
  69. u32 reg;
  70. reg = readl_relaxed(reset);
  71. reg |= 0x10;
  72. writel_relaxed(reg, reset);
  73. }
  74. static void __init tegra_init_cache(void)
  75. {
  76. #ifdef CONFIG_CACHE_L2X0
  77. int ret;
  78. void __iomem *p = IO_ADDRESS(TEGRA_ARM_PERIF_BASE) + 0x3000;
  79. u32 aux_ctrl, cache_type;
  80. cache_type = readl(p + L2X0_CACHE_TYPE);
  81. aux_ctrl = (cache_type & 0x700) << (17-8);
  82. aux_ctrl |= 0x7C400001;
  83. ret = l2x0_of_init(aux_ctrl, 0x8200c3fe);
  84. if (!ret)
  85. l2x0_saved_regs_addr = virt_to_phys(&l2x0_saved_regs);
  86. #endif
  87. }
  88. void __init tegra_init_early(void)
  89. {
  90. tegra_cpu_reset_handler_init();
  91. tegra_apb_io_init();
  92. tegra_init_fuse();
  93. tegra_init_cache();
  94. tegra_powergate_init();
  95. tegra_hotplug_init();
  96. }
  97. void __init tegra_init_late(void)
  98. {
  99. tegra_init_suspend();
  100. tegra_cpuidle_init();
  101. tegra_powergate_debugfs_init();
  102. }