generic.c 10 KB

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  1. /*
  2. * linux/arch/arm/mach-sa1100/generic.c
  3. *
  4. * Author: Nicolas Pitre
  5. *
  6. * Code common to all SA11x0 machines.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License version 2 as
  10. * published by the Free Software Foundation.
  11. */
  12. #include <linux/gpio.h>
  13. #include <linux/module.h>
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/delay.h>
  17. #include <linux/dma-mapping.h>
  18. #include <linux/pm.h>
  19. #include <linux/cpufreq.h>
  20. #include <linux/ioport.h>
  21. #include <linux/platform_device.h>
  22. #include <linux/reboot.h>
  23. #include <video/sa1100fb.h>
  24. #include <asm/div64.h>
  25. #include <asm/mach/map.h>
  26. #include <asm/mach/flash.h>
  27. #include <asm/irq.h>
  28. #include <asm/system_misc.h>
  29. #include <mach/hardware.h>
  30. #include <mach/irqs.h>
  31. #include "generic.h"
  32. unsigned int reset_status;
  33. EXPORT_SYMBOL(reset_status);
  34. #define NR_FREQS 16
  35. /*
  36. * This table is setup for a 3.6864MHz Crystal.
  37. */
  38. static const unsigned short cclk_frequency_100khz[NR_FREQS] = {
  39. 590, /* 59.0 MHz */
  40. 737, /* 73.7 MHz */
  41. 885, /* 88.5 MHz */
  42. 1032, /* 103.2 MHz */
  43. 1180, /* 118.0 MHz */
  44. 1327, /* 132.7 MHz */
  45. 1475, /* 147.5 MHz */
  46. 1622, /* 162.2 MHz */
  47. 1769, /* 176.9 MHz */
  48. 1917, /* 191.7 MHz */
  49. 2064, /* 206.4 MHz */
  50. 2212, /* 221.2 MHz */
  51. 2359, /* 235.9 MHz */
  52. 2507, /* 250.7 MHz */
  53. 2654, /* 265.4 MHz */
  54. 2802 /* 280.2 MHz */
  55. };
  56. /* rounds up(!) */
  57. unsigned int sa11x0_freq_to_ppcr(unsigned int khz)
  58. {
  59. int i;
  60. khz /= 100;
  61. for (i = 0; i < NR_FREQS; i++)
  62. if (cclk_frequency_100khz[i] >= khz)
  63. break;
  64. return i;
  65. }
  66. unsigned int sa11x0_ppcr_to_freq(unsigned int idx)
  67. {
  68. unsigned int freq = 0;
  69. if (idx < NR_FREQS)
  70. freq = cclk_frequency_100khz[idx] * 100;
  71. return freq;
  72. }
  73. /* make sure that only the "userspace" governor is run -- anything else wouldn't make sense on
  74. * this platform, anyway.
  75. */
  76. int sa11x0_verify_speed(struct cpufreq_policy *policy)
  77. {
  78. unsigned int tmp;
  79. if (policy->cpu)
  80. return -EINVAL;
  81. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  82. /* make sure that at least one frequency is within the policy */
  83. tmp = cclk_frequency_100khz[sa11x0_freq_to_ppcr(policy->min)] * 100;
  84. if (tmp > policy->max)
  85. policy->max = tmp;
  86. cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, policy->cpuinfo.max_freq);
  87. return 0;
  88. }
  89. unsigned int sa11x0_getspeed(unsigned int cpu)
  90. {
  91. if (cpu)
  92. return 0;
  93. return cclk_frequency_100khz[PPCR & 0xf] * 100;
  94. }
  95. /*
  96. * Default power-off for SA1100
  97. */
  98. static void sa1100_power_off(void)
  99. {
  100. mdelay(100);
  101. local_irq_disable();
  102. /* disable internal oscillator, float CS lines */
  103. PCFR = (PCFR_OPDE | PCFR_FP | PCFR_FS);
  104. /* enable wake-up on GPIO0 (Assabet...) */
  105. PWER = GFER = GRER = 1;
  106. /*
  107. * set scratchpad to zero, just in case it is used as a
  108. * restart address by the bootloader.
  109. */
  110. PSPR = 0;
  111. /* enter sleep mode */
  112. PMCR = PMCR_SF;
  113. }
  114. void sa11x0_restart(enum reboot_mode mode, const char *cmd)
  115. {
  116. if (mode == REBOOT_SOFT) {
  117. /* Jump into ROM at address 0 */
  118. soft_restart(0);
  119. } else {
  120. /* Use on-chip reset capability */
  121. RSRR = RSRR_SWR;
  122. }
  123. }
  124. static void sa11x0_register_device(struct platform_device *dev, void *data)
  125. {
  126. int err;
  127. dev->dev.platform_data = data;
  128. err = platform_device_register(dev);
  129. if (err)
  130. printk(KERN_ERR "Unable to register device %s: %d\n",
  131. dev->name, err);
  132. }
  133. static struct resource sa11x0udc_resources[] = {
  134. [0] = DEFINE_RES_MEM(__PREG(Ser0UDCCR), SZ_64K),
  135. [1] = DEFINE_RES_IRQ(IRQ_Ser0UDC),
  136. };
  137. static u64 sa11x0udc_dma_mask = 0xffffffffUL;
  138. static struct platform_device sa11x0udc_device = {
  139. .name = "sa11x0-udc",
  140. .id = -1,
  141. .dev = {
  142. .dma_mask = &sa11x0udc_dma_mask,
  143. .coherent_dma_mask = 0xffffffff,
  144. },
  145. .num_resources = ARRAY_SIZE(sa11x0udc_resources),
  146. .resource = sa11x0udc_resources,
  147. };
  148. static struct resource sa11x0uart1_resources[] = {
  149. [0] = DEFINE_RES_MEM(__PREG(Ser1UTCR0), SZ_64K),
  150. [1] = DEFINE_RES_IRQ(IRQ_Ser1UART),
  151. };
  152. static struct platform_device sa11x0uart1_device = {
  153. .name = "sa11x0-uart",
  154. .id = 1,
  155. .num_resources = ARRAY_SIZE(sa11x0uart1_resources),
  156. .resource = sa11x0uart1_resources,
  157. };
  158. static struct resource sa11x0uart3_resources[] = {
  159. [0] = DEFINE_RES_MEM(__PREG(Ser3UTCR0), SZ_64K),
  160. [1] = DEFINE_RES_IRQ(IRQ_Ser3UART),
  161. };
  162. static struct platform_device sa11x0uart3_device = {
  163. .name = "sa11x0-uart",
  164. .id = 3,
  165. .num_resources = ARRAY_SIZE(sa11x0uart3_resources),
  166. .resource = sa11x0uart3_resources,
  167. };
  168. static struct resource sa11x0mcp_resources[] = {
  169. [0] = DEFINE_RES_MEM(__PREG(Ser4MCCR0), SZ_64K),
  170. [1] = DEFINE_RES_MEM(__PREG(Ser4MCCR1), 4),
  171. [2] = DEFINE_RES_IRQ(IRQ_Ser4MCP),
  172. };
  173. static u64 sa11x0mcp_dma_mask = 0xffffffffUL;
  174. static struct platform_device sa11x0mcp_device = {
  175. .name = "sa11x0-mcp",
  176. .id = -1,
  177. .dev = {
  178. .dma_mask = &sa11x0mcp_dma_mask,
  179. .coherent_dma_mask = 0xffffffff,
  180. },
  181. .num_resources = ARRAY_SIZE(sa11x0mcp_resources),
  182. .resource = sa11x0mcp_resources,
  183. };
  184. void __init sa11x0_ppc_configure_mcp(void)
  185. {
  186. /* Setup the PPC unit for the MCP */
  187. PPDR &= ~PPC_RXD4;
  188. PPDR |= PPC_TXD4 | PPC_SCLK | PPC_SFRM;
  189. PSDR |= PPC_RXD4;
  190. PSDR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
  191. PPSR &= ~(PPC_TXD4 | PPC_SCLK | PPC_SFRM);
  192. }
  193. void sa11x0_register_mcp(struct mcp_plat_data *data)
  194. {
  195. sa11x0_register_device(&sa11x0mcp_device, data);
  196. }
  197. static struct resource sa11x0ssp_resources[] = {
  198. [0] = DEFINE_RES_MEM(0x80070000, SZ_64K),
  199. [1] = DEFINE_RES_IRQ(IRQ_Ser4SSP),
  200. };
  201. static u64 sa11x0ssp_dma_mask = 0xffffffffUL;
  202. static struct platform_device sa11x0ssp_device = {
  203. .name = "sa11x0-ssp",
  204. .id = -1,
  205. .dev = {
  206. .dma_mask = &sa11x0ssp_dma_mask,
  207. .coherent_dma_mask = 0xffffffff,
  208. },
  209. .num_resources = ARRAY_SIZE(sa11x0ssp_resources),
  210. .resource = sa11x0ssp_resources,
  211. };
  212. static struct resource sa11x0fb_resources[] = {
  213. [0] = DEFINE_RES_MEM(0xb0100000, SZ_64K),
  214. [1] = DEFINE_RES_IRQ(IRQ_LCD),
  215. };
  216. static struct platform_device sa11x0fb_device = {
  217. .name = "sa11x0-fb",
  218. .id = -1,
  219. .dev = {
  220. .coherent_dma_mask = 0xffffffff,
  221. },
  222. .num_resources = ARRAY_SIZE(sa11x0fb_resources),
  223. .resource = sa11x0fb_resources,
  224. };
  225. void sa11x0_register_lcd(struct sa1100fb_mach_info *inf)
  226. {
  227. sa11x0_register_device(&sa11x0fb_device, inf);
  228. }
  229. static struct platform_device sa11x0pcmcia_device = {
  230. .name = "sa11x0-pcmcia",
  231. .id = -1,
  232. };
  233. static struct platform_device sa11x0mtd_device = {
  234. .name = "sa1100-mtd",
  235. .id = -1,
  236. };
  237. void sa11x0_register_mtd(struct flash_platform_data *flash,
  238. struct resource *res, int nr)
  239. {
  240. flash->name = "sa1100";
  241. sa11x0mtd_device.resource = res;
  242. sa11x0mtd_device.num_resources = nr;
  243. sa11x0_register_device(&sa11x0mtd_device, flash);
  244. }
  245. static struct resource sa11x0ir_resources[] = {
  246. DEFINE_RES_MEM(__PREG(Ser2UTCR0), 0x24),
  247. DEFINE_RES_MEM(__PREG(Ser2HSCR0), 0x1c),
  248. DEFINE_RES_MEM(__PREG(Ser2HSCR2), 0x04),
  249. DEFINE_RES_IRQ(IRQ_Ser2ICP),
  250. };
  251. static struct platform_device sa11x0ir_device = {
  252. .name = "sa11x0-ir",
  253. .id = -1,
  254. .num_resources = ARRAY_SIZE(sa11x0ir_resources),
  255. .resource = sa11x0ir_resources,
  256. };
  257. void sa11x0_register_irda(struct irda_platform_data *irda)
  258. {
  259. sa11x0_register_device(&sa11x0ir_device, irda);
  260. }
  261. static struct resource sa1100_rtc_resources[] = {
  262. DEFINE_RES_MEM(0x90010000, 0x40),
  263. DEFINE_RES_IRQ_NAMED(IRQ_RTC1Hz, "rtc 1Hz"),
  264. DEFINE_RES_IRQ_NAMED(IRQ_RTCAlrm, "rtc alarm"),
  265. };
  266. static struct platform_device sa11x0rtc_device = {
  267. .name = "sa1100-rtc",
  268. .id = -1,
  269. .num_resources = ARRAY_SIZE(sa1100_rtc_resources),
  270. .resource = sa1100_rtc_resources,
  271. };
  272. static struct resource sa11x0dma_resources[] = {
  273. DEFINE_RES_MEM(DMA_PHYS, DMA_SIZE),
  274. DEFINE_RES_IRQ(IRQ_DMA0),
  275. DEFINE_RES_IRQ(IRQ_DMA1),
  276. DEFINE_RES_IRQ(IRQ_DMA2),
  277. DEFINE_RES_IRQ(IRQ_DMA3),
  278. DEFINE_RES_IRQ(IRQ_DMA4),
  279. DEFINE_RES_IRQ(IRQ_DMA5),
  280. };
  281. static u64 sa11x0dma_dma_mask = DMA_BIT_MASK(32);
  282. static struct platform_device sa11x0dma_device = {
  283. .name = "sa11x0-dma",
  284. .id = -1,
  285. .dev = {
  286. .dma_mask = &sa11x0dma_dma_mask,
  287. .coherent_dma_mask = 0xffffffff,
  288. },
  289. .num_resources = ARRAY_SIZE(sa11x0dma_resources),
  290. .resource = sa11x0dma_resources,
  291. };
  292. static struct platform_device *sa11x0_devices[] __initdata = {
  293. &sa11x0udc_device,
  294. &sa11x0uart1_device,
  295. &sa11x0uart3_device,
  296. &sa11x0ssp_device,
  297. &sa11x0pcmcia_device,
  298. &sa11x0rtc_device,
  299. &sa11x0dma_device,
  300. };
  301. static int __init sa1100_init(void)
  302. {
  303. pm_power_off = sa1100_power_off;
  304. return platform_add_devices(sa11x0_devices, ARRAY_SIZE(sa11x0_devices));
  305. }
  306. arch_initcall(sa1100_init);
  307. void __init sa11x0_init_late(void)
  308. {
  309. sa11x0_pm_init();
  310. }
  311. /*
  312. * Common I/O mapping:
  313. *
  314. * Typically, static virtual address mappings are as follow:
  315. *
  316. * 0xf0000000-0xf3ffffff: miscellaneous stuff (CPLDs, etc.)
  317. * 0xf4000000-0xf4ffffff: SA-1111
  318. * 0xf5000000-0xf5ffffff: reserved (used by cache flushing area)
  319. * 0xf6000000-0xfffeffff: reserved (internal SA1100 IO defined above)
  320. * 0xffff0000-0xffff0fff: SA1100 exception vectors
  321. * 0xffff2000-0xffff2fff: Minicache copy_user_page area
  322. *
  323. * Below 0xe8000000 is reserved for vm allocation.
  324. *
  325. * The machine specific code must provide the extra mapping beside the
  326. * default mapping provided here.
  327. */
  328. static struct map_desc standard_io_desc[] __initdata = {
  329. { /* PCM */
  330. .virtual = 0xf8000000,
  331. .pfn = __phys_to_pfn(0x80000000),
  332. .length = 0x00100000,
  333. .type = MT_DEVICE
  334. }, { /* SCM */
  335. .virtual = 0xfa000000,
  336. .pfn = __phys_to_pfn(0x90000000),
  337. .length = 0x00100000,
  338. .type = MT_DEVICE
  339. }, { /* MER */
  340. .virtual = 0xfc000000,
  341. .pfn = __phys_to_pfn(0xa0000000),
  342. .length = 0x00100000,
  343. .type = MT_DEVICE
  344. }, { /* LCD + DMA */
  345. .virtual = 0xfe000000,
  346. .pfn = __phys_to_pfn(0xb0000000),
  347. .length = 0x00200000,
  348. .type = MT_DEVICE
  349. },
  350. };
  351. void __init sa1100_map_io(void)
  352. {
  353. iotable_init(standard_io_desc, ARRAY_SIZE(standard_io_desc));
  354. }
  355. /*
  356. * Disable the memory bus request/grant signals on the SA1110 to
  357. * ensure that we don't receive spurious memory requests. We set
  358. * the MBGNT signal false to ensure the SA1111 doesn't own the
  359. * SDRAM bus.
  360. */
  361. void sa1110_mb_disable(void)
  362. {
  363. unsigned long flags;
  364. local_irq_save(flags);
  365. PGSR &= ~GPIO_MBGNT;
  366. GPCR = GPIO_MBGNT;
  367. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  368. GAFR &= ~(GPIO_MBGNT | GPIO_MBREQ);
  369. local_irq_restore(flags);
  370. }
  371. /*
  372. * If the system is going to use the SA-1111 DMA engines, set up
  373. * the memory bus request/grant pins.
  374. */
  375. void sa1110_mb_enable(void)
  376. {
  377. unsigned long flags;
  378. local_irq_save(flags);
  379. PGSR &= ~GPIO_MBGNT;
  380. GPCR = GPIO_MBGNT;
  381. GPDR = (GPDR & ~GPIO_MBREQ) | GPIO_MBGNT;
  382. GAFR |= (GPIO_MBGNT | GPIO_MBREQ);
  383. TUCR |= TUCR_MR;
  384. local_irq_restore(flags);
  385. }