common.c 5.3 KB

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  1. /*
  2. * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Copyright 2009 Samsung Electronics Co.
  6. * Byungho Min <bhmin@samsung.com>
  7. *
  8. * Common Codes for S5PC100
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/types.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/list.h>
  18. #include <linux/timer.h>
  19. #include <linux/init.h>
  20. #include <linux/clk.h>
  21. #include <linux/io.h>
  22. #include <linux/device.h>
  23. #include <linux/serial_core.h>
  24. #include <linux/platform_device.h>
  25. #include <linux/sched.h>
  26. #include <linux/reboot.h>
  27. #include <asm/irq.h>
  28. #include <asm/proc-fns.h>
  29. #include <asm/system_misc.h>
  30. #include <asm/mach/arch.h>
  31. #include <asm/mach/map.h>
  32. #include <asm/mach/irq.h>
  33. #include <mach/map.h>
  34. #include <mach/hardware.h>
  35. #include <mach/regs-clock.h>
  36. #include <plat/cpu.h>
  37. #include <plat/devs.h>
  38. #include <plat/clock.h>
  39. #include <plat/sdhci.h>
  40. #include <plat/adc-core.h>
  41. #include <plat/ata-core.h>
  42. #include <plat/fb-core.h>
  43. #include <plat/iic-core.h>
  44. #include <plat/onenand-core.h>
  45. #include <plat/spi-core.h>
  46. #include <plat/regs-serial.h>
  47. #include <plat/watchdog-reset.h>
  48. #include "common.h"
  49. static const char name_s5pc100[] = "S5PC100";
  50. static struct cpu_table cpu_ids[] __initdata = {
  51. {
  52. .idcode = S5PC100_CPU_ID,
  53. .idmask = S5PC100_CPU_MASK,
  54. .map_io = s5pc100_map_io,
  55. .init_clocks = s5pc100_init_clocks,
  56. .init_uarts = s5pc100_init_uarts,
  57. .init = s5pc100_init,
  58. .name = name_s5pc100,
  59. },
  60. };
  61. /* Initial IO mappings */
  62. static struct map_desc s5pc100_iodesc[] __initdata = {
  63. {
  64. .virtual = (unsigned long)S5P_VA_CHIPID,
  65. .pfn = __phys_to_pfn(S5PC100_PA_CHIPID),
  66. .length = SZ_4K,
  67. .type = MT_DEVICE,
  68. }, {
  69. .virtual = (unsigned long)S3C_VA_SYS,
  70. .pfn = __phys_to_pfn(S5PC100_PA_SYSCON),
  71. .length = SZ_64K,
  72. .type = MT_DEVICE,
  73. }, {
  74. .virtual = (unsigned long)S3C_VA_TIMER,
  75. .pfn = __phys_to_pfn(S5PC100_PA_TIMER),
  76. .length = SZ_16K,
  77. .type = MT_DEVICE,
  78. }, {
  79. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  80. .pfn = __phys_to_pfn(S5PC100_PA_WATCHDOG),
  81. .length = SZ_4K,
  82. .type = MT_DEVICE,
  83. }, {
  84. .virtual = (unsigned long)S5P_VA_SROMC,
  85. .pfn = __phys_to_pfn(S5PC100_PA_SROMC),
  86. .length = SZ_4K,
  87. .type = MT_DEVICE,
  88. }, {
  89. .virtual = (unsigned long)S5P_VA_SYSTIMER,
  90. .pfn = __phys_to_pfn(S5PC100_PA_SYSTIMER),
  91. .length = SZ_16K,
  92. .type = MT_DEVICE,
  93. }, {
  94. .virtual = (unsigned long)S5P_VA_GPIO,
  95. .pfn = __phys_to_pfn(S5PC100_PA_GPIO),
  96. .length = SZ_4K,
  97. .type = MT_DEVICE,
  98. }, {
  99. .virtual = (unsigned long)VA_VIC0,
  100. .pfn = __phys_to_pfn(S5PC100_PA_VIC0),
  101. .length = SZ_16K,
  102. .type = MT_DEVICE,
  103. }, {
  104. .virtual = (unsigned long)VA_VIC1,
  105. .pfn = __phys_to_pfn(S5PC100_PA_VIC1),
  106. .length = SZ_16K,
  107. .type = MT_DEVICE,
  108. }, {
  109. .virtual = (unsigned long)VA_VIC2,
  110. .pfn = __phys_to_pfn(S5PC100_PA_VIC2),
  111. .length = SZ_16K,
  112. .type = MT_DEVICE,
  113. }, {
  114. .virtual = (unsigned long)S3C_VA_UART,
  115. .pfn = __phys_to_pfn(S3C_PA_UART),
  116. .length = SZ_512K,
  117. .type = MT_DEVICE,
  118. }, {
  119. .virtual = (unsigned long)S5PC100_VA_OTHERS,
  120. .pfn = __phys_to_pfn(S5PC100_PA_OTHERS),
  121. .length = SZ_4K,
  122. .type = MT_DEVICE,
  123. }
  124. };
  125. /*
  126. * s5pc100_map_io
  127. *
  128. * register the standard CPU IO areas
  129. */
  130. void __init s5pc100_init_io(struct map_desc *mach_desc, int size)
  131. {
  132. /* initialize the io descriptors we need for initialization */
  133. iotable_init(s5pc100_iodesc, ARRAY_SIZE(s5pc100_iodesc));
  134. if (mach_desc)
  135. iotable_init(mach_desc, size);
  136. /* detect cpu id and rev. */
  137. s5p_init_cpu(S5P_VA_CHIPID);
  138. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  139. }
  140. void __init s5pc100_map_io(void)
  141. {
  142. /* initialise device information early */
  143. s5pc100_default_sdhci0();
  144. s5pc100_default_sdhci1();
  145. s5pc100_default_sdhci2();
  146. s3c_adc_setname("s3c64xx-adc");
  147. /* the i2c devices are directly compatible with s3c2440 */
  148. s3c_i2c0_setname("s3c2440-i2c");
  149. s3c_i2c1_setname("s3c2440-i2c");
  150. s3c_onenand_setname("s5pc100-onenand");
  151. s3c_fb_setname("s5pc100-fb");
  152. s3c_cfcon_setname("s5pc100-pata");
  153. s3c64xx_spi_setname("s5pc100-spi");
  154. }
  155. void __init s5pc100_init_clocks(int xtal)
  156. {
  157. printk(KERN_DEBUG "%s: initializing clocks\n", __func__);
  158. s3c24xx_register_baseclocks(xtal);
  159. s5p_register_clocks(xtal);
  160. s5pc100_register_clocks();
  161. s5pc100_setup_clocks();
  162. samsung_wdt_reset_init(S3C_VA_WATCHDOG);
  163. }
  164. void __init s5pc100_init_irq(void)
  165. {
  166. u32 vic[] = {~0, ~0, ~0};
  167. /* VIC0, VIC1, and VIC2 are fully populated. */
  168. s5p_init_irq(vic, ARRAY_SIZE(vic));
  169. }
  170. static struct bus_type s5pc100_subsys = {
  171. .name = "s5pc100-core",
  172. .dev_name = "s5pc100-core",
  173. };
  174. static struct device s5pc100_dev = {
  175. .bus = &s5pc100_subsys,
  176. };
  177. static int __init s5pc100_core_init(void)
  178. {
  179. return subsys_system_register(&s5pc100_subsys, NULL);
  180. }
  181. core_initcall(s5pc100_core_init);
  182. int __init s5pc100_init(void)
  183. {
  184. printk(KERN_INFO "S5PC100: Initializing architecture\n");
  185. return device_register(&s5pc100_dev);
  186. }
  187. /* uart registration process */
  188. void __init s5pc100_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  189. {
  190. s3c24xx_init_uartdevs("s3c6400-uart", s5p_uart_resources, cfg, no);
  191. }
  192. void s5pc100_restart(enum reboot_mode mode, const char *cmd)
  193. {
  194. if (mode != REBOOT_SOFT)
  195. samsung_wdt_reset();
  196. soft_restart(0);
  197. }