common.c 9.3 KB

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  1. /*
  2. * Copyright (c) 2011 Samsung Electronics Co., Ltd.
  3. * http://www.samsung.com
  4. *
  5. * Copyright 2008 Openmoko, Inc.
  6. * Copyright 2008 Simtec Electronics
  7. * Ben Dooks <ben@simtec.co.uk>
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * Common Codes for S3C64XX machines
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/init.h>
  18. #include <linux/module.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/ioport.h>
  21. #include <linux/serial_core.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/reboot.h>
  24. #include <linux/io.h>
  25. #include <linux/dma-mapping.h>
  26. #include <linux/irq.h>
  27. #include <linux/gpio.h>
  28. #include <linux/irqchip/arm-vic.h>
  29. #include <asm/mach/arch.h>
  30. #include <asm/mach/map.h>
  31. #include <asm/system_misc.h>
  32. #include <mach/map.h>
  33. #include <mach/hardware.h>
  34. #include <mach/regs-gpio.h>
  35. #include <plat/cpu.h>
  36. #include <plat/clock.h>
  37. #include <plat/devs.h>
  38. #include <plat/pm.h>
  39. #include <plat/gpio-cfg.h>
  40. #include <plat/irq-uart.h>
  41. #include <plat/irq-vic-timer.h>
  42. #include <plat/regs-irqtype.h>
  43. #include <plat/regs-serial.h>
  44. #include <plat/watchdog-reset.h>
  45. #include "common.h"
  46. /* uart registration process */
  47. static void __init s3c64xx_init_uarts(struct s3c2410_uartcfg *cfg, int no)
  48. {
  49. s3c24xx_init_uartdevs("s3c6400-uart", s3c64xx_uart_resources, cfg, no);
  50. }
  51. /* table of supported CPUs */
  52. static const char name_s3c6400[] = "S3C6400";
  53. static const char name_s3c6410[] = "S3C6410";
  54. static struct cpu_table cpu_ids[] __initdata = {
  55. {
  56. .idcode = S3C6400_CPU_ID,
  57. .idmask = S3C64XX_CPU_MASK,
  58. .map_io = s3c6400_map_io,
  59. .init_clocks = s3c6400_init_clocks,
  60. .init_uarts = s3c64xx_init_uarts,
  61. .init = s3c6400_init,
  62. .name = name_s3c6400,
  63. }, {
  64. .idcode = S3C6410_CPU_ID,
  65. .idmask = S3C64XX_CPU_MASK,
  66. .map_io = s3c6410_map_io,
  67. .init_clocks = s3c6410_init_clocks,
  68. .init_uarts = s3c64xx_init_uarts,
  69. .init = s3c6410_init,
  70. .name = name_s3c6410,
  71. },
  72. };
  73. /* minimal IO mapping */
  74. /* see notes on uart map in arch/arm/mach-s3c64xx/include/mach/debug-macro.S */
  75. #define UART_OFFS (S3C_PA_UART & 0xfffff)
  76. static struct map_desc s3c_iodesc[] __initdata = {
  77. {
  78. .virtual = (unsigned long)S3C_VA_SYS,
  79. .pfn = __phys_to_pfn(S3C64XX_PA_SYSCON),
  80. .length = SZ_4K,
  81. .type = MT_DEVICE,
  82. }, {
  83. .virtual = (unsigned long)S3C_VA_MEM,
  84. .pfn = __phys_to_pfn(S3C64XX_PA_SROM),
  85. .length = SZ_4K,
  86. .type = MT_DEVICE,
  87. }, {
  88. .virtual = (unsigned long)(S3C_VA_UART + UART_OFFS),
  89. .pfn = __phys_to_pfn(S3C_PA_UART),
  90. .length = SZ_4K,
  91. .type = MT_DEVICE,
  92. }, {
  93. .virtual = (unsigned long)VA_VIC0,
  94. .pfn = __phys_to_pfn(S3C64XX_PA_VIC0),
  95. .length = SZ_16K,
  96. .type = MT_DEVICE,
  97. }, {
  98. .virtual = (unsigned long)VA_VIC1,
  99. .pfn = __phys_to_pfn(S3C64XX_PA_VIC1),
  100. .length = SZ_16K,
  101. .type = MT_DEVICE,
  102. }, {
  103. .virtual = (unsigned long)S3C_VA_TIMER,
  104. .pfn = __phys_to_pfn(S3C_PA_TIMER),
  105. .length = SZ_16K,
  106. .type = MT_DEVICE,
  107. }, {
  108. .virtual = (unsigned long)S3C64XX_VA_GPIO,
  109. .pfn = __phys_to_pfn(S3C64XX_PA_GPIO),
  110. .length = SZ_4K,
  111. .type = MT_DEVICE,
  112. }, {
  113. .virtual = (unsigned long)S3C64XX_VA_MODEM,
  114. .pfn = __phys_to_pfn(S3C64XX_PA_MODEM),
  115. .length = SZ_4K,
  116. .type = MT_DEVICE,
  117. }, {
  118. .virtual = (unsigned long)S3C_VA_WATCHDOG,
  119. .pfn = __phys_to_pfn(S3C64XX_PA_WATCHDOG),
  120. .length = SZ_4K,
  121. .type = MT_DEVICE,
  122. }, {
  123. .virtual = (unsigned long)S3C_VA_USB_HSPHY,
  124. .pfn = __phys_to_pfn(S3C64XX_PA_USB_HSPHY),
  125. .length = SZ_1K,
  126. .type = MT_DEVICE,
  127. },
  128. };
  129. static struct bus_type s3c64xx_subsys = {
  130. .name = "s3c64xx-core",
  131. .dev_name = "s3c64xx-core",
  132. };
  133. static struct device s3c64xx_dev = {
  134. .bus = &s3c64xx_subsys,
  135. };
  136. /* read cpu identification code */
  137. void __init s3c64xx_init_io(struct map_desc *mach_desc, int size)
  138. {
  139. /* initialise the io descriptors we need for initialisation */
  140. iotable_init(s3c_iodesc, ARRAY_SIZE(s3c_iodesc));
  141. iotable_init(mach_desc, size);
  142. /* detect cpu id */
  143. s3c64xx_init_cpu();
  144. s3c_init_cpu(samsung_cpu_id, cpu_ids, ARRAY_SIZE(cpu_ids));
  145. }
  146. static __init int s3c64xx_dev_init(void)
  147. {
  148. subsys_system_register(&s3c64xx_subsys, NULL);
  149. return device_register(&s3c64xx_dev);
  150. }
  151. core_initcall(s3c64xx_dev_init);
  152. /*
  153. * setup the sources the vic should advertise resume
  154. * for, even though it is not doing the wake
  155. * (set_irq_wake needs to be valid)
  156. */
  157. #define IRQ_VIC0_RESUME (1 << (IRQ_RTC_TIC - IRQ_VIC0_BASE))
  158. #define IRQ_VIC1_RESUME (1 << (IRQ_RTC_ALARM - IRQ_VIC1_BASE) | \
  159. 1 << (IRQ_PENDN - IRQ_VIC1_BASE) | \
  160. 1 << (IRQ_HSMMC0 - IRQ_VIC1_BASE) | \
  161. 1 << (IRQ_HSMMC1 - IRQ_VIC1_BASE) | \
  162. 1 << (IRQ_HSMMC2 - IRQ_VIC1_BASE))
  163. void __init s3c64xx_init_irq(u32 vic0_valid, u32 vic1_valid)
  164. {
  165. /*
  166. * FIXME: there is no better place to put this at the moment
  167. * (samsung_wdt_reset_init needs clocks)
  168. */
  169. samsung_wdt_reset_init(S3C_VA_WATCHDOG);
  170. printk(KERN_DEBUG "%s: initialising interrupts\n", __func__);
  171. /* initialise the pair of VICs */
  172. vic_init(VA_VIC0, IRQ_VIC0_BASE, vic0_valid, IRQ_VIC0_RESUME);
  173. vic_init(VA_VIC1, IRQ_VIC1_BASE, vic1_valid, IRQ_VIC1_RESUME);
  174. /* add the timer sub-irqs */
  175. s3c_init_vic_timer_irq(5, IRQ_TIMER0);
  176. }
  177. #define eint_offset(irq) ((irq) - IRQ_EINT(0))
  178. #define eint_irq_to_bit(irq) ((u32)(1 << eint_offset(irq)))
  179. static inline void s3c_irq_eint_mask(struct irq_data *data)
  180. {
  181. u32 mask;
  182. mask = __raw_readl(S3C64XX_EINT0MASK);
  183. mask |= (u32)data->chip_data;
  184. __raw_writel(mask, S3C64XX_EINT0MASK);
  185. }
  186. static void s3c_irq_eint_unmask(struct irq_data *data)
  187. {
  188. u32 mask;
  189. mask = __raw_readl(S3C64XX_EINT0MASK);
  190. mask &= ~((u32)data->chip_data);
  191. __raw_writel(mask, S3C64XX_EINT0MASK);
  192. }
  193. static inline void s3c_irq_eint_ack(struct irq_data *data)
  194. {
  195. __raw_writel((u32)data->chip_data, S3C64XX_EINT0PEND);
  196. }
  197. static void s3c_irq_eint_maskack(struct irq_data *data)
  198. {
  199. /* compiler should in-line these */
  200. s3c_irq_eint_mask(data);
  201. s3c_irq_eint_ack(data);
  202. }
  203. static int s3c_irq_eint_set_type(struct irq_data *data, unsigned int type)
  204. {
  205. int offs = eint_offset(data->irq);
  206. int pin, pin_val;
  207. int shift;
  208. u32 ctrl, mask;
  209. u32 newvalue = 0;
  210. void __iomem *reg;
  211. if (offs > 27)
  212. return -EINVAL;
  213. if (offs <= 15)
  214. reg = S3C64XX_EINT0CON0;
  215. else
  216. reg = S3C64XX_EINT0CON1;
  217. switch (type) {
  218. case IRQ_TYPE_NONE:
  219. printk(KERN_WARNING "No edge setting!\n");
  220. break;
  221. case IRQ_TYPE_EDGE_RISING:
  222. newvalue = S3C2410_EXTINT_RISEEDGE;
  223. break;
  224. case IRQ_TYPE_EDGE_FALLING:
  225. newvalue = S3C2410_EXTINT_FALLEDGE;
  226. break;
  227. case IRQ_TYPE_EDGE_BOTH:
  228. newvalue = S3C2410_EXTINT_BOTHEDGE;
  229. break;
  230. case IRQ_TYPE_LEVEL_LOW:
  231. newvalue = S3C2410_EXTINT_LOWLEV;
  232. break;
  233. case IRQ_TYPE_LEVEL_HIGH:
  234. newvalue = S3C2410_EXTINT_HILEV;
  235. break;
  236. default:
  237. printk(KERN_ERR "No such irq type %d", type);
  238. return -1;
  239. }
  240. if (offs <= 15)
  241. shift = (offs / 2) * 4;
  242. else
  243. shift = ((offs - 16) / 2) * 4;
  244. mask = 0x7 << shift;
  245. ctrl = __raw_readl(reg);
  246. ctrl &= ~mask;
  247. ctrl |= newvalue << shift;
  248. __raw_writel(ctrl, reg);
  249. /* set the GPIO pin appropriately */
  250. if (offs < 16) {
  251. pin = S3C64XX_GPN(offs);
  252. pin_val = S3C_GPIO_SFN(2);
  253. } else if (offs < 23) {
  254. pin = S3C64XX_GPL(offs + 8 - 16);
  255. pin_val = S3C_GPIO_SFN(3);
  256. } else {
  257. pin = S3C64XX_GPM(offs - 23);
  258. pin_val = S3C_GPIO_SFN(3);
  259. }
  260. s3c_gpio_cfgpin(pin, pin_val);
  261. return 0;
  262. }
  263. static struct irq_chip s3c_irq_eint = {
  264. .name = "s3c-eint",
  265. .irq_mask = s3c_irq_eint_mask,
  266. .irq_unmask = s3c_irq_eint_unmask,
  267. .irq_mask_ack = s3c_irq_eint_maskack,
  268. .irq_ack = s3c_irq_eint_ack,
  269. .irq_set_type = s3c_irq_eint_set_type,
  270. .irq_set_wake = s3c_irqext_wake,
  271. };
  272. /* s3c_irq_demux_eint
  273. *
  274. * This function demuxes the IRQ from the group0 external interrupts,
  275. * from IRQ_EINT(0) to IRQ_EINT(27). It is designed to be inlined into
  276. * the specific handlers s3c_irq_demux_eintX_Y.
  277. */
  278. static inline void s3c_irq_demux_eint(unsigned int start, unsigned int end)
  279. {
  280. u32 status = __raw_readl(S3C64XX_EINT0PEND);
  281. u32 mask = __raw_readl(S3C64XX_EINT0MASK);
  282. unsigned int irq;
  283. status &= ~mask;
  284. status >>= start;
  285. status &= (1 << (end - start + 1)) - 1;
  286. for (irq = IRQ_EINT(start); irq <= IRQ_EINT(end); irq++) {
  287. if (status & 1)
  288. generic_handle_irq(irq);
  289. status >>= 1;
  290. }
  291. }
  292. static void s3c_irq_demux_eint0_3(unsigned int irq, struct irq_desc *desc)
  293. {
  294. s3c_irq_demux_eint(0, 3);
  295. }
  296. static void s3c_irq_demux_eint4_11(unsigned int irq, struct irq_desc *desc)
  297. {
  298. s3c_irq_demux_eint(4, 11);
  299. }
  300. static void s3c_irq_demux_eint12_19(unsigned int irq, struct irq_desc *desc)
  301. {
  302. s3c_irq_demux_eint(12, 19);
  303. }
  304. static void s3c_irq_demux_eint20_27(unsigned int irq, struct irq_desc *desc)
  305. {
  306. s3c_irq_demux_eint(20, 27);
  307. }
  308. static int __init s3c64xx_init_irq_eint(void)
  309. {
  310. int irq;
  311. for (irq = IRQ_EINT(0); irq <= IRQ_EINT(27); irq++) {
  312. irq_set_chip_and_handler(irq, &s3c_irq_eint, handle_level_irq);
  313. irq_set_chip_data(irq, (void *)eint_irq_to_bit(irq));
  314. set_irq_flags(irq, IRQF_VALID);
  315. }
  316. irq_set_chained_handler(IRQ_EINT0_3, s3c_irq_demux_eint0_3);
  317. irq_set_chained_handler(IRQ_EINT4_11, s3c_irq_demux_eint4_11);
  318. irq_set_chained_handler(IRQ_EINT12_19, s3c_irq_demux_eint12_19);
  319. irq_set_chained_handler(IRQ_EINT20_27, s3c_irq_demux_eint20_27);
  320. return 0;
  321. }
  322. arch_initcall(s3c64xx_init_irq_eint);
  323. void s3c64xx_restart(enum reboot_mode mode, const char *cmd)
  324. {
  325. if (mode != REBOOT_SOFT)
  326. samsung_wdt_reset();
  327. /* if all else fails, or mode was for soft, jump to 0 */
  328. soft_restart(0);
  329. }
  330. void __init s3c64xx_init_late(void)
  331. {
  332. s3c64xx_pm_late_initcall();
  333. }