dma-s3c2443.c 4.2 KB

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  1. /* linux/arch/arm/mach-s3c2443/dma.c
  2. *
  3. * Copyright (c) 2007 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2443 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <linux/io.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-dma.h>
  25. #include <mach/regs-lcd.h>
  26. #include <plat/regs-spi.h>
  27. #define MAP(x) { \
  28. [0] = (x) | DMA_CH_VALID, \
  29. [1] = (x) | DMA_CH_VALID, \
  30. [2] = (x) | DMA_CH_VALID, \
  31. [3] = (x) | DMA_CH_VALID, \
  32. [4] = (x) | DMA_CH_VALID, \
  33. [5] = (x) | DMA_CH_VALID, \
  34. }
  35. static struct s3c24xx_dma_map __initdata s3c2443_dma_mappings[] = {
  36. [DMACH_XD0] = {
  37. .name = "xdreq0",
  38. .channels = MAP(S3C2443_DMAREQSEL_XDREQ0),
  39. },
  40. [DMACH_XD1] = {
  41. .name = "xdreq1",
  42. .channels = MAP(S3C2443_DMAREQSEL_XDREQ1),
  43. },
  44. [DMACH_SDI] = { /* only on S3C2443 */
  45. .name = "sdi",
  46. .channels = MAP(S3C2443_DMAREQSEL_SDI),
  47. },
  48. [DMACH_SPI0_RX] = {
  49. .name = "spi0-rx",
  50. .channels = MAP(S3C2443_DMAREQSEL_SPI0RX),
  51. },
  52. [DMACH_SPI0_TX] = {
  53. .name = "spi0-tx",
  54. .channels = MAP(S3C2443_DMAREQSEL_SPI0TX),
  55. },
  56. [DMACH_SPI1_RX] = { /* only on S3C2443/S3C2450 */
  57. .name = "spi1-rx",
  58. .channels = MAP(S3C2443_DMAREQSEL_SPI1RX),
  59. },
  60. [DMACH_SPI1_TX] = { /* only on S3C2443/S3C2450 */
  61. .name = "spi1-tx",
  62. .channels = MAP(S3C2443_DMAREQSEL_SPI1TX),
  63. },
  64. [DMACH_UART0] = {
  65. .name = "uart0",
  66. .channels = MAP(S3C2443_DMAREQSEL_UART0_0),
  67. },
  68. [DMACH_UART1] = {
  69. .name = "uart1",
  70. .channels = MAP(S3C2443_DMAREQSEL_UART1_0),
  71. },
  72. [DMACH_UART2] = {
  73. .name = "uart2",
  74. .channels = MAP(S3C2443_DMAREQSEL_UART2_0),
  75. },
  76. [DMACH_UART3] = {
  77. .name = "uart3",
  78. .channels = MAP(S3C2443_DMAREQSEL_UART3_0),
  79. },
  80. [DMACH_UART0_SRC2] = {
  81. .name = "uart0",
  82. .channels = MAP(S3C2443_DMAREQSEL_UART0_1),
  83. },
  84. [DMACH_UART1_SRC2] = {
  85. .name = "uart1",
  86. .channels = MAP(S3C2443_DMAREQSEL_UART1_1),
  87. },
  88. [DMACH_UART2_SRC2] = {
  89. .name = "uart2",
  90. .channels = MAP(S3C2443_DMAREQSEL_UART2_1),
  91. },
  92. [DMACH_UART3_SRC2] = {
  93. .name = "uart3",
  94. .channels = MAP(S3C2443_DMAREQSEL_UART3_1),
  95. },
  96. [DMACH_TIMER] = {
  97. .name = "timer",
  98. .channels = MAP(S3C2443_DMAREQSEL_TIMER),
  99. },
  100. [DMACH_I2S_IN] = {
  101. .name = "i2s-sdi",
  102. .channels = MAP(S3C2443_DMAREQSEL_I2SRX),
  103. },
  104. [DMACH_I2S_OUT] = {
  105. .name = "i2s-sdo",
  106. .channels = MAP(S3C2443_DMAREQSEL_I2STX),
  107. },
  108. [DMACH_PCM_IN] = {
  109. .name = "pcm-in",
  110. .channels = MAP(S3C2443_DMAREQSEL_PCMIN),
  111. },
  112. [DMACH_PCM_OUT] = {
  113. .name = "pcm-out",
  114. .channels = MAP(S3C2443_DMAREQSEL_PCMOUT),
  115. },
  116. [DMACH_MIC_IN] = {
  117. .name = "mic-in",
  118. .channels = MAP(S3C2443_DMAREQSEL_MICIN),
  119. },
  120. };
  121. static void s3c2443_dma_select(struct s3c2410_dma_chan *chan,
  122. struct s3c24xx_dma_map *map)
  123. {
  124. unsigned long chsel = map->channels[0] & (~DMA_CH_VALID);
  125. writel(chsel | S3C2443_DMAREQSEL_HW,
  126. chan->regs + S3C2443_DMA_DMAREQSEL);
  127. }
  128. static struct s3c24xx_dma_selection __initdata s3c2443_dma_sel = {
  129. .select = s3c2443_dma_select,
  130. .dcon_mask = 0,
  131. .map = s3c2443_dma_mappings,
  132. .map_size = ARRAY_SIZE(s3c2443_dma_mappings),
  133. };
  134. static int __init s3c2443_dma_add(struct device *dev,
  135. struct subsys_interface *sif)
  136. {
  137. s3c24xx_dma_init(6, IRQ_S3C2443_DMA0, 0x100);
  138. return s3c24xx_dma_init_map(&s3c2443_dma_sel);
  139. }
  140. #ifdef CONFIG_CPU_S3C2416
  141. /* S3C2416 DMA contains the same selection table as the S3C2443 */
  142. static struct subsys_interface s3c2416_dma_interface = {
  143. .name = "s3c2416_dma",
  144. .subsys = &s3c2416_subsys,
  145. .add_dev = s3c2443_dma_add,
  146. };
  147. static int __init s3c2416_dma_init(void)
  148. {
  149. return subsys_interface_register(&s3c2416_dma_interface);
  150. }
  151. arch_initcall(s3c2416_dma_init);
  152. #endif
  153. #ifdef CONFIG_CPU_S3C2443
  154. static struct subsys_interface s3c2443_dma_interface = {
  155. .name = "s3c2443_dma",
  156. .subsys = &s3c2443_subsys,
  157. .add_dev = s3c2443_dma_add,
  158. };
  159. static int __init s3c2443_dma_init(void)
  160. {
  161. return subsys_interface_register(&s3c2443_dma_interface);
  162. }
  163. arch_initcall(s3c2443_dma_init);
  164. #endif