dma-s3c2440.c 4.7 KB

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  1. /* linux/arch/arm/mach-s3c2440/dma.c
  2. *
  3. * Copyright (c) 2006 Simtec Electronics
  4. * Ben Dooks <ben@simtec.co.uk>
  5. *
  6. * S3C2440 DMA selection
  7. *
  8. * http://armlinux.simtec.co.uk/
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License version 2 as
  12. * published by the Free Software Foundation.
  13. */
  14. #include <linux/kernel.h>
  15. #include <linux/init.h>
  16. #include <linux/device.h>
  17. #include <linux/serial_core.h>
  18. #include <mach/map.h>
  19. #include <mach/dma.h>
  20. #include <plat/dma-s3c24xx.h>
  21. #include <plat/cpu.h>
  22. #include <plat/regs-serial.h>
  23. #include <mach/regs-gpio.h>
  24. #include <plat/regs-dma.h>
  25. #include <mach/regs-lcd.h>
  26. #include <plat/regs-spi.h>
  27. static struct s3c24xx_dma_map __initdata s3c2440_dma_mappings[] = {
  28. [DMACH_XD0] = {
  29. .name = "xdreq0",
  30. .channels[0] = S3C2410_DCON_CH0_XDREQ0 | DMA_CH_VALID,
  31. },
  32. [DMACH_XD1] = {
  33. .name = "xdreq1",
  34. .channels[1] = S3C2410_DCON_CH1_XDREQ1 | DMA_CH_VALID,
  35. },
  36. [DMACH_SDI] = {
  37. .name = "sdi",
  38. .channels[0] = S3C2410_DCON_CH0_SDI | DMA_CH_VALID,
  39. .channels[1] = S3C2440_DCON_CH1_SDI | DMA_CH_VALID,
  40. .channels[2] = S3C2410_DCON_CH2_SDI | DMA_CH_VALID,
  41. .channels[3] = S3C2410_DCON_CH3_SDI | DMA_CH_VALID,
  42. },
  43. [DMACH_SPI0] = {
  44. .name = "spi0",
  45. .channels[1] = S3C2410_DCON_CH1_SPI | DMA_CH_VALID,
  46. },
  47. [DMACH_SPI1] = {
  48. .name = "spi1",
  49. .channels[3] = S3C2410_DCON_CH3_SPI | DMA_CH_VALID,
  50. },
  51. [DMACH_UART0] = {
  52. .name = "uart0",
  53. .channels[0] = S3C2410_DCON_CH0_UART0 | DMA_CH_VALID,
  54. },
  55. [DMACH_UART1] = {
  56. .name = "uart1",
  57. .channels[1] = S3C2410_DCON_CH1_UART1 | DMA_CH_VALID,
  58. },
  59. [DMACH_UART2] = {
  60. .name = "uart2",
  61. .channels[3] = S3C2410_DCON_CH3_UART2 | DMA_CH_VALID,
  62. },
  63. [DMACH_TIMER] = {
  64. .name = "timer",
  65. .channels[0] = S3C2410_DCON_CH0_TIMER | DMA_CH_VALID,
  66. .channels[2] = S3C2410_DCON_CH2_TIMER | DMA_CH_VALID,
  67. .channels[3] = S3C2410_DCON_CH3_TIMER | DMA_CH_VALID,
  68. },
  69. [DMACH_I2S_IN] = {
  70. .name = "i2s-sdi",
  71. .channels[1] = S3C2410_DCON_CH1_I2SSDI | DMA_CH_VALID,
  72. .channels[2] = S3C2410_DCON_CH2_I2SSDI | DMA_CH_VALID,
  73. },
  74. [DMACH_I2S_OUT] = {
  75. .name = "i2s-sdo",
  76. .channels[0] = S3C2440_DCON_CH0_I2SSDO | DMA_CH_VALID,
  77. .channels[2] = S3C2410_DCON_CH2_I2SSDO | DMA_CH_VALID,
  78. },
  79. [DMACH_PCM_IN] = {
  80. .name = "pcm-in",
  81. .channels[0] = S3C2440_DCON_CH0_PCMIN | DMA_CH_VALID,
  82. .channels[2] = S3C2440_DCON_CH2_PCMIN | DMA_CH_VALID,
  83. },
  84. [DMACH_PCM_OUT] = {
  85. .name = "pcm-out",
  86. .channels[1] = S3C2440_DCON_CH1_PCMOUT | DMA_CH_VALID,
  87. .channels[3] = S3C2440_DCON_CH3_PCMOUT | DMA_CH_VALID,
  88. },
  89. [DMACH_MIC_IN] = {
  90. .name = "mic-in",
  91. .channels[2] = S3C2440_DCON_CH2_MICIN | DMA_CH_VALID,
  92. .channels[3] = S3C2440_DCON_CH3_MICIN | DMA_CH_VALID,
  93. },
  94. [DMACH_USB_EP1] = {
  95. .name = "usb-ep1",
  96. .channels[0] = S3C2410_DCON_CH0_USBEP1 | DMA_CH_VALID,
  97. },
  98. [DMACH_USB_EP2] = {
  99. .name = "usb-ep2",
  100. .channels[1] = S3C2410_DCON_CH1_USBEP2 | DMA_CH_VALID,
  101. },
  102. [DMACH_USB_EP3] = {
  103. .name = "usb-ep3",
  104. .channels[2] = S3C2410_DCON_CH2_USBEP3 | DMA_CH_VALID,
  105. },
  106. [DMACH_USB_EP4] = {
  107. .name = "usb-ep4",
  108. .channels[3] = S3C2410_DCON_CH3_USBEP4 | DMA_CH_VALID,
  109. },
  110. };
  111. static void s3c2440_dma_select(struct s3c2410_dma_chan *chan,
  112. struct s3c24xx_dma_map *map)
  113. {
  114. chan->dcon = map->channels[chan->number] & ~DMA_CH_VALID;
  115. }
  116. static struct s3c24xx_dma_selection __initdata s3c2440_dma_sel = {
  117. .select = s3c2440_dma_select,
  118. .dcon_mask = 7 << 24,
  119. .map = s3c2440_dma_mappings,
  120. .map_size = ARRAY_SIZE(s3c2440_dma_mappings),
  121. };
  122. static struct s3c24xx_dma_order __initdata s3c2440_dma_order = {
  123. .channels = {
  124. [DMACH_SDI] = {
  125. .list = {
  126. [0] = 3 | DMA_CH_VALID,
  127. [1] = 2 | DMA_CH_VALID,
  128. [2] = 1 | DMA_CH_VALID,
  129. [3] = 0 | DMA_CH_VALID,
  130. },
  131. },
  132. [DMACH_I2S_IN] = {
  133. .list = {
  134. [0] = 1 | DMA_CH_VALID,
  135. [1] = 2 | DMA_CH_VALID,
  136. },
  137. },
  138. [DMACH_I2S_OUT] = {
  139. .list = {
  140. [0] = 2 | DMA_CH_VALID,
  141. [1] = 1 | DMA_CH_VALID,
  142. },
  143. },
  144. [DMACH_PCM_IN] = {
  145. .list = {
  146. [0] = 2 | DMA_CH_VALID,
  147. [1] = 1 | DMA_CH_VALID,
  148. },
  149. },
  150. [DMACH_PCM_OUT] = {
  151. .list = {
  152. [0] = 1 | DMA_CH_VALID,
  153. [1] = 3 | DMA_CH_VALID,
  154. },
  155. },
  156. [DMACH_MIC_IN] = {
  157. .list = {
  158. [0] = 3 | DMA_CH_VALID,
  159. [1] = 2 | DMA_CH_VALID,
  160. },
  161. },
  162. },
  163. };
  164. static int __init s3c2440_dma_add(struct device *dev,
  165. struct subsys_interface *sif)
  166. {
  167. s3c2410_dma_init();
  168. s3c24xx_dma_order_set(&s3c2440_dma_order);
  169. return s3c24xx_dma_init_map(&s3c2440_dma_sel);
  170. }
  171. static struct subsys_interface s3c2440_dma_interface = {
  172. .name = "s3c2440_dma",
  173. .subsys = &s3c2440_subsys,
  174. .add_dev = s3c2440_dma_add,
  175. };
  176. static int __init s3c2440_dma_init(void)
  177. {
  178. return subsys_interface_register(&s3c2440_dma_interface);
  179. }
  180. arch_initcall(s3c2440_dma_init);