clock-s3c2410.c 6.7 KB

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  1. /*
  2. * Copyright (c) 2006 Simtec Electronics
  3. * Ben Dooks <ben@simtec.co.uk>
  4. *
  5. * S3C2410,S3C2440,S3C2442 Clock control support
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. *
  12. * This program is distributed in the hope that it will be useful,
  13. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License
  18. * along with this program; if not, write to the Free Software
  19. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  20. */
  21. #include <linux/init.h>
  22. #include <linux/module.h>
  23. #include <linux/kernel.h>
  24. #include <linux/list.h>
  25. #include <linux/errno.h>
  26. #include <linux/err.h>
  27. #include <linux/device.h>
  28. #include <linux/clk.h>
  29. #include <linux/mutex.h>
  30. #include <linux/delay.h>
  31. #include <linux/serial_core.h>
  32. #include <linux/io.h>
  33. #include <asm/mach/map.h>
  34. #include <mach/hardware.h>
  35. #include <plat/regs-serial.h>
  36. #include <mach/regs-clock.h>
  37. #include <mach/regs-gpio.h>
  38. #include <plat/clock.h>
  39. #include <plat/cpu.h>
  40. int s3c2410_clkcon_enable(struct clk *clk, int enable)
  41. {
  42. unsigned int clocks = clk->ctrlbit;
  43. unsigned long clkcon;
  44. clkcon = __raw_readl(S3C2410_CLKCON);
  45. if (enable)
  46. clkcon |= clocks;
  47. else
  48. clkcon &= ~clocks;
  49. /* ensure none of the special function bits set */
  50. clkcon &= ~(S3C2410_CLKCON_IDLE|S3C2410_CLKCON_POWER);
  51. __raw_writel(clkcon, S3C2410_CLKCON);
  52. return 0;
  53. }
  54. static int s3c2410_upll_enable(struct clk *clk, int enable)
  55. {
  56. unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
  57. unsigned long orig = clkslow;
  58. if (enable)
  59. clkslow &= ~S3C2410_CLKSLOW_UCLK_OFF;
  60. else
  61. clkslow |= S3C2410_CLKSLOW_UCLK_OFF;
  62. __raw_writel(clkslow, S3C2410_CLKSLOW);
  63. /* if we started the UPLL, then allow to settle */
  64. if (enable && (orig & S3C2410_CLKSLOW_UCLK_OFF))
  65. udelay(200);
  66. return 0;
  67. }
  68. /* standard clock definitions */
  69. static struct clk init_clocks_off[] = {
  70. {
  71. .name = "nand",
  72. .parent = &clk_h,
  73. .enable = s3c2410_clkcon_enable,
  74. .ctrlbit = S3C2410_CLKCON_NAND,
  75. }, {
  76. .name = "sdi",
  77. .parent = &clk_p,
  78. .enable = s3c2410_clkcon_enable,
  79. .ctrlbit = S3C2410_CLKCON_SDI,
  80. }, {
  81. .name = "adc",
  82. .parent = &clk_p,
  83. .enable = s3c2410_clkcon_enable,
  84. .ctrlbit = S3C2410_CLKCON_ADC,
  85. }, {
  86. .name = "i2c",
  87. .parent = &clk_p,
  88. .enable = s3c2410_clkcon_enable,
  89. .ctrlbit = S3C2410_CLKCON_IIC,
  90. }, {
  91. .name = "iis",
  92. .parent = &clk_p,
  93. .enable = s3c2410_clkcon_enable,
  94. .ctrlbit = S3C2410_CLKCON_IIS,
  95. }, {
  96. .name = "spi",
  97. .parent = &clk_p,
  98. .enable = s3c2410_clkcon_enable,
  99. .ctrlbit = S3C2410_CLKCON_SPI,
  100. }
  101. };
  102. static struct clk clk_lcd = {
  103. .name = "lcd",
  104. .parent = &clk_h,
  105. .enable = s3c2410_clkcon_enable,
  106. .ctrlbit = S3C2410_CLKCON_LCDC,
  107. };
  108. static struct clk clk_gpio = {
  109. .name = "gpio",
  110. .parent = &clk_p,
  111. .enable = s3c2410_clkcon_enable,
  112. .ctrlbit = S3C2410_CLKCON_GPIO,
  113. };
  114. static struct clk clk_usb_host = {
  115. .name = "usb-host",
  116. .parent = &clk_h,
  117. .enable = s3c2410_clkcon_enable,
  118. .ctrlbit = S3C2410_CLKCON_USBH,
  119. };
  120. static struct clk clk_usb_device = {
  121. .name = "usb-device",
  122. .parent = &clk_h,
  123. .enable = s3c2410_clkcon_enable,
  124. .ctrlbit = S3C2410_CLKCON_USBD,
  125. };
  126. static struct clk clk_timers = {
  127. .name = "timers",
  128. .parent = &clk_p,
  129. .enable = s3c2410_clkcon_enable,
  130. .ctrlbit = S3C2410_CLKCON_PWMT,
  131. };
  132. struct clk s3c24xx_clk_uart0 = {
  133. .name = "uart",
  134. .devname = "s3c2410-uart.0",
  135. .parent = &clk_p,
  136. .enable = s3c2410_clkcon_enable,
  137. .ctrlbit = S3C2410_CLKCON_UART0,
  138. };
  139. struct clk s3c24xx_clk_uart1 = {
  140. .name = "uart",
  141. .devname = "s3c2410-uart.1",
  142. .parent = &clk_p,
  143. .enable = s3c2410_clkcon_enable,
  144. .ctrlbit = S3C2410_CLKCON_UART1,
  145. };
  146. struct clk s3c24xx_clk_uart2 = {
  147. .name = "uart",
  148. .devname = "s3c2410-uart.2",
  149. .parent = &clk_p,
  150. .enable = s3c2410_clkcon_enable,
  151. .ctrlbit = S3C2410_CLKCON_UART2,
  152. };
  153. static struct clk clk_rtc = {
  154. .name = "rtc",
  155. .parent = &clk_p,
  156. .enable = s3c2410_clkcon_enable,
  157. .ctrlbit = S3C2410_CLKCON_RTC,
  158. };
  159. static struct clk clk_watchdog = {
  160. .name = "watchdog",
  161. .parent = &clk_p,
  162. .ctrlbit = 0,
  163. };
  164. static struct clk clk_usb_bus_host = {
  165. .name = "usb-bus-host",
  166. .parent = &clk_usb_bus,
  167. };
  168. static struct clk clk_usb_bus_gadget = {
  169. .name = "usb-bus-gadget",
  170. .parent = &clk_usb_bus,
  171. };
  172. static struct clk *init_clocks[] = {
  173. &clk_lcd,
  174. &clk_gpio,
  175. &clk_usb_host,
  176. &clk_usb_device,
  177. &clk_timers,
  178. &s3c24xx_clk_uart0,
  179. &s3c24xx_clk_uart1,
  180. &s3c24xx_clk_uart2,
  181. &clk_rtc,
  182. &clk_watchdog,
  183. &clk_usb_bus_host,
  184. &clk_usb_bus_gadget,
  185. };
  186. /* s3c2410_baseclk_add()
  187. *
  188. * Add all the clocks used by the s3c2410 or compatible CPUs
  189. * such as the S3C2440 and S3C2442.
  190. *
  191. * We cannot use a system device as we are needed before any
  192. * of the init-calls that initialise the devices are actually
  193. * done.
  194. */
  195. int __init s3c2410_baseclk_add(void)
  196. {
  197. unsigned long clkslow = __raw_readl(S3C2410_CLKSLOW);
  198. unsigned long clkcon = __raw_readl(S3C2410_CLKCON);
  199. struct clk *xtal;
  200. int ret;
  201. int ptr;
  202. clk_upll.enable = s3c2410_upll_enable;
  203. if (s3c24xx_register_clock(&clk_usb_bus) < 0)
  204. printk(KERN_ERR "failed to register usb bus clock\n");
  205. /* register clocks from clock array */
  206. for (ptr = 0; ptr < ARRAY_SIZE(init_clocks); ptr++) {
  207. struct clk *clkp = init_clocks[ptr];
  208. /* ensure that we note the clock state */
  209. clkp->usage = clkcon & clkp->ctrlbit ? 1 : 0;
  210. ret = s3c24xx_register_clock(clkp);
  211. if (ret < 0) {
  212. printk(KERN_ERR "Failed to register clock %s (%d)\n",
  213. clkp->name, ret);
  214. }
  215. }
  216. /* We must be careful disabling the clocks we are not intending to
  217. * be using at boot time, as subsystems such as the LCD which do
  218. * their own DMA requests to the bus can cause the system to lockup
  219. * if they where in the middle of requesting bus access.
  220. *
  221. * Disabling the LCD clock if the LCD is active is very dangerous,
  222. * and therefore the bootloader should be careful to not enable
  223. * the LCD clock if it is not needed.
  224. */
  225. /* install (and disable) the clocks we do not need immediately */
  226. s3c_register_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  227. s3c_disable_clocks(init_clocks_off, ARRAY_SIZE(init_clocks_off));
  228. /* show the clock-slow value */
  229. xtal = clk_get(NULL, "xtal");
  230. printk("CLOCK: Slow mode (%ld.%ld MHz), %s, MPLL %s, UPLL %s\n",
  231. print_mhz(clk_get_rate(xtal) /
  232. ( 2 * S3C2410_CLKSLOW_GET_SLOWVAL(clkslow))),
  233. (clkslow & S3C2410_CLKSLOW_SLOW) ? "slow" : "fast",
  234. (clkslow & S3C2410_CLKSLOW_MPLL_OFF) ? "off" : "on",
  235. (clkslow & S3C2410_CLKSLOW_UCLK_OFF) ? "off" : "on");
  236. s3c_pwmclk_init();
  237. return 0;
  238. }